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  1. # TI/Luminary Stellaris LM3S chip family
  2. # Some devices have errata in returning their device class.
  3. # DEVICECLASS is provided as a manual override
  4. # Manual setting of a device class of 0xff is not allowed
  5. global _DEVICECLASS
  6. if { [info exists DEVICECLASS] } {
  7. set _DEVICECLASS $DEVICECLASS
  8. } else {
  9. set _DEVICECLASS 0xff
  10. }
  11. # Luminary chips support both JTAG and SWD transports.
  12. # Adapt based on what transport is active.
  13. source [find target/swj-dp.tcl]
  14. # For now we ignore the SPI and UART options, which
  15. # are usable only for ISP style initial flash programming.
  16. if { [info exists CHIPNAME] } {
  17. set _CHIPNAME $CHIPNAME
  18. } else {
  19. set _CHIPNAME lm3s
  20. }
  21. # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  22. # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  23. # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  24. # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
  25. # CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
  26. # ... we'll ignore the JTAG version field, rather than list every
  27. # chip revision that turns up.
  28. if { [info exists CPUTAPID] } {
  29. set _CPUTAPID $CPUTAPID
  30. } else {
  31. set _CPUTAPID 0x0ba00477
  32. }
  33. # SWD DAP, and JTAG TAP, take same params for now;
  34. # ... even though SWD ignores all except TAPID, and
  35. # JTAG shouldn't need anything more then irlen. (and TAPID).
  36. swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  37. -expected-id $_CPUTAPID -ignore-version
  38. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  39. if { [info exists WORKAREASIZE] } {
  40. set _WORKAREASIZE $WORKAREASIZE
  41. } else {
  42. # default to 2K working area
  43. set _WORKAREASIZE 0x800
  44. }
  45. set _TARGETNAME $_CHIPNAME.cpu
  46. target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
  47. # 8K working area at base of ram, not backed up
  48. #
  49. # NOTE: you may need or want to reconfigure the work area;
  50. # some parts have just 6K, and you may want to use other
  51. # addresses (at end of mem not beginning) or back it up.
  52. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  53. # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  54. # LM3S parts don't support RTCK
  55. #
  56. # NOTE: this may be increased by a reset-init handler, after it
  57. # configures and enables the PLL. Or you might need to decrease
  58. # this, if you're using a slower clock.
  59. adapter speed 500
  60. source [find mem_helper.tcl]
  61. proc reset_peripherals {family} {
  62. source [find chip/ti/lm3s/lm3s.tcl]
  63. echo "Resetting Core Peripherals"
  64. # Disable the PLL and the system clock divider (nop if disabled)
  65. mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
  66. mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
  67. # RCC and RCC2 to their reset values
  68. mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
  69. mww $SYSCTL_RCC2 0x07806810
  70. mww $SYSCTL_RCC 0x078e3ad1
  71. # Reset the deep sleep clock configuration register
  72. mww $SYSCTL_DSLPCLKCFG 0x07800000
  73. # Reset the clock gating registers
  74. mww $SYSCTL_RCGC0 0x00000040
  75. mww $SYSCTL_RCGC1 0
  76. mww $SYSCTL_RCGC2 0
  77. mww $SYSCTL_SCGC0 0x00000040
  78. mww $SYSCTL_SCGC1 0
  79. mww $SYSCTL_SCGC2 0
  80. mww $SYSCTL_DCGC0 0x00000040
  81. mww $SYSCTL_DCGC1 0
  82. mww $SYSCTL_DCGC2 0
  83. # Reset the remaining SysCtl registers
  84. mww $SYSCTL_PBORCTL 0
  85. mww $SYSCTL_IMC 0
  86. mww $SYSCTL_GPIOHBCTL 0
  87. mww $SYSCTL_MOSCCTL 0
  88. mww $SYSCTL_PIOSCCAL 0
  89. mww $SYSCTL_I2SMCLKCFG 0
  90. # Reset the peripherals
  91. mww $SYSCTL_SRCR0 0xffffffff
  92. mww $SYSCTL_SRCR1 0xffffffff
  93. mww $SYSCTL_SRCR2 0xffffffff
  94. mww $SYSCTL_SRCR0 0
  95. mww $SYSCTL_SRCR1 0
  96. mww $SYSCTL_SRCR2 0
  97. # Clear any pending SysCtl interrupts
  98. mww $SYSCTL_MISC 0xffffffff
  99. # Wait for any pending flash operations to complete
  100. while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
  101. while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
  102. # Reset the flash controller registers
  103. mww $FLASH_FMA 0
  104. mww $FLASH_FCIM 0
  105. mww $FLASH_FCMISC 0xffffffff
  106. mww $FLASH_FWBVAL 0
  107. }
  108. $_TARGETNAME configure -event reset-start {
  109. adapter speed 500
  110. #
  111. # When nRST is asserted on most Stellaris devices, it clears some of
  112. # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
  113. # and OpenOCD depends on those TRMs. So we won't use SRST on those
  114. # chips. (Only power-on reset should affect debug state, beyond a
  115. # few specified bits; not the chip's nRST input, wired to SRST.)
  116. #
  117. # REVISIT current errata specs don't seem to cover this issue.
  118. # Do we have more details than this email?
  119. # https://lists.berlios.de/pipermail
  120. # /openocd-development/2008-August/003065.html
  121. #
  122. global _DEVICECLASS
  123. if {$_DEVICECLASS != 0xff} {
  124. set device_class $_DEVICECLASS
  125. } else {
  126. set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
  127. }
  128. if {$device_class == 0 || $device_class == 1 ||
  129. $device_class == 3 || $device_class == 5 || $device_class == 0xa} {
  130. if {![using_hla]} {
  131. # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
  132. cortex_m reset_config sysresetreq
  133. }
  134. } else {
  135. if {![using_hla]} {
  136. # Tempest and Firestorm default to using NVIC VECTRESET
  137. # peripherals will need resetting manually, see proc reset_peripherals
  138. cortex_m reset_config vectreset
  139. }
  140. # reset peripherals, based on code in
  141. # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
  142. reset_peripherals $device_class
  143. }
  144. }
  145. # flash configuration ... autodetects sizes, autoprobed
  146. flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME