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  1. # script for stm32f2x family
  2. #
  3. # stm32 devices support both JTAG and SWD transports.
  4. #
  5. source [find target/swj-dp.tcl]
  6. source [find mem_helper.tcl]
  7. if { [info exists CHIPNAME] } {
  8. set _CHIPNAME $CHIPNAME
  9. } else {
  10. set _CHIPNAME stm32f2x
  11. }
  12. set _ENDIAN little
  13. # Work-area is a space in RAM used for flash programming
  14. # By default use 64kB
  15. if { [info exists WORKAREASIZE] } {
  16. set _WORKAREASIZE $WORKAREASIZE
  17. } else {
  18. set _WORKAREASIZE 0x10000
  19. }
  20. # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  21. #
  22. # Since we may be running of an RC oscilator, we crank down the speed a
  23. # bit more to be on the safe side. Perhaps superstition, but if are
  24. # running off a crystal, we can run closer to the limit. Note
  25. # that there can be a pretty wide band where things are more or less stable.
  26. adapter speed 1000
  27. adapter srst delay 100
  28. if {[using_jtag]} {
  29. jtag_ntrst_delay 100
  30. }
  31. #jtag scan chain
  32. if { [info exists CPUTAPID] } {
  33. set _CPUTAPID $CPUTAPID
  34. } else {
  35. if { [using_jtag] } {
  36. # See STM Document RM0033
  37. # Section 32.6.3 - corresponds to Cortex-M3 r2p0
  38. set _CPUTAPID 0x4ba00477
  39. } {
  40. set _CPUTAPID 0x2ba01477
  41. }
  42. }
  43. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  44. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  45. if {[using_jtag]} {
  46. jtag newtap $_CHIPNAME bs -irlen 5
  47. }
  48. set _TARGETNAME $_CHIPNAME.cpu
  49. target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  50. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  51. set _FLASHNAME $_CHIPNAME.flash
  52. flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  53. flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
  54. reset_config srst_nogate
  55. if {![using_hla]} {
  56. # if srst is not fitted use SYSRESETREQ to
  57. # perform a soft reset
  58. cortex_m reset_config sysresetreq
  59. }
  60. $_TARGETNAME configure -event examine-end {
  61. # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  62. mmw 0xE0042004 0x00000007 0
  63. # Stop watchdog counters during halt
  64. # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  65. mmw 0xE0042008 0x00001800 0
  66. }
  67. $_TARGETNAME configure -event trace-config {
  68. # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  69. # change this value accordingly to configure trace pins
  70. # assignment
  71. mmw 0xE0042004 0x00000020 0
  72. }