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  1. # script for stm32g4x family
  2. #
  3. # stm32g4 devices support both JTAG and SWD transports.
  4. #
  5. source [find target/swj-dp.tcl]
  6. source [find mem_helper.tcl]
  7. if { [info exists CHIPNAME] } {
  8. set _CHIPNAME $CHIPNAME
  9. } else {
  10. set _CHIPNAME stm32g4x
  11. }
  12. set _ENDIAN little
  13. # Work-area is a space in RAM used for flash programming
  14. # Smallest current target has 32kB ram, use 16kB by default to avoid surprises
  15. if { [info exists WORKAREASIZE] } {
  16. set _WORKAREASIZE $WORKAREASIZE
  17. } else {
  18. set _WORKAREASIZE 0x4000
  19. }
  20. #jtag scan chain
  21. if { [info exists CPUTAPID] } {
  22. set _CPUTAPID $CPUTAPID
  23. } else {
  24. if { [using_jtag] } {
  25. # See STM Document RM0440
  26. # Section 46.6.3 - corresponds to Cortex-M4 r0p1
  27. set _CPUTAPID 0x4ba00477
  28. } {
  29. set _CPUTAPID 0x2ba01477
  30. }
  31. }
  32. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  33. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  34. if {[using_jtag]} {
  35. jtag newtap $_CHIPNAME bs -irlen 5
  36. }
  37. set _TARGETNAME $_CHIPNAME.cpu
  38. target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  39. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  40. flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  41. flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
  42. if { [info exists QUADSPI] && $QUADSPI } {
  43. set a [llength [flash list]]
  44. set _QSPINAME $_CHIPNAME.qspi
  45. flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
  46. }
  47. # reasonable default
  48. adapter speed 2000
  49. adapter srst delay 100
  50. if {[using_jtag]} {
  51. jtag_ntrst_delay 100
  52. }
  53. reset_config srst_nogate
  54. if {![using_hla]} {
  55. # if srst is not fitted use SYSRESETREQ to
  56. # perform a soft reset
  57. cortex_m reset_config sysresetreq
  58. }
  59. $_TARGETNAME configure -event reset-init {
  60. # CPU comes out of reset with HSION | HSIRDY.
  61. # Use HSI 16 MHz clock, compliant even with VOS == 2.
  62. # 1 WS compliant with VOS == 2 and 16 MHz.
  63. mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1
  64. mmw 0x40021000 0x00000100 0x00000000 ;# RCC_CR |= HSION
  65. mmw 0x40021008 0x00000001 0x00000002 ;# RCC_CFGR: SW=HSI16
  66. }
  67. $_TARGETNAME configure -event reset-start {
  68. # Reset clock is HSI (16 MHz)
  69. adapter speed 2000
  70. }
  71. $_TARGETNAME configure -event examine-end {
  72. # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  73. mmw 0xE0042004 0x00000007 0
  74. # Stop watchdog counters during halt
  75. # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
  76. mmw 0xE0042008 0x00001800 0
  77. }
  78. $_TARGETNAME configure -event trace-config {
  79. # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  80. # change this value accordingly to configure trace pins
  81. # assignment
  82. mmw 0xE0042004 0x00000020 0
  83. }