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  1. #
  2. # M0+ devices only have SW-DP, but swj-dp code works, just don't
  3. # set any jtag related features
  4. #
  5. source [find target/swj-dp.tcl]
  6. source [find mem_helper.tcl]
  7. if { [info exists CHIPNAME] } {
  8. set _CHIPNAME $CHIPNAME
  9. } else {
  10. set _CHIPNAME stm32l0
  11. }
  12. set _ENDIAN little
  13. # Work-area is a space in RAM used for flash programming
  14. # By default use 2kB (max ram on smallest part)
  15. if { [info exists WORKAREASIZE] } {
  16. set _WORKAREASIZE $WORKAREASIZE
  17. } else {
  18. set _WORKAREASIZE 0x800
  19. }
  20. # JTAG speed should be <= F_CPU/6.
  21. # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
  22. adapter speed 300
  23. adapter srst delay 100
  24. if { [info exists CPUTAPID] } {
  25. set _CPUTAPID $CPUTAPID
  26. } else {
  27. # Arm, m0+, non-multidrop.
  28. # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
  29. set _CPUTAPID 0x0bc11477
  30. }
  31. swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
  32. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  33. set _TARGETNAME $_CHIPNAME.cpu
  34. target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  35. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  36. # flash size will be probed
  37. set _FLASHNAME $_CHIPNAME.flash
  38. flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  39. reset_config srst_nogate
  40. if {![using_hla]} {
  41. # if srst is not fitted use SYSRESETREQ to
  42. # perform a soft reset
  43. cortex_m reset_config sysresetreq
  44. }
  45. proc stm32l0_enable_HSI16 {} {
  46. # Enable HSI16 as clock source
  47. echo "STM32L0: Enabling HSI16"
  48. # Set HSI16ON in RCC_CR (leave MSI enabled)
  49. mmw 0x40021000 0x00000101 0
  50. # Set HSI16 as SYSCLK (RCC_CFGR)
  51. mmw 0x4002100c 0x00000001 0
  52. # Wait until System clock switches to HSI16
  53. while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
  54. # Increase speed
  55. adapter speed 2500
  56. }
  57. $_TARGETNAME configure -event reset-init {
  58. stm32l0_enable_HSI16
  59. }
  60. $_TARGETNAME configure -event reset-start {
  61. adapter speed 300
  62. }
  63. $_TARGETNAME configure -event examine-end {
  64. # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  65. mmw 0x40015804 0x00000007 0
  66. # Stop watchdog counters during halt
  67. # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  68. mmw 0x40015808 0x00001800 0
  69. }