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  1. # script for stm32wlx family
  2. #
  3. # stm32wl devices support both JTAG and SWD transports.
  4. #
  5. source [find target/swj-dp.tcl]
  6. source [find mem_helper.tcl]
  7. if { [info exists CHIPNAME] } {
  8. set _CHIPNAME $CHIPNAME
  9. } else {
  10. set _CHIPNAME stm32wlx
  11. }
  12. set _ENDIAN little
  13. # Work-area is a space in RAM used for flash programming
  14. # By default use 20kB
  15. if { [info exists WORKAREASIZE] } {
  16. set _WORKAREASIZE $WORKAREASIZE
  17. } else {
  18. set _WORKAREASIZE 0x5000
  19. }
  20. #jtag scan chain
  21. if { [info exists CPUTAPID] } {
  22. set _CPUTAPID $CPUTAPID
  23. } else {
  24. if { [using_jtag] } {
  25. set _CPUTAPID 0x6ba00477
  26. } else {
  27. # SWD IDCODE (single drop, arm)
  28. set _CPUTAPID 0x6ba02477
  29. }
  30. }
  31. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  32. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  33. if {[using_jtag]} {
  34. jtag newtap $_CHIPNAME bs -irlen 5
  35. }
  36. set _TARGETNAME $_CHIPNAME.cpu
  37. target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  38. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  39. flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  40. flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
  41. # Common knowledges tells JTAG speed should be <= F_CPU/6.
  42. # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  43. # the safe side.
  44. #
  45. # Note that there is a pretty wide band where things are
  46. # more or less stable, see http://openocd.zylin.com/#/c/3366/
  47. adapter speed 500
  48. adapter srst delay 100
  49. if {[using_jtag]} {
  50. jtag_ntrst_delay 100
  51. }
  52. reset_config srst_nogate
  53. if {![using_hla]} {
  54. # if srst is not fitted use SYSRESETREQ to
  55. # perform a soft reset
  56. cortex_m reset_config sysresetreq
  57. }
  58. $_TARGETNAME configure -event reset-init {
  59. # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
  60. # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
  61. # 2 WS compliant with VOS=Range1 and 24 MHz.
  62. mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
  63. mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
  64. # Boost JTAG frequency
  65. adapter speed 4000
  66. }
  67. $_TARGETNAME configure -event reset-start {
  68. # Reset clock is MSI (4 MHz)
  69. adapter speed 500
  70. }
  71. $_TARGETNAME configure -event examine-end {
  72. # Enable debug during low power modes (uses more power)
  73. # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  74. mmw 0xE0042004 0x00000007 0
  75. # Stop watchdog counters during halt
  76. # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
  77. mmw 0xE004203C 0x00001800 0
  78. }
  79. $_TARGETNAME configure -event trace-config {
  80. # nothing to do
  81. }