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  1. /** @page primerjtag OpenOCD JTAG Primer
  2. JTAG is unnecessarily confusing, because JTAG is often confused with
  3. boundary scan, which is just one of its possible functions.
  4. JTAG is simply a communication interface designed to allow communication
  5. to functions contained on devices, for the designed purposes of
  6. initialisation, programming, testing, debugging, and anything else you
  7. want to use it for (as a chip designer).
  8. Think of JTAG as I2C for testing. It doesn't define what it can do,
  9. just a logical interface that allows a uniform channel for communication.
  10. See @par
  11. http://en.wikipedia.org/wiki/Joint_Test_Action_Group
  12. @image html jtag-state-machine-large.png
  13. The first page (among other things) shows a logical representation
  14. describing how multiple devices are wired up using JTAG. JTAG does not
  15. specify, data rates or interface levels (3.3V/1.8V, etc) each device can
  16. support different data rates/interface logic levels. How to wire them
  17. in a compatible way is an exercise for an engineer.
  18. Basically TMS controls which shift register is placed on the device,
  19. between TDI and TDO. The second diagram shows the state transitions on
  20. TMS which will select different shift registers.
  21. The first thing you need to do is reset the state machine, because when
  22. you connect to a chip you do not know what state the controller is in,you need
  23. to clock TMS as 1, at least 5 times. This will put you into "Test Logic
  24. Reset" State. Knowing this, you can, once reset, then track what each
  25. transition on TMS will do, and hence know what state the JTAG state
  26. machine is in.
  27. There are 2 "types" of shift registers. The Instruction shift register
  28. and the data shift register. The sizes of these are undefined, and can
  29. change from chip to chip. The Instruction register is used to select
  30. which Data register/data register function is used, and the data
  31. register is used to read data from that function or write data to it.
  32. Each of the states control what happens to either the data register or
  33. instruction register.
  34. For example, one of the data registers will be known as "bypass" this is
  35. (usually) a single bit which has no function and is used to bypass the
  36. chip. Assume we have 3 identical chips, wired up like the picture(wikipedia)
  37. and each has a 3 bits instruction register, and there are 2 known
  38. instructions (110 = bypass, 010 = "some other function") if we want to use
  39. "some other function", on the second chip in the line, and not change
  40. the other chips we would do the following transitions.
  41. From Test Logic Reset, TMS goes:
  42. 0 1 1 0 0
  43. which puts every chip in the chain into the "Shift IR state"
  44. Then (while holding TMS as 0) TDI goes:
  45. 0 1 1 0 1 0 0 1 1
  46. which puts the following values in the instruction shift register for
  47. each chip [110] [010] [110]
  48. The order is reversed, because we shift out the least significant bit
  49. first. Then we transition TMS:
  50. 1 1 1 0 0
  51. which puts us in the "Shift DR state".
  52. Now when we clock data onto TDI (again while holding TMS to 0) , the
  53. data shifts through the data registers, and because of the instruction
  54. registers we selected ("some other function" has 8 bits in its data
  55. register), our total data register in the chain looks like this:
  56. 0 00000000 0
  57. The first and last bit are in the "bypassed" chips, so values read from
  58. them are irrelevant and data written to them is ignored. But we need to
  59. write bits for those registers, because they are in the chain.
  60. If we wanted to write 0xF5 to the data register we would clock out of
  61. TDI (holding TMS to 0):
  62. 0 1 0 1 0 1 1 1 1 0
  63. Again, we are clocking the least-significant bit first. Then we would
  64. clock TMS:
  65. 1 1 0
  66. which updates the selected data register with the value 0xF5 and returns
  67. us to run test idle.
  68. If we needed to read the data register before over-writing it with F5,
  69. no sweat, that's already done, because the TDI/TDO are set up as a
  70. circular shift register, so if you write enough bits to fill the shift
  71. register, you will receive the "captured" contents of the data registers
  72. simultaneously on TDO.
  73. That's JTAG in a nutshell. On top of this, you need to get specs for
  74. target chips and work out what the various instruction registers/data
  75. registers do, so you can actually do something useful. That's where it
  76. gets interesting. But in and of itself, JTAG is actually very simple.
  77. @section primerjtag More Reading
  78. A separate primer contains information about @subpage primerjtagbs for
  79. developers that want to extend OpenOCD for such purposes.
  80. */
  81. /** @page primerjtagbs JTAG Boundary Scan Primer
  82. The following page provides an introduction on JTAG that focuses on its
  83. boundary scan capabilities: @par
  84. http://www.engr.udayton.edu/faculty/jloomis/ece446/notes/jtag/jtag1.html
  85. OpenOCD does not presently have clear means of using JTAG for boundary
  86. scan testing purposes; however, some developers have explored the
  87. possibilities. The page contains information that may be useful to
  88. those wishing to implement boundary scan capabilities in OpenOCD.
  89. @section primerbsdl The BSDL Language
  90. For more information on the Boundary Scan Description Language (BSDL),
  91. the following page provides a good introduction: @par
  92. http://www.radio-electronics.com/info/t_and_m/boundaryscan/bsdl.php
  93. @section primerbsdlvendors Vendor BSDL Files
  94. NXP LPC: @par
  95. http://www.standardics.nxp.com/support/models/lpc2000/
  96. Freescale PowerPC: @par
  97. http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCBSDLFLS
  98. Freescale i.MX1 (too old): @par
  99. http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX1&nodeId=0162468rH311432973ZrDR&fpsp=1&tab=Design_Tools_Tab
  100. Renesas R32C/117: @par
  101. http://sg.renesas.com/fmwk.jsp?cnt=r32c116_7_8_root.jsp&fp=/products/mpumcu/m16c_family/r32c100_series/r32c116_7_8_group/
  102. - The device page does not come with BSDL file; you have to register to
  103. download them. @par
  104. http://www.corelis.com/support/BSDL.htm
  105. TI links theirs right off the generic page for each chip;
  106. this may be the case for other vendors as well. For example:
  107. - DaVinci DM355 -- http://www.ti.com/litv/zip/sprm262b
  108. - DaVinci DM6446
  109. - 2.1 silicon -- http://www.ti.com/litv/zip/sprm325a
  110. - older silicon -- http://www.ti.com/litv/zip/sprm203
  111. - OMAP 3530
  112. - CBB package -- http://www.ti.com/litv/zip/sprm315b
  113. - 515 ball s-PGBA, POP, 0.4mm pitch
  114. - CUS package -- http://www.ti.com/litv/zip/sprm314a
  115. - 515 ball s-PGBA, POP, 0.5mm pitch
  116. - CBC package -- http://www.ti.com/litv/zip/sprm346
  117. - 423 ball s-PGBA, 0.65mm pitch
  118. Many other files are available in the "Semiconductor Manufacturer's BSDL
  119. files" section of the following site: @par
  120. http://www.freelabs.com/~whitis/electronics/jtag/
  121. */
  122. /** @file
  123. This file contains the @ref primerjtag and @ref primerjtagbs page.
  124. */