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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  21. ***************************************************************************/
  22. #ifndef MIPS32_H
  23. #define MIPS32_H
  24. #include "target.h"
  25. #include "mips32_pracc.h"
  26. #define MIPS32_COMMON_MAGIC 0xB320B320
  27. /* offsets into mips32 core register cache */
  28. enum
  29. {
  30. MIPS32_PC = 37,
  31. MIPS32NUMCOREREGS
  32. };
  33. struct mips32_comparator
  34. {
  35. int used;
  36. //int type;
  37. uint32_t bp_value;
  38. uint32_t reg_address;
  39. };
  40. struct mips32_common
  41. {
  42. uint32_t common_magic;
  43. void *arch_info;
  44. struct reg_cache *core_cache;
  45. struct mips_ejtag ejtag_info;
  46. uint32_t core_regs[MIPS32NUMCOREREGS];
  47. int bp_scanned;
  48. int num_inst_bpoints;
  49. int num_data_bpoints;
  50. int num_inst_bpoints_avail;
  51. int num_data_bpoints_avail;
  52. struct mips32_comparator *inst_break_list;
  53. struct mips32_comparator *data_break_list;
  54. /* register cache to processor synchronization */
  55. int (*read_core_reg)(struct target *target, int num);
  56. int (*write_core_reg)(struct target *target, int num);
  57. };
  58. struct mips32_core_reg
  59. {
  60. uint32_t num;
  61. struct target *target;
  62. struct mips32_common *mips32_common;
  63. };
  64. #define MIPS32_OP_BEQ 0x04
  65. #define MIPS32_OP_BNE 0x05
  66. #define MIPS32_OP_ADDI 0x08
  67. #define MIPS32_OP_AND 0x24
  68. #define MIPS32_OP_COP0 0x10
  69. #define MIPS32_OP_JR 0x08
  70. #define MIPS32_OP_LUI 0x0F
  71. #define MIPS32_OP_LW 0x23
  72. #define MIPS32_OP_LBU 0x24
  73. #define MIPS32_OP_LHU 0x25
  74. #define MIPS32_OP_MFHI 0x10
  75. #define MIPS32_OP_MTHI 0x11
  76. #define MIPS32_OP_MFLO 0x12
  77. #define MIPS32_OP_MTLO 0x13
  78. #define MIPS32_OP_SB 0x28
  79. #define MIPS32_OP_SH 0x29
  80. #define MIPS32_OP_SW 0x2B
  81. #define MIPS32_OP_ORI 0x0D
  82. #define MIPS32_COP0_MF 0x00
  83. #define MIPS32_COP0_MT 0x04
  84. #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
  85. #define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
  86. #define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
  87. #define MIPS32_NOP 0
  88. #define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
  89. #define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
  90. #define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
  91. #define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
  92. #define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
  93. #define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
  94. #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
  95. #define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
  96. #define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
  97. #define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
  98. #define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
  99. #define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
  100. #define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
  101. #define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
  102. #define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
  103. #define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
  104. #define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
  105. #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
  106. #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
  107. #define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
  108. /* ejtag specific instructions */
  109. #define MIPS32_DRET 0x4200001F
  110. #define MIPS32_SDBBP 0x7000003F
  111. #define MIPS16_SDBBP 0xE801
  112. int mips32_arch_state(struct target *target);
  113. int mips32_init_arch_info(struct target *target,
  114. struct mips32_common *mips32, struct jtag_tap *tap);
  115. int mips32_restore_context(struct target *target);
  116. int mips32_save_context(struct target *target);
  117. struct reg_cache *mips32_build_reg_cache(struct target *target);
  118. int mips32_run_algorithm(struct target *target,
  119. int num_mem_params, struct mem_param *mem_params,
  120. int num_reg_params, struct reg_param *reg_params,
  121. uint32_t entry_point, uint32_t exit_point,
  122. int timeout_ms, void *arch_info);
  123. int mips32_configure_break_unit(struct target *target);
  124. int mips32_enable_interrupts(struct target *target, int enable);
  125. int mips32_examine(struct target *target);
  126. int mips32_register_commands(struct command_context *cmd_ctx);
  127. int mips32_get_gdb_reg_list(struct target *target,
  128. struct reg **reg_list[], int *reg_list_size);
  129. #endif /*MIPS32_H*/