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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "mips32.h"
  28. #include "mips_ejtag.h"
  29. int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
  30. {
  31. struct jtag_tap *tap;
  32. tap = ejtag_info->tap;
  33. if (tap == NULL)
  34. return ERROR_FAIL;
  35. if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr)
  36. {
  37. struct scan_field field;
  38. uint8_t t[4];
  39. field.tap = tap;
  40. field.num_bits = tap->ir_length;
  41. field.out_value = t;
  42. buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  43. field.in_value = NULL;
  44. jtag_add_ir_scan(1, &field, jtag_get_end_state());
  45. }
  46. return ERROR_OK;
  47. }
  48. int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
  49. {
  50. struct scan_field field;
  51. jtag_set_end_state(TAP_IDLE);
  52. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
  53. field.tap = ejtag_info->tap;
  54. field.num_bits = 32;
  55. field.out_value = NULL;
  56. field.in_value = (void*)idcode;
  57. jtag_add_dr_scan(1, &field, jtag_get_end_state());
  58. if (jtag_execute_queue() != ERROR_OK)
  59. {
  60. LOG_ERROR("register read failed");
  61. }
  62. return ERROR_OK;
  63. }
  64. int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
  65. {
  66. struct scan_field field;
  67. jtag_set_end_state(TAP_IDLE);
  68. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
  69. field.tap = ejtag_info->tap;
  70. field.num_bits = 32;
  71. field.out_value = NULL;
  72. field.in_value = (void*)impcode;
  73. jtag_add_dr_scan(1, &field, jtag_get_end_state());
  74. if (jtag_execute_queue() != ERROR_OK)
  75. {
  76. LOG_ERROR("register read failed");
  77. }
  78. return ERROR_OK;
  79. }
  80. int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
  81. {
  82. struct jtag_tap *tap;
  83. tap = ejtag_info->tap;
  84. if (tap == NULL)
  85. return ERROR_FAIL;
  86. struct scan_field field;
  87. uint8_t t[4], r[4];
  88. int retval;
  89. field.tap = tap;
  90. field.num_bits = 32;
  91. field.out_value = t;
  92. buf_set_u32(field.out_value, 0, field.num_bits, *data);
  93. field.in_value = r;
  94. jtag_add_dr_scan(1, &field, jtag_get_end_state());
  95. if ((retval = jtag_execute_queue()) != ERROR_OK)
  96. {
  97. LOG_ERROR("register read failed");
  98. return retval;
  99. }
  100. *data = buf_get_u32(field.in_value, 0, 32);
  101. keep_alive();
  102. return ERROR_OK;
  103. }
  104. int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
  105. {
  106. uint32_t code[] = {
  107. MIPS32_MTC0(1,31,0), /* move $1 to COP0 DeSave */
  108. MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
  109. MIPS32_ORI(1,1,0x0100), /* set SSt bit in debug reg */
  110. MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */
  111. MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */
  112. MIPS32_NOP,
  113. MIPS32_B(NEG16(7)),
  114. MIPS32_NOP,
  115. };
  116. mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
  117. 0, NULL, 0, NULL, 1);
  118. return ERROR_OK;
  119. }
  120. int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
  121. {
  122. uint32_t code[] = {
  123. MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
  124. MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
  125. MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
  126. MIPS32_SW(1,0,15), /* sw $1,($15) */
  127. MIPS32_SW(2,0,15), /* sw $2,($15) */
  128. MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
  129. MIPS32_LUI(2,0xFFFF), /* $2 = 0xfffffeff */
  130. MIPS32_ORI(2,2,0xFEFF),
  131. MIPS32_AND(1,1,2),
  132. MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */
  133. MIPS32_LW(2,0,15),
  134. MIPS32_LW(1,0,15),
  135. MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
  136. MIPS32_NOP,
  137. MIPS32_B(NEG16(15)),
  138. MIPS32_NOP,
  139. };
  140. mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
  141. 0, NULL, 0, NULL, 1);
  142. return ERROR_OK;
  143. }
  144. int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
  145. {
  146. if (enable_step)
  147. return mips_ejtag_step_enable(ejtag_info);
  148. return mips_ejtag_step_disable(ejtag_info);
  149. }
  150. int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
  151. {
  152. uint32_t ejtag_ctrl;
  153. jtag_set_end_state(TAP_IDLE);
  154. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  155. /* set debug break bit */
  156. ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
  157. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  158. /* break bit will be cleared by hardware */
  159. ejtag_ctrl = ejtag_info->ejtag_ctrl;
  160. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  161. LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
  162. if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
  163. LOG_DEBUG("Failed to enter Debug Mode!");
  164. return ERROR_OK;
  165. }
  166. int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
  167. {
  168. uint32_t inst;
  169. inst = MIPS32_DRET;
  170. /* execute our dret instruction */
  171. mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
  172. return ERROR_OK;
  173. }
  174. int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
  175. {
  176. /* read ejtag ECR */
  177. uint32_t code[] = {
  178. MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
  179. MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
  180. MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
  181. MIPS32_SW(1,0,15), /* sw $1,($15) */
  182. MIPS32_SW(2,0,15), /* sw $2,($15) */
  183. MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */
  184. MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
  185. MIPS32_MFC0(2,23,0), /* move COP0 Debug to $2 */
  186. MIPS32_SW(2,0,1),
  187. MIPS32_LW(2,0,15),
  188. MIPS32_LW(1,0,15),
  189. MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
  190. MIPS32_NOP,
  191. MIPS32_B(NEG16(14)),
  192. MIPS32_NOP,
  193. };
  194. mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
  195. 0, NULL, 1, debug_reg, 1);
  196. return ERROR_OK;
  197. }
  198. int mips_ejtag_init(struct mips_ejtag *ejtag_info)
  199. {
  200. uint32_t ejtag_version;
  201. mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
  202. LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
  203. /* get ejtag version */
  204. ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
  205. switch (ejtag_version)
  206. {
  207. case 0:
  208. LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
  209. break;
  210. case 1:
  211. LOG_DEBUG("EJTAG: Version 2.5 Detected");
  212. break;
  213. case 2:
  214. LOG_DEBUG("EJTAG: Version 2.6 Detected");
  215. break;
  216. case 3:
  217. LOG_DEBUG("EJTAG: Version 3.1 Detected");
  218. break;
  219. default:
  220. LOG_DEBUG("EJTAG: Unknown Version Detected");
  221. break;
  222. }
  223. LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
  224. ejtag_info->impcode & (1 << 28) ? " R3k": " R4k",
  225. ejtag_info->impcode & (1 << 24) ? " DINT": "",
  226. ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
  227. ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
  228. ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
  229. ejtag_info->impcode & (1 << 14) ? " noDMA": " DMA",
  230. ejtag_info->impcode & (1 << 0) ? " MIPS64": " MIPS32"
  231. );
  232. if ((ejtag_info->impcode & (1 << 14)) == 0)
  233. LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
  234. /* set initial state for ejtag control reg */
  235. ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
  236. return ERROR_OK;
  237. }
  238. int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data)
  239. {
  240. struct jtag_tap *tap;
  241. tap = ejtag_info->tap;
  242. if (tap == NULL)
  243. return ERROR_FAIL;
  244. struct scan_field fields[2];
  245. uint8_t spracc = 0;
  246. uint8_t t[4] = {0, 0, 0, 0};
  247. /* fastdata 1-bit register */
  248. fields[0].tap = tap;
  249. fields[0].num_bits = 1;
  250. fields[0].out_value = &spracc;
  251. fields[0].in_value = NULL;
  252. /* processor access data register 32 bit */
  253. fields[1].tap = tap;
  254. fields[1].num_bits = 32;
  255. fields[1].out_value = t;
  256. if (write)
  257. {
  258. fields[1].in_value = NULL;
  259. buf_set_u32(t, 0, 32, *data);
  260. }
  261. else
  262. {
  263. fields[1].in_value = (uint8_t *) data;
  264. }
  265. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  266. keep_alive();
  267. return ERROR_OK;
  268. }