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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "breakpoints.h"
  28. #include "mips32.h"
  29. #include "mips_m4k.h"
  30. #include "mips32_dmaacc.h"
  31. #include "target_type.h"
  32. #include "register.h"
  33. /* cli handling */
  34. /* forward declarations */
  35. int mips_m4k_poll(struct target *target);
  36. int mips_m4k_halt(struct target *target);
  37. int mips_m4k_soft_reset_halt(struct target *target);
  38. int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
  39. int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
  40. int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  41. int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  42. int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target);
  43. int mips_m4k_target_create(struct target *target, Jim_Interp *interp);
  44. int mips_m4k_examine(struct target *target);
  45. int mips_m4k_assert_reset(struct target *target);
  46. int mips_m4k_deassert_reset(struct target *target);
  47. int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum);
  48. struct target_type mips_m4k_target =
  49. {
  50. .name = "mips_m4k",
  51. .poll = mips_m4k_poll,
  52. .arch_state = mips32_arch_state,
  53. .target_request_data = NULL,
  54. .halt = mips_m4k_halt,
  55. .resume = mips_m4k_resume,
  56. .step = mips_m4k_step,
  57. .assert_reset = mips_m4k_assert_reset,
  58. .deassert_reset = mips_m4k_deassert_reset,
  59. .soft_reset_halt = mips_m4k_soft_reset_halt,
  60. .get_gdb_reg_list = mips32_get_gdb_reg_list,
  61. .read_memory = mips_m4k_read_memory,
  62. .write_memory = mips_m4k_write_memory,
  63. .bulk_write_memory = mips_m4k_bulk_write_memory,
  64. .checksum_memory = mips_m4k_checksum_memory,
  65. .blank_check_memory = NULL,
  66. .run_algorithm = mips32_run_algorithm,
  67. .add_breakpoint = mips_m4k_add_breakpoint,
  68. .remove_breakpoint = mips_m4k_remove_breakpoint,
  69. .add_watchpoint = mips_m4k_add_watchpoint,
  70. .remove_watchpoint = mips_m4k_remove_watchpoint,
  71. .target_create = mips_m4k_target_create,
  72. .init_target = mips_m4k_init_target,
  73. .examine = mips_m4k_examine,
  74. };
  75. int mips_m4k_examine_debug_reason(struct target *target)
  76. {
  77. uint32_t break_status;
  78. int retval;
  79. if ((target->debug_reason != DBG_REASON_DBGRQ)
  80. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  81. {
  82. /* get info about inst breakpoint support */
  83. if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
  84. return retval;
  85. if (break_status & 0x1f)
  86. {
  87. /* we have halted on a breakpoint */
  88. if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
  89. return retval;
  90. target->debug_reason = DBG_REASON_BREAKPOINT;
  91. }
  92. /* get info about data breakpoint support */
  93. if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
  94. return retval;
  95. if (break_status & 0x1f)
  96. {
  97. /* we have halted on a breakpoint */
  98. if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
  99. return retval;
  100. target->debug_reason = DBG_REASON_WATCHPOINT;
  101. }
  102. }
  103. return ERROR_OK;
  104. }
  105. int mips_m4k_debug_entry(struct target *target)
  106. {
  107. struct mips32_common *mips32 = target->arch_info;
  108. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  109. uint32_t debug_reg;
  110. /* read debug register */
  111. mips_ejtag_read_debug(ejtag_info, &debug_reg);
  112. /* make sure break uit configured */
  113. mips32_configure_break_unit(target);
  114. /* attempt to find halt reason */
  115. mips_m4k_examine_debug_reason(target);
  116. /* clear single step if active */
  117. if (debug_reg & EJTAG_DEBUG_DSS)
  118. {
  119. /* stopped due to single step - clear step bit */
  120. mips_ejtag_config_step(ejtag_info, 0);
  121. }
  122. mips32_save_context(target);
  123. LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
  124. *(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
  125. target_state_name(target));
  126. return ERROR_OK;
  127. }
  128. int mips_m4k_poll(struct target *target)
  129. {
  130. int retval;
  131. struct mips32_common *mips32 = target->arch_info;
  132. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  133. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
  134. /* read ejtag control reg */
  135. jtag_set_end_state(TAP_IDLE);
  136. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  137. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  138. /* clear this bit before handling polling
  139. * as after reset registers will read zero */
  140. if (ejtag_ctrl & EJTAG_CTRL_ROCC)
  141. {
  142. /* we have detected a reset, clear flag
  143. * otherwise ejtag will not work */
  144. jtag_set_end_state(TAP_IDLE);
  145. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
  146. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  147. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  148. LOG_DEBUG("Reset Detected");
  149. }
  150. /* check for processor halted */
  151. if (ejtag_ctrl & EJTAG_CTRL_BRKST)
  152. {
  153. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
  154. {
  155. jtag_set_end_state(TAP_IDLE);
  156. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
  157. target->state = TARGET_HALTED;
  158. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  159. return retval;
  160. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  161. }
  162. else if (target->state == TARGET_DEBUG_RUNNING)
  163. {
  164. target->state = TARGET_HALTED;
  165. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  166. return retval;
  167. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  168. }
  169. }
  170. else
  171. {
  172. target->state = TARGET_RUNNING;
  173. }
  174. // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
  175. return ERROR_OK;
  176. }
  177. int mips_m4k_halt(struct target *target)
  178. {
  179. struct mips32_common *mips32 = target->arch_info;
  180. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  181. LOG_DEBUG("target->state: %s",
  182. target_state_name(target));
  183. if (target->state == TARGET_HALTED)
  184. {
  185. LOG_DEBUG("target was already halted");
  186. return ERROR_OK;
  187. }
  188. if (target->state == TARGET_UNKNOWN)
  189. {
  190. LOG_WARNING("target was in unknown state when halt was requested");
  191. }
  192. if (target->state == TARGET_RESET)
  193. {
  194. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  195. {
  196. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  197. return ERROR_TARGET_FAILURE;
  198. }
  199. else
  200. {
  201. /* we came here in a reset_halt or reset_init sequence
  202. * debug entry was already prepared in mips32_prepare_reset_halt()
  203. */
  204. target->debug_reason = DBG_REASON_DBGRQ;
  205. return ERROR_OK;
  206. }
  207. }
  208. /* break processor */
  209. mips_ejtag_enter_debug(ejtag_info);
  210. target->debug_reason = DBG_REASON_DBGRQ;
  211. return ERROR_OK;
  212. }
  213. int mips_m4k_assert_reset(struct target *target)
  214. {
  215. struct mips32_common *mips32 = target->arch_info;
  216. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  217. LOG_DEBUG("target->state: %s",
  218. target_state_name(target));
  219. enum reset_types jtag_reset_config = jtag_get_reset_config();
  220. if (!(jtag_reset_config & RESET_HAS_SRST))
  221. {
  222. LOG_ERROR("Can't assert SRST");
  223. return ERROR_FAIL;
  224. }
  225. if (target->reset_halt)
  226. {
  227. /* use hardware to catch reset */
  228. jtag_set_end_state(TAP_IDLE);
  229. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
  230. }
  231. else
  232. {
  233. jtag_set_end_state(TAP_IDLE);
  234. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
  235. }
  236. if (strcmp(target->variant, "ejtag_srst") == 0)
  237. {
  238. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
  239. LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
  240. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  241. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  242. }
  243. else
  244. {
  245. /* here we should issue a srst only, but we may have to assert trst as well */
  246. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  247. {
  248. jtag_add_reset(1, 1);
  249. }
  250. else
  251. {
  252. jtag_add_reset(0, 1);
  253. }
  254. }
  255. target->state = TARGET_RESET;
  256. jtag_add_sleep(50000);
  257. register_cache_invalidate(mips32->core_cache);
  258. if (target->reset_halt)
  259. {
  260. int retval;
  261. if ((retval = target_halt(target)) != ERROR_OK)
  262. return retval;
  263. }
  264. return ERROR_OK;
  265. }
  266. int mips_m4k_deassert_reset(struct target *target)
  267. {
  268. LOG_DEBUG("target->state: %s",
  269. target_state_name(target));
  270. /* deassert reset lines */
  271. jtag_add_reset(0, 0);
  272. return ERROR_OK;
  273. }
  274. int mips_m4k_soft_reset_halt(struct target *target)
  275. {
  276. /* TODO */
  277. return ERROR_OK;
  278. }
  279. int mips_m4k_single_step_core(struct target *target)
  280. {
  281. struct mips32_common *mips32 = target->arch_info;
  282. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  283. /* configure single step mode */
  284. mips_ejtag_config_step(ejtag_info, 1);
  285. /* disable interrupts while stepping */
  286. mips32_enable_interrupts(target, 0);
  287. /* exit debug mode */
  288. mips_ejtag_exit_debug(ejtag_info);
  289. mips_m4k_debug_entry(target);
  290. return ERROR_OK;
  291. }
  292. int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
  293. {
  294. struct mips32_common *mips32 = target->arch_info;
  295. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  296. struct breakpoint *breakpoint = NULL;
  297. uint32_t resume_pc;
  298. if (target->state != TARGET_HALTED)
  299. {
  300. LOG_WARNING("target not halted");
  301. return ERROR_TARGET_NOT_HALTED;
  302. }
  303. if (!debug_execution)
  304. {
  305. target_free_all_working_areas(target);
  306. mips_m4k_enable_breakpoints(target);
  307. mips_m4k_enable_watchpoints(target);
  308. }
  309. /* current = 1: continue on current pc, otherwise continue at <address> */
  310. if (!current)
  311. {
  312. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  313. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  314. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  315. }
  316. resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
  317. mips32_restore_context(target);
  318. /* the front-end may request us not to handle breakpoints */
  319. if (handle_breakpoints)
  320. {
  321. /* Single step past breakpoint at current address */
  322. if ((breakpoint = breakpoint_find(target, resume_pc)))
  323. {
  324. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  325. mips_m4k_unset_breakpoint(target, breakpoint);
  326. mips_m4k_single_step_core(target);
  327. mips_m4k_set_breakpoint(target, breakpoint);
  328. }
  329. }
  330. /* enable interrupts if we are running */
  331. mips32_enable_interrupts(target, !debug_execution);
  332. /* exit debug mode */
  333. mips_ejtag_exit_debug(ejtag_info);
  334. target->debug_reason = DBG_REASON_NOTHALTED;
  335. /* registers are now invalid */
  336. register_cache_invalidate(mips32->core_cache);
  337. if (!debug_execution)
  338. {
  339. target->state = TARGET_RUNNING;
  340. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  341. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  342. }
  343. else
  344. {
  345. target->state = TARGET_DEBUG_RUNNING;
  346. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  347. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  348. }
  349. return ERROR_OK;
  350. }
  351. int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
  352. {
  353. /* get pointers to arch-specific information */
  354. struct mips32_common *mips32 = target->arch_info;
  355. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  356. struct breakpoint *breakpoint = NULL;
  357. if (target->state != TARGET_HALTED)
  358. {
  359. LOG_WARNING("target not halted");
  360. return ERROR_TARGET_NOT_HALTED;
  361. }
  362. /* current = 1: continue on current pc, otherwise continue at <address> */
  363. if (!current)
  364. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  365. /* the front-end may request us not to handle breakpoints */
  366. if (handle_breakpoints)
  367. if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
  368. mips_m4k_unset_breakpoint(target, breakpoint);
  369. /* restore context */
  370. mips32_restore_context(target);
  371. /* configure single step mode */
  372. mips_ejtag_config_step(ejtag_info, 1);
  373. target->debug_reason = DBG_REASON_SINGLESTEP;
  374. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  375. /* disable interrupts while stepping */
  376. mips32_enable_interrupts(target, 0);
  377. /* exit debug mode */
  378. mips_ejtag_exit_debug(ejtag_info);
  379. /* registers are now invalid */
  380. register_cache_invalidate(mips32->core_cache);
  381. if (breakpoint)
  382. mips_m4k_set_breakpoint(target, breakpoint);
  383. LOG_DEBUG("target stepped ");
  384. mips_m4k_debug_entry(target);
  385. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  386. return ERROR_OK;
  387. }
  388. void mips_m4k_enable_breakpoints(struct target *target)
  389. {
  390. struct breakpoint *breakpoint = target->breakpoints;
  391. /* set any pending breakpoints */
  392. while (breakpoint)
  393. {
  394. if (breakpoint->set == 0)
  395. mips_m4k_set_breakpoint(target, breakpoint);
  396. breakpoint = breakpoint->next;
  397. }
  398. }
  399. int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
  400. {
  401. struct mips32_common *mips32 = target->arch_info;
  402. struct mips32_comparator * comparator_list = mips32->inst_break_list;
  403. int retval;
  404. if (breakpoint->set)
  405. {
  406. LOG_WARNING("breakpoint already set");
  407. return ERROR_OK;
  408. }
  409. if (breakpoint->type == BKPT_HARD)
  410. {
  411. int bp_num = 0;
  412. while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
  413. bp_num++;
  414. if (bp_num >= mips32->num_inst_bpoints)
  415. {
  416. LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
  417. breakpoint->unique_id );
  418. return ERROR_FAIL;
  419. }
  420. breakpoint->set = bp_num + 1;
  421. comparator_list[bp_num].used = 1;
  422. comparator_list[bp_num].bp_value = breakpoint->address;
  423. target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
  424. target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
  425. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
  426. LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
  427. breakpoint->unique_id,
  428. bp_num, comparator_list[bp_num].bp_value);
  429. }
  430. else if (breakpoint->type == BKPT_SOFT)
  431. {
  432. LOG_DEBUG("bpid: %d", breakpoint->unique_id );
  433. if (breakpoint->length == 4)
  434. {
  435. uint32_t verify = 0xffffffff;
  436. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
  437. {
  438. return retval;
  439. }
  440. if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
  441. {
  442. return retval;
  443. }
  444. if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
  445. {
  446. return retval;
  447. }
  448. if (verify != MIPS32_SDBBP)
  449. {
  450. LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  451. return ERROR_OK;
  452. }
  453. }
  454. else
  455. {
  456. uint16_t verify = 0xffff;
  457. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
  458. {
  459. return retval;
  460. }
  461. if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
  462. {
  463. return retval;
  464. }
  465. if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
  466. {
  467. return retval;
  468. }
  469. if (verify != MIPS16_SDBBP)
  470. {
  471. LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  472. return ERROR_OK;
  473. }
  474. }
  475. breakpoint->set = 20; /* Any nice value but 0 */
  476. }
  477. return ERROR_OK;
  478. }
  479. int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
  480. {
  481. /* get pointers to arch-specific information */
  482. struct mips32_common *mips32 = target->arch_info;
  483. struct mips32_comparator * comparator_list = mips32->inst_break_list;
  484. int retval;
  485. if (!breakpoint->set)
  486. {
  487. LOG_WARNING("breakpoint not set");
  488. return ERROR_OK;
  489. }
  490. if (breakpoint->type == BKPT_HARD)
  491. {
  492. int bp_num = breakpoint->set - 1;
  493. if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
  494. {
  495. LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
  496. breakpoint->unique_id);
  497. return ERROR_OK;
  498. }
  499. LOG_DEBUG("bpid: %d - releasing hw: %d",
  500. breakpoint->unique_id,
  501. bp_num );
  502. comparator_list[bp_num].used = 0;
  503. comparator_list[bp_num].bp_value = 0;
  504. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
  505. }
  506. else
  507. {
  508. /* restore original instruction (kept in target endianness) */
  509. LOG_DEBUG("bpid: %d", breakpoint->unique_id);
  510. if (breakpoint->length == 4)
  511. {
  512. uint32_t current_instr;
  513. /* check that user program has not modified breakpoint instruction */
  514. if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
  515. {
  516. return retval;
  517. }
  518. if (current_instr == MIPS32_SDBBP)
  519. {
  520. if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  521. {
  522. return retval;
  523. }
  524. }
  525. }
  526. else
  527. {
  528. uint16_t current_instr;
  529. /* check that user program has not modified breakpoint instruction */
  530. if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
  531. {
  532. return retval;
  533. }
  534. if (current_instr == MIPS16_SDBBP)
  535. {
  536. if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  537. {
  538. return retval;
  539. }
  540. }
  541. }
  542. }
  543. breakpoint->set = 0;
  544. return ERROR_OK;
  545. }
  546. int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  547. {
  548. struct mips32_common *mips32 = target->arch_info;
  549. if (breakpoint->type == BKPT_HARD)
  550. {
  551. if (mips32->num_inst_bpoints_avail < 1)
  552. {
  553. LOG_INFO("no hardware breakpoint available");
  554. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  555. }
  556. mips32->num_inst_bpoints_avail--;
  557. }
  558. mips_m4k_set_breakpoint(target, breakpoint);
  559. return ERROR_OK;
  560. }
  561. int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
  562. {
  563. /* get pointers to arch-specific information */
  564. struct mips32_common *mips32 = target->arch_info;
  565. if (target->state != TARGET_HALTED)
  566. {
  567. LOG_WARNING("target not halted");
  568. return ERROR_TARGET_NOT_HALTED;
  569. }
  570. if (breakpoint->set)
  571. {
  572. mips_m4k_unset_breakpoint(target, breakpoint);
  573. }
  574. if (breakpoint->type == BKPT_HARD)
  575. mips32->num_inst_bpoints_avail++;
  576. return ERROR_OK;
  577. }
  578. int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
  579. {
  580. struct mips32_common *mips32 = target->arch_info;
  581. struct mips32_comparator * comparator_list = mips32->data_break_list;
  582. int wp_num = 0;
  583. /*
  584. * watchpoint enabled, ignore all byte lanes in value register
  585. * and exclude both load and store accesses from watchpoint
  586. * condition evaluation
  587. */
  588. int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
  589. (0xff << EJTAG_DBCn_BLM_SHIFT);
  590. if (watchpoint->set)
  591. {
  592. LOG_WARNING("watchpoint already set");
  593. return ERROR_OK;
  594. }
  595. while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
  596. wp_num++;
  597. if (wp_num >= mips32->num_data_bpoints)
  598. {
  599. LOG_ERROR("Can not find free FP Comparator");
  600. return ERROR_FAIL;
  601. }
  602. if (watchpoint->length != 4)
  603. {
  604. LOG_ERROR("Only watchpoints of length 4 are supported");
  605. return ERROR_TARGET_UNALIGNED_ACCESS;
  606. }
  607. if (watchpoint->address % 4)
  608. {
  609. LOG_ERROR("Watchpoints address should be word aligned");
  610. return ERROR_TARGET_UNALIGNED_ACCESS;
  611. }
  612. switch (watchpoint->rw)
  613. {
  614. case WPT_READ:
  615. enable &= ~EJTAG_DBCn_NOLB;
  616. break;
  617. case WPT_WRITE:
  618. enable &= ~EJTAG_DBCn_NOSB;
  619. break;
  620. case WPT_ACCESS:
  621. enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
  622. break;
  623. default:
  624. LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
  625. }
  626. watchpoint->set = wp_num + 1;
  627. comparator_list[wp_num].used = 1;
  628. comparator_list[wp_num].bp_value = watchpoint->address;
  629. target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
  630. target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
  631. target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
  632. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
  633. target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
  634. LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
  635. return ERROR_OK;
  636. }
  637. int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
  638. {
  639. /* get pointers to arch-specific information */
  640. struct mips32_common *mips32 = target->arch_info;
  641. struct mips32_comparator * comparator_list = mips32->data_break_list;
  642. if (!watchpoint->set)
  643. {
  644. LOG_WARNING("watchpoint not set");
  645. return ERROR_OK;
  646. }
  647. int wp_num = watchpoint->set - 1;
  648. if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
  649. {
  650. LOG_DEBUG("Invalid FP Comparator number in watchpoint");
  651. return ERROR_OK;
  652. }
  653. comparator_list[wp_num].used = 0;
  654. comparator_list[wp_num].bp_value = 0;
  655. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
  656. watchpoint->set = 0;
  657. return ERROR_OK;
  658. }
  659. int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  660. {
  661. struct mips32_common *mips32 = target->arch_info;
  662. if (mips32->num_data_bpoints_avail < 1)
  663. {
  664. LOG_INFO("no hardware watchpoints available");
  665. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  666. }
  667. mips32->num_data_bpoints_avail--;
  668. mips_m4k_set_watchpoint(target, watchpoint);
  669. return ERROR_OK;
  670. }
  671. int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
  672. {
  673. /* get pointers to arch-specific information */
  674. struct mips32_common *mips32 = target->arch_info;
  675. if (target->state != TARGET_HALTED)
  676. {
  677. LOG_WARNING("target not halted");
  678. return ERROR_TARGET_NOT_HALTED;
  679. }
  680. if (watchpoint->set)
  681. {
  682. mips_m4k_unset_watchpoint(target, watchpoint);
  683. }
  684. mips32->num_data_bpoints_avail++;
  685. return ERROR_OK;
  686. }
  687. void mips_m4k_enable_watchpoints(struct target *target)
  688. {
  689. struct watchpoint *watchpoint = target->watchpoints;
  690. /* set any pending watchpoints */
  691. while (watchpoint)
  692. {
  693. if (watchpoint->set == 0)
  694. mips_m4k_set_watchpoint(target, watchpoint);
  695. watchpoint = watchpoint->next;
  696. }
  697. }
  698. int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  699. {
  700. struct mips32_common *mips32 = target->arch_info;
  701. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  702. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
  703. if (target->state != TARGET_HALTED)
  704. {
  705. LOG_WARNING("target not halted");
  706. return ERROR_TARGET_NOT_HALTED;
  707. }
  708. /* sanitize arguments */
  709. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  710. return ERROR_INVALID_ARGUMENTS;
  711. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  712. return ERROR_TARGET_UNALIGNED_ACCESS;
  713. /* if noDMA off, use DMAACC mode for memory read */
  714. int retval;
  715. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  716. retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  717. else
  718. retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  719. if (ERROR_OK != retval)
  720. return retval;
  721. return ERROR_OK;
  722. }
  723. int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  724. {
  725. struct mips32_common *mips32 = target->arch_info;
  726. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  727. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
  728. if (target->state != TARGET_HALTED)
  729. {
  730. LOG_WARNING("target not halted");
  731. return ERROR_TARGET_NOT_HALTED;
  732. }
  733. /* sanitize arguments */
  734. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  735. return ERROR_INVALID_ARGUMENTS;
  736. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  737. return ERROR_TARGET_UNALIGNED_ACCESS;
  738. /* if noDMA off, use DMAACC mode for memory write */
  739. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  740. return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  741. else
  742. return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  743. }
  744. int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
  745. {
  746. mips32_build_reg_cache(target);
  747. return ERROR_OK;
  748. }
  749. int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
  750. {
  751. struct mips32_common *mips32 = &mips_m4k->mips32_common;
  752. mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
  753. /* initialize mips4k specific info */
  754. mips32_init_arch_info(target, mips32, tap);
  755. mips32->arch_info = mips_m4k;
  756. return ERROR_OK;
  757. }
  758. int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
  759. {
  760. struct mips_m4k_common *mips_m4k = calloc(1,sizeof(struct mips_m4k_common));
  761. mips_m4k_init_arch_info(target, mips_m4k, target->tap);
  762. return ERROR_OK;
  763. }
  764. int mips_m4k_examine(struct target *target)
  765. {
  766. int retval;
  767. struct mips32_common *mips32 = target->arch_info;
  768. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  769. uint32_t idcode = 0;
  770. if (!target_was_examined(target))
  771. {
  772. mips_ejtag_get_idcode(ejtag_info, &idcode);
  773. ejtag_info->idcode = idcode;
  774. if (((idcode >> 1) & 0x7FF) == 0x29)
  775. {
  776. /* we are using a pic32mx so select ejtag port
  777. * as it is not selected by default */
  778. mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
  779. LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
  780. }
  781. }
  782. /* init rest of ejtag interface */
  783. if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
  784. return retval;
  785. if ((retval = mips32_examine(target)) != ERROR_OK)
  786. return retval;
  787. return ERROR_OK;
  788. }
  789. int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
  790. {
  791. struct mips32_common *mips32 = target->arch_info;
  792. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  793. struct working_area *source;
  794. int retval;
  795. int write = 1;
  796. LOG_DEBUG("address: 0x%8.8x, count: 0x%8.8x", address, count);
  797. if (target->state != TARGET_HALTED)
  798. {
  799. LOG_WARNING("target not halted");
  800. return ERROR_TARGET_NOT_HALTED;
  801. }
  802. /* check alignment */
  803. if (address & 0x3u)
  804. return ERROR_TARGET_UNALIGNED_ACCESS;
  805. /* Get memory for block write handler */
  806. retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source);
  807. if (retval != ERROR_OK)
  808. {
  809. LOG_WARNING("No working area available, falling back to non-bulk write");
  810. return mips_m4k_write_memory(target, address, 4, count, buffer);
  811. }
  812. /* TAP data register is loaded LSB first (little endian) */
  813. if (target->endianness == TARGET_BIG_ENDIAN)
  814. {
  815. uint32_t i, t32;
  816. for(i = 0; i < (count*4); i+=4)
  817. {
  818. t32 = be_to_h_u32((uint8_t *) &buffer[i]);
  819. h_u32_to_le(&buffer[i], t32);
  820. }
  821. }
  822. retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address, count, (uint32_t *) buffer);
  823. if (source)
  824. target_free_working_area(target, source);
  825. return retval;
  826. }
  827. int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)
  828. {
  829. return ERROR_FAIL; /* use bulk read method */
  830. }