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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2007,2008 √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * Copyright (C) 2008 by Hongtao Zheng *
  12. * hontor@126.com *
  13. * *
  14. * This program is free software; you can redistribute it and/or modify *
  15. * it under the terms of the GNU General Public License as published by *
  16. * the Free Software Foundation; either version 2 of the License, or *
  17. * (at your option) any later version. *
  18. * *
  19. * This program is distributed in the hope that it will be useful, *
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  22. * GNU General Public License for more details. *
  23. * *
  24. * You should have received a copy of the GNU General Public License *
  25. * along with this program; if not, write to the *
  26. * Free Software Foundation, Inc., *
  27. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  28. ***************************************************************************/
  29. #ifdef HAVE_CONFIG_H
  30. #include "config.h"
  31. #endif
  32. #include "replacements.h"
  33. #include "embeddedice.h"
  34. #include "target.h"
  35. #include "target_request.h"
  36. #include "armv4_5.h"
  37. #include "arm_jtag.h"
  38. #include "jtag.h"
  39. #include "log.h"
  40. #include "arm7_9_common.h"
  41. #include "breakpoints.h"
  42. #include "time_support.h"
  43. #include "arm_simulator.h"
  44. #include <stdlib.h>
  45. #include <string.h>
  46. #include <unistd.h>
  47. #include <sys/types.h>
  48. #include <sys/stat.h>
  49. #include <sys/time.h>
  50. #include <errno.h>
  51. int arm7_9_debug_entry(target_t *target);
  52. int arm7_9_enable_sw_bkpts(struct target_s *target);
  53. /* command handler forward declarations */
  54. int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55. int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56. int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57. int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  58. int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  59. int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  60. int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  61. int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  62. static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
  63. {
  64. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  65. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  66. arm7_9->sw_breakpoints_added = 0;
  67. arm7_9->wp0_used = 0;
  68. arm7_9->wp1_used = arm7_9->wp1_used_default;
  69. arm7_9->wp_available = arm7_9->wp_available_max;
  70. return jtag_execute_queue();
  71. }
  72. /* set up embedded ice registers */
  73. static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
  74. {
  75. if (arm7_9->sw_breakpoints_added)
  76. {
  77. return ERROR_OK;
  78. }
  79. if (arm7_9->wp_available < 1)
  80. {
  81. LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
  82. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  83. }
  84. arm7_9->wp_available--;
  85. /* pick a breakpoint unit */
  86. if (!arm7_9->wp0_used)
  87. {
  88. arm7_9->sw_breakpoints_added=1;
  89. arm7_9->wp0_used = 3;
  90. } else if (!arm7_9->wp1_used)
  91. {
  92. arm7_9->sw_breakpoints_added=2;
  93. arm7_9->wp1_used = 3;
  94. }
  95. else
  96. {
  97. LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
  98. return ERROR_FAIL;
  99. }
  100. if (arm7_9->sw_breakpoints_added==1)
  101. {
  102. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
  103. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
  104. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
  105. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  106. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  107. }
  108. else if (arm7_9->sw_breakpoints_added==2)
  109. {
  110. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
  111. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
  112. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
  113. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  114. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  115. }
  116. else
  117. {
  118. LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
  119. return ERROR_FAIL;
  120. }
  121. return jtag_execute_queue();
  122. }
  123. /* set things up after a reset / on startup */
  124. int arm7_9_setup(target_t *target)
  125. {
  126. armv4_5_common_t *armv4_5 = target->arch_info;
  127. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  128. return arm7_9_clear_watchpoints(arm7_9);
  129. }
  130. int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
  131. {
  132. armv4_5_common_t *armv4_5 = target->arch_info;
  133. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  134. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  135. {
  136. return -1;
  137. }
  138. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
  139. {
  140. return -1;
  141. }
  142. *armv4_5_p = armv4_5;
  143. *arm7_9_p = arm7_9;
  144. return ERROR_OK;
  145. }
  146. /* we set up the breakpoint even if it is already set. Some action, e.g. reset
  147. * might have erased the values in embedded ice
  148. */
  149. int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  150. {
  151. armv4_5_common_t *armv4_5 = target->arch_info;
  152. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  153. int retval=ERROR_OK;
  154. if (target->state != TARGET_HALTED)
  155. {
  156. LOG_WARNING("target not halted");
  157. return ERROR_TARGET_NOT_HALTED;
  158. }
  159. if (breakpoint->type == BKPT_HARD)
  160. {
  161. /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
  162. u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
  163. if (breakpoint->set==1)
  164. {
  165. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
  166. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
  167. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
  168. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  169. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  170. }
  171. else if (breakpoint->set==2)
  172. {
  173. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
  174. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
  175. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
  176. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  177. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  178. }
  179. else
  180. {
  181. LOG_ERROR("BUG: no hardware comparator available");
  182. return ERROR_OK;
  183. }
  184. retval=jtag_execute_queue();
  185. }
  186. else if (breakpoint->type == BKPT_SOFT)
  187. {
  188. if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
  189. return retval;
  190. /* did we already set this breakpoint? */
  191. if (breakpoint->set)
  192. return ERROR_OK;
  193. if (breakpoint->length == 4)
  194. {
  195. u32 verify = 0xffffffff;
  196. /* keep the original instruction in target endianness */
  197. if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  198. {
  199. return retval;
  200. }
  201. /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
  202. if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
  203. {
  204. return retval;
  205. }
  206. if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
  207. {
  208. return retval;
  209. }
  210. if (verify != arm7_9->arm_bkpt)
  211. {
  212. LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
  213. return ERROR_OK;
  214. }
  215. }
  216. else
  217. {
  218. u16 verify = 0xffff;
  219. /* keep the original instruction in target endianness */
  220. if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  221. {
  222. return retval;
  223. }
  224. /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
  225. if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
  226. {
  227. return retval;
  228. }
  229. if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
  230. {
  231. return retval;
  232. }
  233. if (verify != arm7_9->thumb_bkpt)
  234. {
  235. LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
  236. return ERROR_OK;
  237. }
  238. }
  239. breakpoint->set = 1;
  240. }
  241. return retval;
  242. }
  243. int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  244. {
  245. int retval = ERROR_OK;
  246. armv4_5_common_t *armv4_5 = target->arch_info;
  247. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  248. if (!breakpoint->set)
  249. {
  250. LOG_WARNING("breakpoint not set");
  251. return ERROR_OK;
  252. }
  253. if (breakpoint->type == BKPT_HARD)
  254. {
  255. if (breakpoint->set == 1)
  256. {
  257. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  258. arm7_9->wp0_used = 0;
  259. }
  260. else if (breakpoint->set == 2)
  261. {
  262. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  263. arm7_9->wp1_used = 0;
  264. }
  265. retval = jtag_execute_queue();
  266. breakpoint->set = 0;
  267. }
  268. else
  269. {
  270. /* restore original instruction (kept in target endianness) */
  271. if (breakpoint->length == 4)
  272. {
  273. u32 current_instr;
  274. /* check that user program as not modified breakpoint instruction */
  275. if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
  276. {
  277. return retval;
  278. }
  279. if (current_instr==arm7_9->arm_bkpt)
  280. if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  281. {
  282. return retval;
  283. }
  284. }
  285. else
  286. {
  287. u16 current_instr;
  288. /* check that user program as not modified breakpoint instruction */
  289. if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
  290. {
  291. return retval;
  292. }
  293. if (current_instr==arm7_9->thumb_bkpt)
  294. if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  295. {
  296. return retval;
  297. }
  298. }
  299. breakpoint->set = 0;
  300. }
  301. return retval;
  302. }
  303. int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  304. {
  305. armv4_5_common_t *armv4_5 = target->arch_info;
  306. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  307. if (target->state != TARGET_HALTED)
  308. {
  309. LOG_WARNING("target not halted");
  310. return ERROR_TARGET_NOT_HALTED;
  311. }
  312. if (arm7_9->breakpoint_count==0)
  313. {
  314. /* make sure we don't have any dangling breakpoints. This is vital upon
  315. * GDB connect/disconnect
  316. */
  317. arm7_9_clear_watchpoints(arm7_9);
  318. }
  319. if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
  320. {
  321. LOG_INFO("no watchpoint unit available for hardware breakpoint");
  322. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  323. }
  324. if ((breakpoint->length != 2) && (breakpoint->length != 4))
  325. {
  326. LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
  327. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  328. }
  329. if (breakpoint->type == BKPT_HARD)
  330. {
  331. arm7_9->wp_available--;
  332. if (!arm7_9->wp0_used)
  333. {
  334. arm7_9->wp0_used = 1;
  335. breakpoint->set = 1;
  336. }
  337. else if (!arm7_9->wp1_used)
  338. {
  339. arm7_9->wp1_used = 1;
  340. breakpoint->set = 2;
  341. }
  342. else
  343. {
  344. LOG_ERROR("BUG: no hardware comparator available");
  345. }
  346. }
  347. arm7_9->breakpoint_count++;
  348. return arm7_9_set_breakpoint(target, breakpoint);
  349. }
  350. int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  351. {
  352. int retval = ERROR_OK;
  353. armv4_5_common_t *armv4_5 = target->arch_info;
  354. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  355. if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
  356. {
  357. return retval;
  358. }
  359. if (breakpoint->type == BKPT_HARD)
  360. arm7_9->wp_available++;
  361. arm7_9->breakpoint_count--;
  362. if (arm7_9->breakpoint_count==0)
  363. {
  364. /* make sure we don't have any dangling breakpoints */
  365. if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
  366. {
  367. return retval;
  368. }
  369. }
  370. return ERROR_OK;
  371. }
  372. int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  373. {
  374. int retval = ERROR_OK;
  375. armv4_5_common_t *armv4_5 = target->arch_info;
  376. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  377. int rw_mask = 1;
  378. u32 mask;
  379. mask = watchpoint->length - 1;
  380. if (target->state != TARGET_HALTED)
  381. {
  382. LOG_WARNING("target not halted");
  383. return ERROR_TARGET_NOT_HALTED;
  384. }
  385. if (watchpoint->rw == WPT_ACCESS)
  386. rw_mask = 0;
  387. else
  388. rw_mask = 1;
  389. if (!arm7_9->wp0_used)
  390. {
  391. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
  392. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
  393. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
  394. if( watchpoint->mask != 0xffffffffu )
  395. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
  396. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
  397. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
  398. if((retval = jtag_execute_queue()) != ERROR_OK)
  399. {
  400. return retval;
  401. }
  402. watchpoint->set = 1;
  403. arm7_9->wp0_used = 2;
  404. }
  405. else if (!arm7_9->wp1_used)
  406. {
  407. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
  408. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
  409. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
  410. if( watchpoint->mask != 0xffffffffu )
  411. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
  412. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
  413. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
  414. if((retval = jtag_execute_queue()) != ERROR_OK)
  415. {
  416. return retval;
  417. }
  418. watchpoint->set = 2;
  419. arm7_9->wp1_used = 2;
  420. }
  421. else
  422. {
  423. LOG_ERROR("BUG: no hardware comparator available");
  424. return ERROR_OK;
  425. }
  426. return ERROR_OK;
  427. }
  428. int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  429. {
  430. int retval = ERROR_OK;
  431. armv4_5_common_t *armv4_5 = target->arch_info;
  432. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  433. if (target->state != TARGET_HALTED)
  434. {
  435. LOG_WARNING("target not halted");
  436. return ERROR_TARGET_NOT_HALTED;
  437. }
  438. if (!watchpoint->set)
  439. {
  440. LOG_WARNING("breakpoint not set");
  441. return ERROR_OK;
  442. }
  443. if (watchpoint->set == 1)
  444. {
  445. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  446. if((retval = jtag_execute_queue()) != ERROR_OK)
  447. {
  448. return retval;
  449. }
  450. arm7_9->wp0_used = 0;
  451. }
  452. else if (watchpoint->set == 2)
  453. {
  454. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  455. if((retval = jtag_execute_queue()) != ERROR_OK)
  456. {
  457. return retval;
  458. }
  459. arm7_9->wp1_used = 0;
  460. }
  461. watchpoint->set = 0;
  462. return ERROR_OK;
  463. }
  464. int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  465. {
  466. armv4_5_common_t *armv4_5 = target->arch_info;
  467. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  468. if (target->state != TARGET_HALTED)
  469. {
  470. LOG_WARNING("target not halted");
  471. return ERROR_TARGET_NOT_HALTED;
  472. }
  473. if (arm7_9->wp_available < 1)
  474. {
  475. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  476. }
  477. if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
  478. {
  479. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  480. }
  481. arm7_9->wp_available--;
  482. return ERROR_OK;
  483. }
  484. int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  485. {
  486. int retval = ERROR_OK;
  487. armv4_5_common_t *armv4_5 = target->arch_info;
  488. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  489. if (watchpoint->set)
  490. {
  491. if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
  492. {
  493. return retval;
  494. }
  495. }
  496. arm7_9->wp_available++;
  497. return ERROR_OK;
  498. }
  499. int arm7_9_execute_sys_speed(struct target_s *target)
  500. {
  501. int retval;
  502. armv4_5_common_t *armv4_5 = target->arch_info;
  503. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  504. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  505. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  506. /* set RESTART instruction */
  507. jtag_add_end_state(TAP_RTI);
  508. if (arm7_9->need_bypass_before_restart) {
  509. arm7_9->need_bypass_before_restart = 0;
  510. arm_jtag_set_instr(jtag_info, 0xf, NULL);
  511. }
  512. arm_jtag_set_instr(jtag_info, 0x4, NULL);
  513. long long then=timeval_ms();
  514. int timeout;
  515. while (!(timeout=((timeval_ms()-then)>1000)))
  516. {
  517. /* read debug status register */
  518. embeddedice_read_reg(dbg_stat);
  519. if ((retval = jtag_execute_queue()) != ERROR_OK)
  520. return retval;
  521. if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
  522. && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
  523. break;
  524. if (debug_level>=3)
  525. {
  526. alive_sleep(100);
  527. } else
  528. {
  529. keep_alive();
  530. }
  531. }
  532. if (timeout)
  533. {
  534. LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
  535. return ERROR_TARGET_TIMEOUT;
  536. }
  537. return ERROR_OK;
  538. }
  539. int arm7_9_execute_fast_sys_speed(struct target_s *target)
  540. {
  541. static int set=0;
  542. static u8 check_value[4], check_mask[4];
  543. armv4_5_common_t *armv4_5 = target->arch_info;
  544. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  545. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  546. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  547. /* set RESTART instruction */
  548. jtag_add_end_state(TAP_RTI);
  549. if (arm7_9->need_bypass_before_restart) {
  550. arm7_9->need_bypass_before_restart = 0;
  551. arm_jtag_set_instr(jtag_info, 0xf, NULL);
  552. }
  553. arm_jtag_set_instr(jtag_info, 0x4, NULL);
  554. if (!set)
  555. {
  556. /* check for DBGACK and SYSCOMP set (others don't care) */
  557. /* NB! These are constants that must be available until after next jtag_execute() and
  558. we evaluate the values upon first execution in lieu of setting up these constants
  559. during early setup.
  560. */
  561. buf_set_u32(check_value, 0, 32, 0x9);
  562. buf_set_u32(check_mask, 0, 32, 0x9);
  563. set=1;
  564. }
  565. /* read debug status register */
  566. embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
  567. return ERROR_OK;
  568. }
  569. int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
  570. {
  571. armv4_5_common_t *armv4_5 = target->arch_info;
  572. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  573. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  574. u32 *data;
  575. int i, retval = ERROR_OK;
  576. data = malloc(size * (sizeof(u32)));
  577. retval = embeddedice_receive(jtag_info, data, size);
  578. for (i = 0; i < size; i++)
  579. {
  580. h_u32_to_le(buffer + (i * 4), data[i]);
  581. }
  582. free(data);
  583. return retval;
  584. }
  585. int arm7_9_handle_target_request(void *priv)
  586. {
  587. int retval = ERROR_OK;
  588. target_t *target = priv;
  589. if (!target->type->examined)
  590. return ERROR_OK;
  591. armv4_5_common_t *armv4_5 = target->arch_info;
  592. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  593. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  594. reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
  595. if (!target->dbg_msg_enabled)
  596. return ERROR_OK;
  597. if (target->state == TARGET_RUNNING)
  598. {
  599. /* read DCC control register */
  600. embeddedice_read_reg(dcc_control);
  601. if ((retval = jtag_execute_queue()) != ERROR_OK)
  602. {
  603. return retval;
  604. }
  605. /* check W bit */
  606. if (buf_get_u32(dcc_control->value, 1, 1) == 1)
  607. {
  608. u32 request;
  609. if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
  610. {
  611. return retval;
  612. }
  613. if ((retval = target_request(target, request)) != ERROR_OK)
  614. {
  615. return retval;
  616. }
  617. }
  618. }
  619. return ERROR_OK;
  620. }
  621. int arm7_9_poll(target_t *target)
  622. {
  623. int retval;
  624. armv4_5_common_t *armv4_5 = target->arch_info;
  625. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  626. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  627. /* read debug status register */
  628. embeddedice_read_reg(dbg_stat);
  629. if ((retval = jtag_execute_queue()) != ERROR_OK)
  630. {
  631. return retval;
  632. }
  633. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
  634. {
  635. /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
  636. if (target->state == TARGET_UNKNOWN)
  637. {
  638. target->state = TARGET_RUNNING;
  639. LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
  640. }
  641. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
  642. {
  643. int check_pc=0;
  644. if (target->state == TARGET_RESET)
  645. {
  646. if (target->reset_halt)
  647. {
  648. if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
  649. {
  650. check_pc = 1;
  651. }
  652. }
  653. }
  654. target->state = TARGET_HALTED;
  655. if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
  656. return retval;
  657. if (check_pc)
  658. {
  659. reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
  660. u32 t=*((u32 *)reg->value);
  661. if (t!=0)
  662. {
  663. LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
  664. }
  665. }
  666. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
  667. {
  668. return retval;
  669. }
  670. }
  671. if (target->state == TARGET_DEBUG_RUNNING)
  672. {
  673. target->state = TARGET_HALTED;
  674. if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
  675. return retval;
  676. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
  677. {
  678. return retval;
  679. }
  680. }
  681. if (target->state != TARGET_HALTED)
  682. {
  683. LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
  684. }
  685. }
  686. else
  687. {
  688. if (target->state != TARGET_DEBUG_RUNNING)
  689. target->state = TARGET_RUNNING;
  690. }
  691. return ERROR_OK;
  692. }
  693. /*
  694. Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
  695. in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
  696. while the core is held in reset(SRST). It isn't possible to program the halt
  697. condition once reset was asserted, hence a hook that allows the target to set
  698. up its reset-halt condition prior to asserting reset.
  699. */
  700. int arm7_9_assert_reset(target_t *target)
  701. {
  702. armv4_5_common_t *armv4_5 = target->arch_info;
  703. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  704. LOG_DEBUG("target->state: %s",
  705. Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
  706. if (!(jtag_reset_config & RESET_HAS_SRST))
  707. {
  708. LOG_ERROR("Can't assert SRST");
  709. return ERROR_FAIL;
  710. }
  711. if (target->reset_halt)
  712. {
  713. /*
  714. * Some targets do not support communication while SRST is asserted. We need to
  715. * set up the reset vector catch here.
  716. *
  717. * If TRST is asserted, then these settings will be reset anyway, so setting them
  718. * here is harmless.
  719. */
  720. if (arm7_9->has_vector_catch)
  721. {
  722. /* program vector catch register to catch reset vector */
  723. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
  724. }
  725. else
  726. {
  727. /* program watchpoint unit to match on reset vector address */
  728. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
  729. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
  730. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  731. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  732. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  733. }
  734. }
  735. /* here we should issue a srst only, but we may have to assert trst as well */
  736. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  737. {
  738. jtag_add_reset(1, 1);
  739. } else
  740. {
  741. jtag_add_reset(0, 1);
  742. }
  743. target->state = TARGET_RESET;
  744. jtag_add_sleep(50000);
  745. armv4_5_invalidate_core_regs(target);
  746. if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
  747. {
  748. /* debug entry was already prepared in arm7_9_assert_reset() */
  749. target->debug_reason = DBG_REASON_DBGRQ;
  750. }
  751. return ERROR_OK;
  752. }
  753. int arm7_9_deassert_reset(target_t *target)
  754. {
  755. int retval=ERROR_OK;
  756. LOG_DEBUG("target->state: %s",
  757. Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
  758. /* deassert reset lines */
  759. jtag_add_reset(0, 0);
  760. if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
  761. {
  762. LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
  763. /* set up embedded ice registers again */
  764. if ((retval=target->type->examine(target))!=ERROR_OK)
  765. return retval;
  766. if ((retval=target_poll(target))!=ERROR_OK)
  767. {
  768. return retval;
  769. }
  770. if ((retval=target_halt(target))!=ERROR_OK)
  771. {
  772. return retval;
  773. }
  774. }
  775. return retval;
  776. }
  777. int arm7_9_clear_halt(target_t *target)
  778. {
  779. armv4_5_common_t *armv4_5 = target->arch_info;
  780. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  781. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  782. /* we used DBGRQ only if we didn't come out of reset */
  783. if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
  784. {
  785. /* program EmbeddedICE Debug Control Register to deassert DBGRQ
  786. */
  787. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
  788. embeddedice_store_reg(dbg_ctrl);
  789. }
  790. else
  791. {
  792. if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
  793. {
  794. /* if we came out of reset, and vector catch is supported, we used
  795. * vector catch to enter debug state
  796. * restore the register in that case
  797. */
  798. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
  799. }
  800. else
  801. {
  802. /* restore registers if watchpoint unit 0 was in use
  803. */
  804. if (arm7_9->wp0_used)
  805. {
  806. if (arm7_9->debug_entry_from_reset)
  807. {
  808. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
  809. }
  810. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
  811. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
  812. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
  813. }
  814. /* control value always has to be restored, as it was either disabled,
  815. * or enabled with possibly different bits
  816. */
  817. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
  818. }
  819. }
  820. return ERROR_OK;
  821. }
  822. int arm7_9_soft_reset_halt(struct target_s *target)
  823. {
  824. armv4_5_common_t *armv4_5 = target->arch_info;
  825. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  826. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  827. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  828. int i;
  829. int retval;
  830. if ((retval=target_halt(target))!=ERROR_OK)
  831. return retval;
  832. long long then=timeval_ms();
  833. int timeout;
  834. while (!(timeout=((timeval_ms()-then)>1000)))
  835. {
  836. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
  837. break;
  838. embeddedice_read_reg(dbg_stat);
  839. if ((retval=jtag_execute_queue())!=ERROR_OK)
  840. return retval;
  841. if (debug_level>=3)
  842. {
  843. alive_sleep(100);
  844. } else
  845. {
  846. keep_alive();
  847. }
  848. }
  849. if (timeout)
  850. {
  851. LOG_ERROR("Failed to halt CPU after 1 sec");
  852. return ERROR_TARGET_TIMEOUT;
  853. }
  854. target->state = TARGET_HALTED;
  855. /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
  856. * ensure that DBGRQ is cleared
  857. */
  858. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
  859. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
  860. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
  861. embeddedice_store_reg(dbg_ctrl);
  862. if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
  863. {
  864. return retval;
  865. }
  866. /* if the target is in Thumb state, change to ARM state */
  867. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
  868. {
  869. u32 r0_thumb, pc_thumb;
  870. LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
  871. /* Entered debug from Thumb mode */
  872. armv4_5->core_state = ARMV4_5_STATE_THUMB;
  873. arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
  874. }
  875. /* all register content is now invalid */
  876. if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
  877. {
  878. return retval;
  879. }
  880. /* SVC, ARM state, IRQ and FIQ disabled */
  881. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
  882. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  883. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  884. /* start fetching from 0x0 */
  885. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  886. armv4_5->core_cache->reg_list[15].dirty = 1;
  887. armv4_5->core_cache->reg_list[15].valid = 1;
  888. armv4_5->core_mode = ARMV4_5_MODE_SVC;
  889. armv4_5->core_state = ARMV4_5_STATE_ARM;
  890. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  891. return ERROR_FAIL;
  892. /* reset registers */
  893. for (i = 0; i <= 14; i++)
  894. {
  895. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
  896. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
  897. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
  898. }
  899. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
  900. {
  901. return retval;
  902. }
  903. return ERROR_OK;
  904. }
  905. int arm7_9_halt(target_t *target)
  906. {
  907. if (target->state==TARGET_RESET)
  908. {
  909. LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
  910. return ERROR_OK;
  911. }
  912. armv4_5_common_t *armv4_5 = target->arch_info;
  913. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  914. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  915. LOG_DEBUG("target->state: %s",
  916. Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
  917. if (target->state == TARGET_HALTED)
  918. {
  919. LOG_DEBUG("target was already halted");
  920. return ERROR_OK;
  921. }
  922. if (target->state == TARGET_UNKNOWN)
  923. {
  924. LOG_WARNING("target was in unknown state when halt was requested");
  925. }
  926. if (arm7_9->use_dbgrq)
  927. {
  928. /* program EmbeddedICE Debug Control Register to assert DBGRQ
  929. */
  930. if (arm7_9->set_special_dbgrq) {
  931. arm7_9->set_special_dbgrq(target);
  932. } else {
  933. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
  934. embeddedice_store_reg(dbg_ctrl);
  935. }
  936. }
  937. else
  938. {
  939. /* program watchpoint unit to match on any address
  940. */
  941. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
  942. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  943. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  944. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  945. }
  946. target->debug_reason = DBG_REASON_DBGRQ;
  947. return ERROR_OK;
  948. }
  949. int arm7_9_debug_entry(target_t *target)
  950. {
  951. int i;
  952. u32 context[16];
  953. u32* context_p[16];
  954. u32 r0_thumb, pc_thumb;
  955. u32 cpsr;
  956. int retval;
  957. /* get pointers to arch-specific information */
  958. armv4_5_common_t *armv4_5 = target->arch_info;
  959. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  960. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  961. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  962. #ifdef _DEBUG_ARM7_9_
  963. LOG_DEBUG("-");
  964. #endif
  965. if (arm7_9->pre_debug_entry)
  966. arm7_9->pre_debug_entry(target);
  967. /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
  968. * ensure that DBGRQ is cleared
  969. */
  970. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
  971. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
  972. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
  973. embeddedice_store_reg(dbg_ctrl);
  974. if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
  975. {
  976. return retval;
  977. }
  978. if ((retval = jtag_execute_queue()) != ERROR_OK)
  979. {
  980. return retval;
  981. }
  982. if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
  983. return retval;
  984. if (target->state != TARGET_HALTED)
  985. {
  986. LOG_WARNING("target not halted");
  987. return ERROR_TARGET_NOT_HALTED;
  988. }
  989. /* if the target is in Thumb state, change to ARM state */
  990. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
  991. {
  992. LOG_DEBUG("target entered debug from Thumb state");
  993. /* Entered debug from Thumb mode */
  994. armv4_5->core_state = ARMV4_5_STATE_THUMB;
  995. arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
  996. LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
  997. }
  998. else
  999. {
  1000. LOG_DEBUG("target entered debug from ARM state");
  1001. /* Entered debug from ARM mode */
  1002. armv4_5->core_state = ARMV4_5_STATE_ARM;
  1003. }
  1004. for (i = 0; i < 16; i++)
  1005. context_p[i] = &context[i];
  1006. /* save core registers (r0 - r15 of current core mode) */
  1007. arm7_9->read_core_regs(target, 0xffff, context_p);
  1008. arm7_9->read_xpsr(target, &cpsr, 0);
  1009. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1010. return retval;
  1011. /* if the core has been executing in Thumb state, set the T bit */
  1012. if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1013. cpsr |= 0x20;
  1014. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
  1015. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
  1016. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  1017. armv4_5->core_mode = cpsr & 0x1f;
  1018. if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
  1019. {
  1020. target->state = TARGET_UNKNOWN;
  1021. LOG_ERROR("cpsr contains invalid mode value - communication failure");
  1022. return ERROR_TARGET_FAILURE;
  1023. }
  1024. LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
  1025. if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1026. {
  1027. LOG_DEBUG("thumb state, applying fixups");
  1028. context[0] = r0_thumb;
  1029. context[15] = pc_thumb;
  1030. } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1031. {
  1032. /* adjust value stored by STM */
  1033. context[15] -= 3 * 4;
  1034. }
  1035. if ((target->debug_reason == DBG_REASON_BREAKPOINT)
  1036. || (target->debug_reason == DBG_REASON_SINGLESTEP)
  1037. || (target->debug_reason == DBG_REASON_WATCHPOINT)
  1038. || (target->debug_reason == DBG_REASON_WPTANDBKPT)
  1039. || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
  1040. context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
  1041. else if (target->debug_reason == DBG_REASON_DBGRQ)
  1042. context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
  1043. else
  1044. {
  1045. LOG_ERROR("unknown debug reason: %i", target->debug_reason);
  1046. }
  1047. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1048. return ERROR_FAIL;
  1049. for (i=0; i<=15; i++)
  1050. {
  1051. LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
  1052. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
  1053. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
  1054. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
  1055. }
  1056. LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
  1057. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1058. return ERROR_FAIL;
  1059. /* exceptions other than USR & SYS have a saved program status register */
  1060. if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
  1061. {
  1062. u32 spsr;
  1063. arm7_9->read_xpsr(target, &spsr, 1);
  1064. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1065. {
  1066. return retval;
  1067. }
  1068. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
  1069. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
  1070. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
  1071. }
  1072. /* r0 and r15 (pc) have to be restored later */
  1073. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
  1074. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
  1075. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1076. return retval;
  1077. if (arm7_9->post_debug_entry)
  1078. arm7_9->post_debug_entry(target);
  1079. return ERROR_OK;
  1080. }
  1081. int arm7_9_full_context(target_t *target)
  1082. {
  1083. int i;
  1084. int retval;
  1085. armv4_5_common_t *armv4_5 = target->arch_info;
  1086. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1087. LOG_DEBUG("-");
  1088. if (target->state != TARGET_HALTED)
  1089. {
  1090. LOG_WARNING("target not halted");
  1091. return ERROR_TARGET_NOT_HALTED;
  1092. }
  1093. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1094. return ERROR_FAIL;
  1095. /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
  1096. * SYS shares registers with User, so we don't touch SYS
  1097. */
  1098. for(i = 0; i < 6; i++)
  1099. {
  1100. u32 mask = 0;
  1101. u32* reg_p[16];
  1102. int j;
  1103. int valid = 1;
  1104. /* check if there are invalid registers in the current mode
  1105. */
  1106. for (j = 0; j <= 16; j++)
  1107. {
  1108. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
  1109. valid = 0;
  1110. }
  1111. if (!valid)
  1112. {
  1113. u32 tmp_cpsr;
  1114. /* change processor mode (and mask T bit) */
  1115. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1116. tmp_cpsr |= armv4_5_number_to_mode(i);
  1117. tmp_cpsr &= ~0x20;
  1118. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1119. for (j = 0; j < 15; j++)
  1120. {
  1121. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
  1122. {
  1123. reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
  1124. mask |= 1 << j;
  1125. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
  1126. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
  1127. }
  1128. }
  1129. /* if only the PSR is invalid, mask is all zeroes */
  1130. if (mask)
  1131. arm7_9->read_core_regs(target, mask, reg_p);
  1132. /* check if the PSR has to be read */
  1133. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
  1134. {
  1135. arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
  1136. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
  1137. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
  1138. }
  1139. }
  1140. }
  1141. /* restore processor mode (mask T bit) */
  1142. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1143. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1144. {
  1145. return retval;
  1146. }
  1147. return ERROR_OK;
  1148. }
  1149. int arm7_9_restore_context(target_t *target)
  1150. {
  1151. armv4_5_common_t *armv4_5 = target->arch_info;
  1152. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1153. reg_t *reg;
  1154. armv4_5_core_reg_t *reg_arch_info;
  1155. enum armv4_5_mode current_mode = armv4_5->core_mode;
  1156. int i, j;
  1157. int dirty;
  1158. int mode_change;
  1159. LOG_DEBUG("-");
  1160. if (target->state != TARGET_HALTED)
  1161. {
  1162. LOG_WARNING("target not halted");
  1163. return ERROR_TARGET_NOT_HALTED;
  1164. }
  1165. if (arm7_9->pre_restore_context)
  1166. arm7_9->pre_restore_context(target);
  1167. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1168. return ERROR_FAIL;
  1169. /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
  1170. * SYS shares registers with User, so we don't touch SYS
  1171. */
  1172. for (i = 0; i < 6; i++)
  1173. {
  1174. LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
  1175. dirty = 0;
  1176. mode_change = 0;
  1177. /* check if there are dirty registers in the current mode
  1178. */
  1179. for (j = 0; j <= 16; j++)
  1180. {
  1181. reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
  1182. reg_arch_info = reg->arch_info;
  1183. if (reg->dirty == 1)
  1184. {
  1185. if (reg->valid == 1)
  1186. {
  1187. dirty = 1;
  1188. LOG_DEBUG("examining dirty reg: %s", reg->name);
  1189. if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
  1190. && (reg_arch_info->mode != current_mode)
  1191. && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
  1192. && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
  1193. {
  1194. mode_change = 1;
  1195. LOG_DEBUG("require mode change");
  1196. }
  1197. }
  1198. else
  1199. {
  1200. LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
  1201. }
  1202. }
  1203. }
  1204. if (dirty)
  1205. {
  1206. u32 mask = 0x0;
  1207. int num_regs = 0;
  1208. u32 regs[16];
  1209. if (mode_change)
  1210. {
  1211. u32 tmp_cpsr;
  1212. /* change processor mode (mask T bit) */
  1213. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1214. tmp_cpsr |= armv4_5_number_to_mode(i);
  1215. tmp_cpsr &= ~0x20;
  1216. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1217. current_mode = armv4_5_number_to_mode(i);
  1218. }
  1219. for (j = 0; j <= 14; j++)
  1220. {
  1221. reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
  1222. reg_arch_info = reg->arch_info;
  1223. if (reg->dirty == 1)
  1224. {
  1225. regs[j] = buf_get_u32(reg->value, 0, 32);
  1226. mask |= 1 << j;
  1227. num_regs++;
  1228. reg->dirty = 0;
  1229. reg->valid = 1;
  1230. LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
  1231. }
  1232. }
  1233. if (mask)
  1234. {
  1235. arm7_9->write_core_regs(target, mask, regs);
  1236. }
  1237. reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
  1238. reg_arch_info = reg->arch_info;
  1239. if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
  1240. {
  1241. LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
  1242. arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
  1243. }
  1244. }
  1245. }
  1246. if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
  1247. {
  1248. /* restore processor mode (mask T bit) */
  1249. u32 tmp_cpsr;
  1250. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1251. tmp_cpsr |= armv4_5_number_to_mode(i);
  1252. tmp_cpsr &= ~0x20;
  1253. LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
  1254. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1255. }
  1256. else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
  1257. {
  1258. /* CPSR has been changed, full restore necessary (mask T bit) */
  1259. LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1260. arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
  1261. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
  1262. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  1263. }
  1264. /* restore PC */
  1265. LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1266. arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1267. armv4_5->core_cache->reg_list[15].dirty = 0;
  1268. if (arm7_9->post_restore_context)
  1269. arm7_9->post_restore_context(target);
  1270. return ERROR_OK;
  1271. }
  1272. int arm7_9_restart_core(struct target_s *target)
  1273. {
  1274. armv4_5_common_t *armv4_5 = target->arch_info;
  1275. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1276. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  1277. /* set RESTART instruction */
  1278. jtag_add_end_state(TAP_RTI);
  1279. if (arm7_9->need_bypass_before_restart) {
  1280. arm7_9->need_bypass_before_restart = 0;
  1281. arm_jtag_set_instr(jtag_info, 0xf, NULL);
  1282. }
  1283. arm_jtag_set_instr(jtag_info, 0x4, NULL);
  1284. jtag_add_runtest(1, TAP_RTI);
  1285. return jtag_execute_queue();
  1286. }
  1287. void arm7_9_enable_watchpoints(struct target_s *target)
  1288. {
  1289. watchpoint_t *watchpoint = target->watchpoints;
  1290. while (watchpoint)
  1291. {
  1292. if (watchpoint->set == 0)
  1293. arm7_9_set_watchpoint(target, watchpoint);
  1294. watchpoint = watchpoint->next;
  1295. }
  1296. }
  1297. void arm7_9_enable_breakpoints(struct target_s *target)
  1298. {
  1299. breakpoint_t *breakpoint = target->breakpoints;
  1300. /* set any pending breakpoints */
  1301. while (breakpoint)
  1302. {
  1303. arm7_9_set_breakpoint(target, breakpoint);
  1304. breakpoint = breakpoint->next;
  1305. }
  1306. }
  1307. int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
  1308. {
  1309. armv4_5_common_t *armv4_5 = target->arch_info;
  1310. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1311. breakpoint_t *breakpoint = target->breakpoints;
  1312. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  1313. int err, retval = ERROR_OK;
  1314. LOG_DEBUG("-");
  1315. if (target->state != TARGET_HALTED)
  1316. {
  1317. LOG_WARNING("target not halted");
  1318. return ERROR_TARGET_NOT_HALTED;
  1319. }
  1320. if (!debug_execution)
  1321. {
  1322. target_free_all_working_areas(target);
  1323. }
  1324. /* current = 1: continue on current pc, otherwise continue at <address> */
  1325. if (!current)
  1326. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
  1327. u32 current_pc;
  1328. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1329. /* the front-end may request us not to handle breakpoints */
  1330. if (handle_breakpoints)
  1331. {
  1332. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
  1333. {
  1334. LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
  1335. if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
  1336. {
  1337. return retval;
  1338. }
  1339. /* calculate PC of next instruction */
  1340. u32 next_pc;
  1341. if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
  1342. {
  1343. u32 current_opcode;
  1344. target_read_u32(target, current_pc, &current_opcode);
  1345. LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
  1346. return retval;
  1347. }
  1348. LOG_DEBUG("enable single-step");
  1349. arm7_9->enable_single_step(target, next_pc);
  1350. target->debug_reason = DBG_REASON_SINGLESTEP;
  1351. if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
  1352. {
  1353. return retval;
  1354. }
  1355. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1356. arm7_9->branch_resume(target);
  1357. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1358. {
  1359. arm7_9->branch_resume_thumb(target);
  1360. }
  1361. else
  1362. {
  1363. LOG_ERROR("unhandled core state");
  1364. return ERROR_FAIL;
  1365. }
  1366. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
  1367. embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
  1368. err = arm7_9_execute_sys_speed(target);
  1369. LOG_DEBUG("disable single-step");
  1370. arm7_9->disable_single_step(target);
  1371. if (err != ERROR_OK)
  1372. {
  1373. if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
  1374. {
  1375. return retval;
  1376. }
  1377. target->state = TARGET_UNKNOWN;
  1378. return err;
  1379. }
  1380. arm7_9_debug_entry(target);
  1381. LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1382. LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
  1383. if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
  1384. {
  1385. return retval;
  1386. }
  1387. }
  1388. }
  1389. /* enable any pending breakpoints and watchpoints */
  1390. arm7_9_enable_breakpoints(target);
  1391. arm7_9_enable_watchpoints(target);
  1392. if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
  1393. {
  1394. return retval;
  1395. }
  1396. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1397. {
  1398. arm7_9->branch_resume(target);
  1399. }
  1400. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1401. {
  1402. arm7_9->branch_resume_thumb(target);
  1403. }
  1404. else
  1405. {
  1406. LOG_ERROR("unhandled core state");
  1407. return ERROR_FAIL;
  1408. }
  1409. /* deassert DBGACK and INTDIS */
  1410. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
  1411. /* INTDIS only when we really resume, not during debug execution */
  1412. if (!debug_execution)
  1413. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
  1414. embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
  1415. if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
  1416. {
  1417. return retval;
  1418. }
  1419. target->debug_reason = DBG_REASON_NOTHALTED;
  1420. if (!debug_execution)
  1421. {
  1422. /* registers are now invalid */
  1423. armv4_5_invalidate_core_regs(target);
  1424. target->state = TARGET_RUNNING;
  1425. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
  1426. {
  1427. return retval;
  1428. }
  1429. }
  1430. else
  1431. {
  1432. target->state = TARGET_DEBUG_RUNNING;
  1433. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
  1434. {
  1435. return retval;
  1436. }
  1437. }
  1438. LOG_DEBUG("target resumed");
  1439. return ERROR_OK;
  1440. }
  1441. void arm7_9_enable_eice_step(target_t *target, u32 next_pc)
  1442. {
  1443. armv4_5_common_t *armv4_5 = target->arch_info;
  1444. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1445. u32 current_pc;
  1446. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1447. if(next_pc != current_pc)
  1448. {
  1449. /* setup an inverse breakpoint on the current PC
  1450. * - comparator 1 matches the current address
  1451. * - rangeout from comparator 1 is connected to comparator 0 rangein
  1452. * - comparator 0 matches any address, as long as rangein is low */
  1453. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
  1454. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  1455. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  1456. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
  1457. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
  1458. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
  1459. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
  1460. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  1461. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  1462. }
  1463. else
  1464. {
  1465. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
  1466. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  1467. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  1468. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
  1469. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
  1470. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
  1471. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
  1472. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  1473. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  1474. }
  1475. }
  1476. void arm7_9_disable_eice_step(target_t *target)
  1477. {
  1478. armv4_5_common_t *armv4_5 = target->arch_info;
  1479. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1480. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
  1481. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
  1482. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
  1483. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
  1484. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
  1485. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
  1486. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
  1487. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
  1488. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
  1489. }
  1490. int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
  1491. {
  1492. armv4_5_common_t *armv4_5 = target->arch_info;
  1493. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1494. breakpoint_t *breakpoint = NULL;
  1495. int err, retval;
  1496. if (target->state != TARGET_HALTED)
  1497. {
  1498. LOG_WARNING("target not halted");
  1499. return ERROR_TARGET_NOT_HALTED;
  1500. }
  1501. /* current = 1: continue on current pc, otherwise continue at <address> */
  1502. if (!current)
  1503. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
  1504. u32 current_pc;
  1505. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1506. /* the front-end may request us not to handle breakpoints */
  1507. if (handle_breakpoints)
  1508. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
  1509. if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
  1510. {
  1511. return retval;
  1512. }
  1513. target->debug_reason = DBG_REASON_SINGLESTEP;
  1514. /* calculate PC of next instruction */
  1515. u32 next_pc;
  1516. if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
  1517. {
  1518. u32 current_opcode;
  1519. target_read_u32(target, current_pc, &current_opcode);
  1520. LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
  1521. return retval;
  1522. }
  1523. if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
  1524. {
  1525. return retval;
  1526. }
  1527. arm7_9->enable_single_step(target, next_pc);
  1528. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1529. {
  1530. arm7_9->branch_resume(target);
  1531. }
  1532. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1533. {
  1534. arm7_9->branch_resume_thumb(target);
  1535. }
  1536. else
  1537. {
  1538. LOG_ERROR("unhandled core state");
  1539. return ERROR_FAIL;
  1540. }
  1541. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
  1542. {
  1543. return retval;
  1544. }
  1545. err = arm7_9_execute_sys_speed(target);
  1546. arm7_9->disable_single_step(target);
  1547. /* registers are now invalid */
  1548. armv4_5_invalidate_core_regs(target);
  1549. if (err != ERROR_OK)
  1550. {
  1551. target->state = TARGET_UNKNOWN;
  1552. } else {
  1553. arm7_9_debug_entry(target);
  1554. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
  1555. {
  1556. return retval;
  1557. }
  1558. LOG_DEBUG("target stepped");
  1559. }
  1560. if (breakpoint)
  1561. if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
  1562. {
  1563. return retval;
  1564. }
  1565. return err;
  1566. }
  1567. int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
  1568. {
  1569. u32* reg_p[16];
  1570. u32 value;
  1571. int retval;
  1572. armv4_5_common_t *armv4_5 = target->arch_info;
  1573. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1574. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1575. return ERROR_FAIL;
  1576. enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
  1577. if ((num < 0) || (num > 16))
  1578. return ERROR_INVALID_ARGUMENTS;
  1579. if ((mode != ARMV4_5_MODE_ANY)
  1580. && (mode != armv4_5->core_mode)
  1581. && (reg_mode != ARMV4_5_MODE_ANY))
  1582. {
  1583. u32 tmp_cpsr;
  1584. /* change processor mode (mask T bit) */
  1585. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1586. tmp_cpsr |= mode;
  1587. tmp_cpsr &= ~0x20;
  1588. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1589. }
  1590. if ((num >= 0) && (num <= 15))
  1591. {
  1592. /* read a normal core register */
  1593. reg_p[num] = &value;
  1594. arm7_9->read_core_regs(target, 1 << num, reg_p);
  1595. }
  1596. else
  1597. {
  1598. /* read a program status register
  1599. * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
  1600. */
  1601. armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
  1602. int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
  1603. arm7_9->read_xpsr(target, &value, spsr);
  1604. }
  1605. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1606. {
  1607. return retval;
  1608. }
  1609. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
  1610. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
  1611. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
  1612. if ((mode != ARMV4_5_MODE_ANY)
  1613. && (mode != armv4_5->core_mode)
  1614. && (reg_mode != ARMV4_5_MODE_ANY)) {
  1615. /* restore processor mode (mask T bit) */
  1616. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1617. }
  1618. return ERROR_OK;
  1619. }
  1620. int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
  1621. {
  1622. u32 reg[16];
  1623. armv4_5_common_t *armv4_5 = target->arch_info;
  1624. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1625. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1626. return ERROR_FAIL;
  1627. enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
  1628. if ((num < 0) || (num > 16))
  1629. return ERROR_INVALID_ARGUMENTS;
  1630. if ((mode != ARMV4_5_MODE_ANY)
  1631. && (mode != armv4_5->core_mode)
  1632. && (reg_mode != ARMV4_5_MODE_ANY)) {
  1633. u32 tmp_cpsr;
  1634. /* change processor mode (mask T bit) */
  1635. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1636. tmp_cpsr |= mode;
  1637. tmp_cpsr &= ~0x20;
  1638. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1639. }
  1640. if ((num >= 0) && (num <= 15))
  1641. {
  1642. /* write a normal core register */
  1643. reg[num] = value;
  1644. arm7_9->write_core_regs(target, 1 << num, reg);
  1645. }
  1646. else
  1647. {
  1648. /* write a program status register
  1649. * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
  1650. */
  1651. armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
  1652. int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
  1653. /* if we're writing the CPSR, mask the T bit */
  1654. if (!spsr)
  1655. value &= ~0x20;
  1656. arm7_9->write_xpsr(target, value, spsr);
  1657. }
  1658. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
  1659. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
  1660. if ((mode != ARMV4_5_MODE_ANY)
  1661. && (mode != armv4_5->core_mode)
  1662. && (reg_mode != ARMV4_5_MODE_ANY)) {
  1663. /* restore processor mode (mask T bit) */
  1664. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1665. }
  1666. return jtag_execute_queue();
  1667. }
  1668. int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  1669. {
  1670. armv4_5_common_t *armv4_5 = target->arch_info;
  1671. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1672. u32 reg[16];
  1673. int num_accesses = 0;
  1674. int thisrun_accesses;
  1675. int i;
  1676. u32 cpsr;
  1677. int retval;
  1678. int last_reg = 0;
  1679. LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
  1680. if (target->state != TARGET_HALTED)
  1681. {
  1682. LOG_WARNING("target not halted");
  1683. return ERROR_TARGET_NOT_HALTED;
  1684. }
  1685. /* sanitize arguments */
  1686. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1687. return ERROR_INVALID_ARGUMENTS;
  1688. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  1689. return ERROR_TARGET_UNALIGNED_ACCESS;
  1690. /* load the base register with the address of the first word */
  1691. reg[0] = address;
  1692. arm7_9->write_core_regs(target, 0x1, reg);
  1693. int j=0;
  1694. switch (size)
  1695. {
  1696. case 4:
  1697. while (num_accesses < count)
  1698. {
  1699. u32 reg_list;
  1700. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1701. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1702. if (last_reg <= thisrun_accesses)
  1703. last_reg = thisrun_accesses;
  1704. arm7_9->load_word_regs(target, reg_list);
  1705. /* fast memory reads are only safe when the target is running
  1706. * from a sufficiently high clock (32 kHz is usually too slow)
  1707. */
  1708. if (arm7_9->fast_memory_access)
  1709. arm7_9_execute_fast_sys_speed(target);
  1710. else
  1711. arm7_9_execute_sys_speed(target);
  1712. arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
  1713. /* advance buffer, count number of accesses */
  1714. buffer += thisrun_accesses * 4;
  1715. num_accesses += thisrun_accesses;
  1716. if ((j++%1024)==0)
  1717. {
  1718. keep_alive();
  1719. }
  1720. }
  1721. break;
  1722. case 2:
  1723. while (num_accesses < count)
  1724. {
  1725. u32 reg_list;
  1726. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1727. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1728. for (i = 1; i <= thisrun_accesses; i++)
  1729. {
  1730. if (i > last_reg)
  1731. last_reg = i;
  1732. arm7_9->load_hword_reg(target, i);
  1733. /* fast memory reads are only safe when the target is running
  1734. * from a sufficiently high clock (32 kHz is usually too slow)
  1735. */
  1736. if (arm7_9->fast_memory_access)
  1737. retval = arm7_9_execute_fast_sys_speed(target);
  1738. else
  1739. retval = arm7_9_execute_sys_speed(target);
  1740. if(retval != ERROR_OK)
  1741. {
  1742. return retval;
  1743. }
  1744. }
  1745. arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
  1746. /* advance buffer, count number of accesses */
  1747. buffer += thisrun_accesses * 2;
  1748. num_accesses += thisrun_accesses;
  1749. if ((j++%1024)==0)
  1750. {
  1751. keep_alive();
  1752. }
  1753. }
  1754. break;
  1755. case 1:
  1756. while (num_accesses < count)
  1757. {
  1758. u32 reg_list;
  1759. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1760. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1761. for (i = 1; i <= thisrun_accesses; i++)
  1762. {
  1763. if (i > last_reg)
  1764. last_reg = i;
  1765. arm7_9->load_byte_reg(target, i);
  1766. /* fast memory reads are only safe when the target is running
  1767. * from a sufficiently high clock (32 kHz is usually too slow)
  1768. */
  1769. if (arm7_9->fast_memory_access)
  1770. retval = arm7_9_execute_fast_sys_speed(target);
  1771. else
  1772. retval = arm7_9_execute_sys_speed(target);
  1773. if(retval != ERROR_OK)
  1774. {
  1775. return retval;
  1776. }
  1777. }
  1778. arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
  1779. /* advance buffer, count number of accesses */
  1780. buffer += thisrun_accesses * 1;
  1781. num_accesses += thisrun_accesses;
  1782. if ((j++%1024)==0)
  1783. {
  1784. keep_alive();
  1785. }
  1786. }
  1787. break;
  1788. default:
  1789. LOG_ERROR("BUG: we shouldn't get here");
  1790. exit(-1);
  1791. break;
  1792. }
  1793. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1794. return ERROR_FAIL;
  1795. for (i=0; i<=last_reg; i++)
  1796. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
  1797. arm7_9->read_xpsr(target, &cpsr, 0);
  1798. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1799. {
  1800. LOG_ERROR("JTAG error while reading cpsr");
  1801. return ERROR_TARGET_DATA_ABORT;
  1802. }
  1803. if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
  1804. {
  1805. LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
  1806. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1807. return ERROR_TARGET_DATA_ABORT;
  1808. }
  1809. return ERROR_OK;
  1810. }
  1811. int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  1812. {
  1813. armv4_5_common_t *armv4_5 = target->arch_info;
  1814. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1815. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  1816. u32 reg[16];
  1817. int num_accesses = 0;
  1818. int thisrun_accesses;
  1819. int i;
  1820. u32 cpsr;
  1821. int retval;
  1822. int last_reg = 0;
  1823. #ifdef _DEBUG_ARM7_9_
  1824. LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
  1825. #endif
  1826. if (target->state != TARGET_HALTED)
  1827. {
  1828. LOG_WARNING("target not halted");
  1829. return ERROR_TARGET_NOT_HALTED;
  1830. }
  1831. /* sanitize arguments */
  1832. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1833. return ERROR_INVALID_ARGUMENTS;
  1834. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  1835. return ERROR_TARGET_UNALIGNED_ACCESS;
  1836. /* load the base register with the address of the first word */
  1837. reg[0] = address;
  1838. arm7_9->write_core_regs(target, 0x1, reg);
  1839. /* Clear DBGACK, to make sure memory fetches work as expected */
  1840. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
  1841. embeddedice_store_reg(dbg_ctrl);
  1842. switch (size)
  1843. {
  1844. case 4:
  1845. while (num_accesses < count)
  1846. {
  1847. u32 reg_list;
  1848. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1849. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1850. for (i = 1; i <= thisrun_accesses; i++)
  1851. {
  1852. if (i > last_reg)
  1853. last_reg = i;
  1854. reg[i] = target_buffer_get_u32(target, buffer);
  1855. buffer += 4;
  1856. }
  1857. arm7_9->write_core_regs(target, reg_list, reg);
  1858. arm7_9->store_word_regs(target, reg_list);
  1859. /* fast memory writes are only safe when the target is running
  1860. * from a sufficiently high clock (32 kHz is usually too slow)
  1861. */
  1862. if (arm7_9->fast_memory_access)
  1863. retval = arm7_9_execute_fast_sys_speed(target);
  1864. else
  1865. retval = arm7_9_execute_sys_speed(target);
  1866. if(retval != ERROR_OK)
  1867. {
  1868. return retval;
  1869. }
  1870. num_accesses += thisrun_accesses;
  1871. }
  1872. break;
  1873. case 2:
  1874. while (num_accesses < count)
  1875. {
  1876. u32 reg_list;
  1877. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1878. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1879. for (i = 1; i <= thisrun_accesses; i++)
  1880. {
  1881. if (i > last_reg)
  1882. last_reg = i;
  1883. reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
  1884. buffer += 2;
  1885. }
  1886. arm7_9->write_core_regs(target, reg_list, reg);
  1887. for (i = 1; i <= thisrun_accesses; i++)
  1888. {
  1889. arm7_9->store_hword_reg(target, i);
  1890. /* fast memory writes are only safe when the target is running
  1891. * from a sufficiently high clock (32 kHz is usually too slow)
  1892. */
  1893. if (arm7_9->fast_memory_access)
  1894. retval = arm7_9_execute_fast_sys_speed(target);
  1895. else
  1896. retval = arm7_9_execute_sys_speed(target);
  1897. if(retval != ERROR_OK)
  1898. {
  1899. return retval;
  1900. }
  1901. }
  1902. num_accesses += thisrun_accesses;
  1903. }
  1904. break;
  1905. case 1:
  1906. while (num_accesses < count)
  1907. {
  1908. u32 reg_list;
  1909. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1910. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1911. for (i = 1; i <= thisrun_accesses; i++)
  1912. {
  1913. if (i > last_reg)
  1914. last_reg = i;
  1915. reg[i] = *buffer++ & 0xff;
  1916. }
  1917. arm7_9->write_core_regs(target, reg_list, reg);
  1918. for (i = 1; i <= thisrun_accesses; i++)
  1919. {
  1920. arm7_9->store_byte_reg(target, i);
  1921. /* fast memory writes are only safe when the target is running
  1922. * from a sufficiently high clock (32 kHz is usually too slow)
  1923. */
  1924. if (arm7_9->fast_memory_access)
  1925. retval = arm7_9_execute_fast_sys_speed(target);
  1926. else
  1927. retval = arm7_9_execute_sys_speed(target);
  1928. if(retval != ERROR_OK)
  1929. {
  1930. return retval;
  1931. }
  1932. }
  1933. num_accesses += thisrun_accesses;
  1934. }
  1935. break;
  1936. default:
  1937. LOG_ERROR("BUG: we shouldn't get here");
  1938. exit(-1);
  1939. break;
  1940. }
  1941. /* Re-Set DBGACK */
  1942. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
  1943. embeddedice_store_reg(dbg_ctrl);
  1944. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  1945. return ERROR_FAIL;
  1946. for (i=0; i<=last_reg; i++)
  1947. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
  1948. arm7_9->read_xpsr(target, &cpsr, 0);
  1949. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1950. {
  1951. LOG_ERROR("JTAG error while reading cpsr");
  1952. return ERROR_TARGET_DATA_ABORT;
  1953. }
  1954. if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
  1955. {
  1956. LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
  1957. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1958. return ERROR_TARGET_DATA_ABORT;
  1959. }
  1960. return ERROR_OK;
  1961. }
  1962. static int dcc_count;
  1963. static u8 *dcc_buffer;
  1964. static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
  1965. {
  1966. int retval = ERROR_OK;
  1967. armv4_5_common_t *armv4_5 = target->arch_info;
  1968. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1969. if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
  1970. return retval;
  1971. int little=target->endianness==TARGET_LITTLE_ENDIAN;
  1972. int count=dcc_count;
  1973. u8 *buffer=dcc_buffer;
  1974. if (count>2)
  1975. {
  1976. /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
  1977. core function repeated.
  1978. */
  1979. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
  1980. buffer+=4;
  1981. embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
  1982. u8 reg_addr = ice_reg->addr & 0x1f;
  1983. int chain_pos = ice_reg->jtag_info->chain_pos;
  1984. embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
  1985. buffer += (count-2)*4;
  1986. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
  1987. } else
  1988. {
  1989. int i;
  1990. for (i = 0; i < count; i++)
  1991. {
  1992. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
  1993. buffer += 4;
  1994. }
  1995. }
  1996. if((retval = target_halt(target))!= ERROR_OK)
  1997. {
  1998. return retval;
  1999. }
  2000. return target_wait_state(target, TARGET_HALTED, 500);
  2001. }
  2002. static const u32 dcc_code[] =
  2003. {
  2004. /* MRC TST BNE MRC STR B */
  2005. 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
  2006. };
  2007. int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
  2008. int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
  2009. {
  2010. int retval;
  2011. armv4_5_common_t *armv4_5 = target->arch_info;
  2012. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  2013. int i;
  2014. if (!arm7_9->dcc_downloads)
  2015. return target->type->write_memory(target, address, 4, count, buffer);
  2016. /* regrab previously allocated working_area, or allocate a new one */
  2017. if (!arm7_9->dcc_working_area)
  2018. {
  2019. u8 dcc_code_buf[6 * 4];
  2020. /* make sure we have a working area */
  2021. if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
  2022. {
  2023. LOG_INFO("no working area available, falling back to memory writes");
  2024. return target->type->write_memory(target, address, 4, count, buffer);
  2025. }
  2026. /* copy target instructions to target endianness */
  2027. for (i = 0; i < 6; i++)
  2028. {
  2029. target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
  2030. }
  2031. /* write DCC code to working area */
  2032. if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
  2033. {
  2034. return retval;
  2035. }
  2036. }
  2037. armv4_5_algorithm_t armv4_5_info;
  2038. reg_param_t reg_params[1];
  2039. armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
  2040. armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
  2041. armv4_5_info.core_state = ARMV4_5_STATE_ARM;
  2042. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
  2043. buf_set_u32(reg_params[0].value, 0, 32, address);
  2044. //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
  2045. // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
  2046. dcc_count=count;
  2047. dcc_buffer=buffer;
  2048. retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
  2049. arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
  2050. if (retval==ERROR_OK)
  2051. {
  2052. u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32);
  2053. if (endaddress!=(address+count*4))
  2054. {
  2055. LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
  2056. retval=ERROR_FAIL;
  2057. }
  2058. }
  2059. destroy_reg_param(&reg_params[0]);
  2060. return retval;
  2061. }
  2062. int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
  2063. {
  2064. working_area_t *crc_algorithm;
  2065. armv4_5_algorithm_t armv4_5_info;
  2066. reg_param_t reg_params[2];
  2067. int retval;
  2068. u32 arm7_9_crc_code[] = {
  2069. 0xE1A02000, /* mov r2, r0 */
  2070. 0xE3E00000, /* mov r0, #0xffffffff */
  2071. 0xE1A03001, /* mov r3, r1 */
  2072. 0xE3A04000, /* mov r4, #0 */
  2073. 0xEA00000B, /* b ncomp */
  2074. /* nbyte: */
  2075. 0xE7D21004, /* ldrb r1, [r2, r4] */
  2076. 0xE59F7030, /* ldr r7, CRC32XOR */
  2077. 0xE0200C01, /* eor r0, r0, r1, asl 24 */
  2078. 0xE3A05000, /* mov r5, #0 */
  2079. /* loop: */
  2080. 0xE3500000, /* cmp r0, #0 */
  2081. 0xE1A06080, /* mov r6, r0, asl #1 */
  2082. 0xE2855001, /* add r5, r5, #1 */
  2083. 0xE1A00006, /* mov r0, r6 */
  2084. 0xB0260007, /* eorlt r0, r6, r7 */
  2085. 0xE3550008, /* cmp r5, #8 */
  2086. 0x1AFFFFF8, /* bne loop */
  2087. 0xE2844001, /* add r4, r4, #1 */
  2088. /* ncomp: */
  2089. 0xE1540003, /* cmp r4, r3 */
  2090. 0x1AFFFFF1, /* bne nbyte */
  2091. /* end: */
  2092. 0xEAFFFFFE, /* b end */
  2093. 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
  2094. };
  2095. int i;
  2096. if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
  2097. {
  2098. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  2099. }
  2100. /* convert flash writing code into a buffer in target endianness */
  2101. for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
  2102. {
  2103. if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK)
  2104. {
  2105. return retval;
  2106. }
  2107. }
  2108. armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
  2109. armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
  2110. armv4_5_info.core_state = ARMV4_5_STATE_ARM;
  2111. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
  2112. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  2113. buf_set_u32(reg_params[0].value, 0, 32, address);
  2114. buf_set_u32(reg_params[1].value, 0, 32, count);
  2115. if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
  2116. crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
  2117. {
  2118. LOG_ERROR("error executing arm7_9 crc algorithm");
  2119. destroy_reg_param(&reg_params[0]);
  2120. destroy_reg_param(&reg_params[1]);
  2121. target_free_working_area(target, crc_algorithm);
  2122. return retval;
  2123. }
  2124. *checksum = buf_get_u32(reg_params[0].value, 0, 32);
  2125. destroy_reg_param(&reg_params[0]);
  2126. destroy_reg_param(&reg_params[1]);
  2127. target_free_working_area(target, crc_algorithm);
  2128. return ERROR_OK;
  2129. }
  2130. int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
  2131. {
  2132. working_area_t *erase_check_algorithm;
  2133. reg_param_t reg_params[3];
  2134. armv4_5_algorithm_t armv4_5_info;
  2135. int retval;
  2136. int i;
  2137. u32 erase_check_code[] =
  2138. {
  2139. /* loop: */
  2140. 0xe4d03001, /* ldrb r3, [r0], #1 */
  2141. 0xe0022003, /* and r2, r2, r3 */
  2142. 0xe2511001, /* subs r1, r1, #1 */
  2143. 0x1afffffb, /* bne loop */
  2144. /* end: */
  2145. 0xeafffffe /* b end */
  2146. };
  2147. /* make sure we have a working area */
  2148. if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
  2149. {
  2150. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  2151. }
  2152. /* convert flash writing code into a buffer in target endianness */
  2153. for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
  2154. if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
  2155. {
  2156. return retval;
  2157. }
  2158. armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
  2159. armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
  2160. armv4_5_info.core_state = ARMV4_5_STATE_ARM;
  2161. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  2162. buf_set_u32(reg_params[0].value, 0, 32, address);
  2163. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  2164. buf_set_u32(reg_params[1].value, 0, 32, count);
  2165. init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
  2166. buf_set_u32(reg_params[2].value, 0, 32, 0xff);
  2167. if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
  2168. erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
  2169. {
  2170. destroy_reg_param(&reg_params[0]);
  2171. destroy_reg_param(&reg_params[1]);
  2172. destroy_reg_param(&reg_params[2]);
  2173. target_free_working_area(target, erase_check_algorithm);
  2174. return 0;
  2175. }
  2176. *blank = buf_get_u32(reg_params[2].value, 0, 32);
  2177. destroy_reg_param(&reg_params[0]);
  2178. destroy_reg_param(&reg_params[1]);
  2179. destroy_reg_param(&reg_params[2]);
  2180. target_free_working_area(target, erase_check_algorithm);
  2181. return ERROR_OK;
  2182. }
  2183. int arm7_9_register_commands(struct command_context_s *cmd_ctx)
  2184. {
  2185. command_t *arm7_9_cmd;
  2186. arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
  2187. register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
  2188. register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
  2189. register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
  2190. register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
  2191. COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
  2192. register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
  2193. COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
  2194. register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
  2195. COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
  2196. register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
  2197. COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
  2198. armv4_5_register_commands(cmd_ctx);
  2199. etm_register_commands(cmd_ctx);
  2200. return ERROR_OK;
  2201. }
  2202. int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2203. {
  2204. u32 value;
  2205. int spsr;
  2206. int retval;
  2207. target_t *target = get_current_target(cmd_ctx);
  2208. armv4_5_common_t *armv4_5;
  2209. arm7_9_common_t *arm7_9;
  2210. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2211. {
  2212. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2213. return ERROR_OK;
  2214. }
  2215. if (target->state != TARGET_HALTED)
  2216. {
  2217. command_print(cmd_ctx, "can't write registers while running");
  2218. return ERROR_OK;
  2219. }
  2220. if (argc < 2)
  2221. {
  2222. command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
  2223. return ERROR_OK;
  2224. }
  2225. value = strtoul(args[0], NULL, 0);
  2226. spsr = strtol(args[1], NULL, 0);
  2227. /* if we're writing the CPSR, mask the T bit */
  2228. if (!spsr)
  2229. value &= ~0x20;
  2230. arm7_9->write_xpsr(target, value, spsr);
  2231. if ((retval = jtag_execute_queue()) != ERROR_OK)
  2232. {
  2233. LOG_ERROR("JTAG error while writing to xpsr");
  2234. return retval;
  2235. }
  2236. return ERROR_OK;
  2237. }
  2238. int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2239. {
  2240. u32 value;
  2241. int rotate;
  2242. int spsr;
  2243. int retval;
  2244. target_t *target = get_current_target(cmd_ctx);
  2245. armv4_5_common_t *armv4_5;
  2246. arm7_9_common_t *arm7_9;
  2247. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2248. {
  2249. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2250. return ERROR_OK;
  2251. }
  2252. if (target->state != TARGET_HALTED)
  2253. {
  2254. command_print(cmd_ctx, "can't write registers while running");
  2255. return ERROR_OK;
  2256. }
  2257. if (argc < 3)
  2258. {
  2259. command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
  2260. return ERROR_OK;
  2261. }
  2262. value = strtoul(args[0], NULL, 0);
  2263. rotate = strtol(args[1], NULL, 0);
  2264. spsr = strtol(args[2], NULL, 0);
  2265. arm7_9->write_xpsr_im8(target, value, rotate, spsr);
  2266. if ((retval = jtag_execute_queue()) != ERROR_OK)
  2267. {
  2268. LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
  2269. return retval;
  2270. }
  2271. return ERROR_OK;
  2272. }
  2273. int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2274. {
  2275. u32 value;
  2276. u32 mode;
  2277. int num;
  2278. target_t *target = get_current_target(cmd_ctx);
  2279. armv4_5_common_t *armv4_5;
  2280. arm7_9_common_t *arm7_9;
  2281. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2282. {
  2283. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2284. return ERROR_OK;
  2285. }
  2286. if (target->state != TARGET_HALTED)
  2287. {
  2288. command_print(cmd_ctx, "can't write registers while running");
  2289. return ERROR_OK;
  2290. }
  2291. if (argc < 3)
  2292. {
  2293. command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
  2294. return ERROR_OK;
  2295. }
  2296. num = strtol(args[0], NULL, 0);
  2297. mode = strtoul(args[1], NULL, 0);
  2298. value = strtoul(args[2], NULL, 0);
  2299. return arm7_9_write_core_reg(target, num, mode, value);
  2300. }
  2301. int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2302. {
  2303. target_t *target = get_current_target(cmd_ctx);
  2304. armv4_5_common_t *armv4_5;
  2305. arm7_9_common_t *arm7_9;
  2306. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2307. {
  2308. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2309. return ERROR_OK;
  2310. }
  2311. if (argc > 0)
  2312. {
  2313. if (strcmp("enable", args[0]) == 0)
  2314. {
  2315. arm7_9->use_dbgrq = 1;
  2316. }
  2317. else if (strcmp("disable", args[0]) == 0)
  2318. {
  2319. arm7_9->use_dbgrq = 0;
  2320. }
  2321. else
  2322. {
  2323. command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
  2324. }
  2325. }
  2326. command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
  2327. return ERROR_OK;
  2328. }
  2329. int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2330. {
  2331. target_t *target = get_current_target(cmd_ctx);
  2332. armv4_5_common_t *armv4_5;
  2333. arm7_9_common_t *arm7_9;
  2334. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2335. {
  2336. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2337. return ERROR_OK;
  2338. }
  2339. if (argc > 0)
  2340. {
  2341. if (strcmp("enable", args[0]) == 0)
  2342. {
  2343. arm7_9->fast_memory_access = 1;
  2344. }
  2345. else if (strcmp("disable", args[0]) == 0)
  2346. {
  2347. arm7_9->fast_memory_access = 0;
  2348. }
  2349. else
  2350. {
  2351. command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
  2352. }
  2353. }
  2354. command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
  2355. return ERROR_OK;
  2356. }
  2357. int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2358. {
  2359. target_t *target = get_current_target(cmd_ctx);
  2360. armv4_5_common_t *armv4_5;
  2361. arm7_9_common_t *arm7_9;
  2362. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2363. {
  2364. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2365. return ERROR_OK;
  2366. }
  2367. if (argc > 0)
  2368. {
  2369. if (strcmp("enable", args[0]) == 0)
  2370. {
  2371. arm7_9->dcc_downloads = 1;
  2372. }
  2373. else if (strcmp("disable", args[0]) == 0)
  2374. {
  2375. arm7_9->dcc_downloads = 0;
  2376. }
  2377. else
  2378. {
  2379. command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
  2380. }
  2381. }
  2382. command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
  2383. return ERROR_OK;
  2384. }
  2385. int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
  2386. {
  2387. int retval = ERROR_OK;
  2388. armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
  2389. arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
  2390. if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
  2391. {
  2392. return retval;
  2393. }
  2394. arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
  2395. arm7_9->wp_available_max = 2;
  2396. arm7_9->sw_breakpoints_added = 0;
  2397. arm7_9->breakpoint_count = 0;
  2398. arm7_9->wp0_used = 0;
  2399. arm7_9->wp1_used = 0;
  2400. arm7_9->wp1_used_default = 0;
  2401. arm7_9->use_dbgrq = 0;
  2402. arm7_9->etm_ctx = NULL;
  2403. arm7_9->has_single_step = 0;
  2404. arm7_9->has_monitor_mode = 0;
  2405. arm7_9->has_vector_catch = 0;
  2406. arm7_9->debug_entry_from_reset = 0;
  2407. arm7_9->dcc_working_area = NULL;
  2408. arm7_9->fast_memory_access = fast_and_dangerous;
  2409. arm7_9->dcc_downloads = fast_and_dangerous;
  2410. arm7_9->need_bypass_before_restart = 0;
  2411. armv4_5->arch_info = arm7_9;
  2412. armv4_5->read_core_reg = arm7_9_read_core_reg;
  2413. armv4_5->write_core_reg = arm7_9_write_core_reg;
  2414. armv4_5->full_context = arm7_9_full_context;
  2415. if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
  2416. {
  2417. return retval;
  2418. }
  2419. if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
  2420. {
  2421. return retval;
  2422. }
  2423. return ERROR_OK;
  2424. }