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  1. /***************************************************************************
  2. * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc., *
  17. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  18. ***************************************************************************/
  19. #ifdef HAVE_CONFIG_H
  20. #include "config.h"
  21. #endif
  22. #include "mflash.h"
  23. #include <target/target.h>
  24. #include <helper/time_support.h>
  25. #include <helper/fileio.h>
  26. #include <helper/log.h>
  27. static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio);
  28. static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val);
  29. static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio);
  30. static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val);
  31. static struct mflash_bank *mflash_bank;
  32. static struct mflash_gpio_drv pxa270_gpio = {
  33. .name = "pxa270",
  34. .set_gpio_to_output = pxa270_set_gpio_to_output,
  35. .set_gpio_output_val = pxa270_set_gpio_output_val
  36. };
  37. static struct mflash_gpio_drv s3c2440_gpio = {
  38. .name = "s3c2440",
  39. .set_gpio_to_output = s3c2440_set_gpio_to_output,
  40. .set_gpio_output_val = s3c2440_set_gpio_output_val
  41. };
  42. static struct mflash_gpio_drv *mflash_gpio[] =
  43. {
  44. &pxa270_gpio,
  45. &s3c2440_gpio,
  46. NULL
  47. };
  48. #define PXA270_GAFR0_L 0x40E00054
  49. #define PXA270_GAFR3_U 0x40E00070
  50. #define PXA270_GAFR3_U_RESERVED_BITS 0xfffc0000u
  51. #define PXA270_GPDR0 0x40E0000C
  52. #define PXA270_GPDR3 0x40E0010C
  53. #define PXA270_GPDR3_RESERVED_BITS 0xfe000000u
  54. #define PXA270_GPSR0 0x40E00018
  55. #define PXA270_GPCR0 0x40E00024
  56. static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio)
  57. {
  58. uint32_t addr, value, mask;
  59. struct target *target = mflash_bank->target;
  60. int ret;
  61. /* remove alternate function. */
  62. mask = 0x3u << (gpio.num & 0xF)*2;
  63. addr = PXA270_GAFR0_L + (gpio.num >> 4) * 4;
  64. if ((ret = target_read_u32(target, addr, &value)) != ERROR_OK)
  65. return ret;
  66. value &= ~mask;
  67. if (addr == PXA270_GAFR3_U)
  68. value &= ~PXA270_GAFR3_U_RESERVED_BITS;
  69. if ((ret = target_write_u32(target, addr, value)) != ERROR_OK)
  70. return ret;
  71. /* set direction to output */
  72. mask = 0x1u << (gpio.num & 0x1F);
  73. addr = PXA270_GPDR0 + (gpio.num >> 5) * 4;
  74. if ((ret = target_read_u32(target, addr, &value)) != ERROR_OK)
  75. return ret;
  76. value |= mask;
  77. if (addr == PXA270_GPDR3)
  78. value &= ~PXA270_GPDR3_RESERVED_BITS;
  79. ret = target_write_u32(target, addr, value);
  80. return ret;
  81. }
  82. static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val)
  83. {
  84. uint32_t addr, value, mask;
  85. struct target *target = mflash_bank->target;
  86. int ret;
  87. mask = 0x1u << (gpio.num & 0x1F);
  88. if (val) {
  89. addr = PXA270_GPSR0 + (gpio.num >> 5) * 4;
  90. } else {
  91. addr = PXA270_GPCR0 + (gpio.num >> 5) * 4;
  92. }
  93. if ((ret = target_read_u32(target, addr, &value)) != ERROR_OK)
  94. return ret;
  95. value |= mask;
  96. ret = target_write_u32(target, addr, value);
  97. return ret;
  98. }
  99. #define S3C2440_GPACON 0x56000000
  100. #define S3C2440_GPADAT 0x56000004
  101. #define S3C2440_GPJCON 0x560000d0
  102. #define S3C2440_GPJDAT 0x560000d4
  103. static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio)
  104. {
  105. uint32_t data, mask, gpio_con;
  106. struct target *target = mflash_bank->target;
  107. int ret;
  108. if (gpio.port[0] >= 'a' && gpio.port[0] <= 'h') {
  109. gpio_con = S3C2440_GPACON + (gpio.port[0] - 'a') * 0x10;
  110. } else if (gpio.port[0] == 'j') {
  111. gpio_con = S3C2440_GPJCON;
  112. } else {
  113. LOG_ERROR("mflash: invalid port %d%s", gpio.num, gpio.port);
  114. return ERROR_INVALID_ARGUMENTS;
  115. }
  116. ret = target_read_u32(target, gpio_con, &data);
  117. if (ret == ERROR_OK) {
  118. if (gpio.port[0] == 'a') {
  119. mask = 1 << gpio.num;
  120. data &= ~mask;
  121. } else {
  122. mask = 3 << gpio.num * 2;
  123. data &= ~mask;
  124. data |= (1 << gpio.num * 2);
  125. }
  126. ret = target_write_u32(target, gpio_con, data);
  127. }
  128. return ret;
  129. }
  130. static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val)
  131. {
  132. uint32_t data, mask, gpio_dat;
  133. struct target *target = mflash_bank->target;
  134. int ret;
  135. if (gpio.port[0] >= 'a' && gpio.port[0] <= 'h') {
  136. gpio_dat = S3C2440_GPADAT + (gpio.port[0] - 'a') * 0x10;
  137. } else if (gpio.port[0] == 'j') {
  138. gpio_dat = S3C2440_GPJDAT;
  139. } else {
  140. LOG_ERROR("mflash: invalid port %d%s", gpio.num, gpio.port);
  141. return ERROR_INVALID_ARGUMENTS;
  142. }
  143. ret = target_read_u32(target, gpio_dat, &data);
  144. if (ret == ERROR_OK) {
  145. mask = 1 << gpio.num;
  146. if (val)
  147. data |= mask;
  148. else
  149. data &= ~mask;
  150. ret = target_write_u32(target, gpio_dat, data);
  151. }
  152. return ret;
  153. }
  154. static int mg_hdrst(uint8_t level)
  155. {
  156. return mflash_bank->gpio_drv->set_gpio_output_val(mflash_bank->rst_pin, level);
  157. }
  158. static int mg_init_gpio (void)
  159. {
  160. int ret;
  161. struct mflash_gpio_drv *gpio_drv = mflash_bank->gpio_drv;
  162. ret = gpio_drv->set_gpio_to_output(mflash_bank->rst_pin);
  163. if (ret != ERROR_OK)
  164. return ret;
  165. ret = gpio_drv->set_gpio_output_val(mflash_bank->rst_pin, 1);
  166. return ret;
  167. }
  168. static int mg_dsk_wait(mg_io_type_wait wait_local, uint32_t time_var)
  169. {
  170. uint8_t status, error;
  171. struct target *target = mflash_bank->target;
  172. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  173. int ret;
  174. long long t = 0;
  175. struct duration bench;
  176. duration_start(&bench);
  177. while (time_var) {
  178. ret = target_read_u8(target, mg_task_reg + MG_REG_STATUS, &status);
  179. if (ret != ERROR_OK)
  180. return ret;
  181. if (status & mg_io_rbit_status_busy)
  182. {
  183. if (wait_local == mg_io_wait_bsy)
  184. return ERROR_OK;
  185. } else {
  186. switch (wait_local)
  187. {
  188. case mg_io_wait_not_bsy:
  189. return ERROR_OK;
  190. case mg_io_wait_rdy_noerr:
  191. if (status & mg_io_rbit_status_ready)
  192. return ERROR_OK;
  193. break;
  194. case mg_io_wait_drq_noerr:
  195. if (status & mg_io_rbit_status_data_req)
  196. return ERROR_OK;
  197. break;
  198. default:
  199. break;
  200. }
  201. /* Now we check the error condition! */
  202. if (status & mg_io_rbit_status_error)
  203. {
  204. ret = target_read_u8(target, mg_task_reg + MG_REG_ERROR, &error);
  205. if (ret != ERROR_OK)
  206. return ret;
  207. LOG_ERROR("mflash: io error 0x%02x", error);
  208. return ERROR_MG_IO;
  209. }
  210. switch (wait_local)
  211. {
  212. case mg_io_wait_rdy:
  213. if (status & mg_io_rbit_status_ready)
  214. return ERROR_OK;
  215. case mg_io_wait_drq:
  216. if (status & mg_io_rbit_status_data_req)
  217. return ERROR_OK;
  218. default:
  219. break;
  220. }
  221. }
  222. ret = duration_measure(&bench);
  223. if (ERROR_OK == ret)
  224. t = duration_elapsed(&bench) * 1000.0;
  225. else
  226. LOG_ERROR("mflash: duration measurement failed: %d", ret);
  227. if (t > time_var)
  228. break;
  229. }
  230. LOG_ERROR("mflash: timeout occured");
  231. return ERROR_MG_TIMEOUT;
  232. }
  233. static int mg_dsk_srst(uint8_t on)
  234. {
  235. struct target *target = mflash_bank->target;
  236. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  237. uint8_t value;
  238. int ret;
  239. if ((ret = target_read_u8(target, mg_task_reg + MG_REG_DRV_CTRL, &value)) != ERROR_OK)
  240. return ret;
  241. if (on) {
  242. value |= (mg_io_rbit_devc_srst);
  243. } else {
  244. value &= ~mg_io_rbit_devc_srst;
  245. }
  246. ret = target_write_u8(target, mg_task_reg + MG_REG_DRV_CTRL, value);
  247. return ret;
  248. }
  249. static int mg_dsk_io_cmd(uint32_t sect_num, uint32_t cnt, uint8_t cmd)
  250. {
  251. struct target *target = mflash_bank->target;
  252. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  253. uint8_t value;
  254. int ret;
  255. ret = mg_dsk_wait(mg_io_wait_rdy_noerr, MG_OEM_DISK_WAIT_TIME_NORMAL);
  256. if (ret != ERROR_OK)
  257. return ret;
  258. value = mg_io_rval_dev_drv_master | mg_io_rval_dev_lba_mode |((sect_num >> 24) & 0xf);
  259. ret = target_write_u8(target, mg_task_reg + MG_REG_DRV_HEAD, value);
  260. ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_CNT, (uint8_t)cnt);
  261. ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_NUM, (uint8_t)sect_num);
  262. ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_LOW, (uint8_t)(sect_num >> 8));
  263. ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_HIGH, (uint8_t)(sect_num >> 16));
  264. if (ret != ERROR_OK)
  265. return ret;
  266. return target_write_u8(target, mg_task_reg + MG_REG_COMMAND, cmd);
  267. }
  268. static int mg_dsk_drv_info(void)
  269. {
  270. struct target *target = mflash_bank->target;
  271. uint32_t mg_buff = mflash_bank->base + MG_BUFFER_OFFSET;
  272. int ret;
  273. if ((ret = mg_dsk_io_cmd(0, 1, mg_io_cmd_identify)) != ERROR_OK)
  274. return ret;
  275. ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL);
  276. if (ret != ERROR_OK)
  277. return ret;
  278. LOG_INFO("mflash: read drive info");
  279. if (! mflash_bank->drv_info)
  280. mflash_bank->drv_info = malloc(sizeof(struct mg_drv_info));
  281. ret = target_read_memory(target, mg_buff, 2,
  282. sizeof(mg_io_type_drv_info) >> 1,
  283. (uint8_t *)&mflash_bank->drv_info->drv_id);
  284. if (ret != ERROR_OK)
  285. return ret;
  286. mflash_bank->drv_info->tot_sects = (uint32_t)(mflash_bank->drv_info->drv_id.total_user_addressable_sectors_hi << 16)
  287. + mflash_bank->drv_info->drv_id.total_user_addressable_sectors_lo;
  288. return target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_read);
  289. }
  290. static int mg_mflash_rst(void)
  291. {
  292. int ret;
  293. if ((ret = mg_init_gpio()) != ERROR_OK)
  294. return ret;
  295. if ((ret = mg_hdrst(0)) != ERROR_OK)
  296. return ret;
  297. if ((ret = mg_dsk_wait(mg_io_wait_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  298. return ret;
  299. if ((ret = mg_hdrst(1)) != ERROR_OK)
  300. return ret;
  301. if ((ret = mg_dsk_wait(mg_io_wait_not_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  302. return ret;
  303. if ((ret = mg_dsk_srst(1)) != ERROR_OK)
  304. return ret;
  305. if ((ret = mg_dsk_wait(mg_io_wait_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  306. return ret;
  307. if ((ret = mg_dsk_srst(0)) != ERROR_OK)
  308. return ret;
  309. if ((ret = mg_dsk_wait(mg_io_wait_not_bsy, MG_OEM_DISK_WAIT_TIME_LONG)) != ERROR_OK)
  310. return ret;
  311. LOG_INFO("mflash: reset ok");
  312. return ERROR_OK;
  313. }
  314. static int mg_mflash_probe(void)
  315. {
  316. int ret;
  317. if ((ret = mg_mflash_rst()) != ERROR_OK)
  318. return ret;
  319. return mg_dsk_drv_info();
  320. }
  321. COMMAND_HANDLER(mg_probe_cmd)
  322. {
  323. int ret;
  324. ret = mg_mflash_probe();
  325. if (ret == ERROR_OK) {
  326. command_print(CMD_CTX, "mflash (total %" PRIu32 " sectors) found at 0x%8.8" PRIx32 "",
  327. mflash_bank->drv_info->tot_sects, mflash_bank->base);
  328. }
  329. return ret;
  330. }
  331. static int mg_mflash_do_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt)
  332. {
  333. uint32_t i, address;
  334. int ret;
  335. struct target *target = mflash_bank->target;
  336. uint8_t *buff_ptr = buff;
  337. if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, mg_io_cmd_read)) != ERROR_OK)
  338. return ret;
  339. address = mflash_bank->base + MG_BUFFER_OFFSET;
  340. struct duration bench;
  341. duration_start(&bench);
  342. for (i = 0; i < sect_cnt; i++) {
  343. ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL);
  344. if (ret != ERROR_OK)
  345. return ret;
  346. ret = target_read_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
  347. if (ret != ERROR_OK)
  348. return ret;
  349. buff_ptr += MG_MFLASH_SECTOR_SIZE;
  350. ret = target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_read);
  351. if (ret != ERROR_OK)
  352. return ret;
  353. LOG_DEBUG("mflash: %" PRIu32 " (0x%8.8" PRIx32 ") sector read", sect_num + i, (sect_num + i) * MG_MFLASH_SECTOR_SIZE);
  354. ret = duration_measure(&bench);
  355. if ((ERROR_OK == ret) && (duration_elapsed(&bench) > 3)) {
  356. LOG_INFO("mflash: read %" PRIu32 "'th sectors", sect_num + i);
  357. duration_start(&bench);
  358. }
  359. }
  360. return mg_dsk_wait(mg_io_wait_rdy, MG_OEM_DISK_WAIT_TIME_NORMAL);
  361. }
  362. static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt)
  363. {
  364. uint32_t quotient, residue, i;
  365. uint8_t *buff_ptr = buff;
  366. int ret = ERROR_OK;
  367. quotient = sect_cnt >> 8;
  368. residue = sect_cnt % 256;
  369. for (i = 0; i < quotient; i++) {
  370. LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p",
  371. sect_num, buff_ptr);
  372. ret = mg_mflash_do_read_sects(buff_ptr, sect_num, 256);
  373. if (ret != ERROR_OK)
  374. return ret;
  375. sect_num += 256;
  376. buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
  377. }
  378. if (residue) {
  379. LOG_DEBUG("mflash: sect num : %" PRIx32 " buff : %p",
  380. sect_num, buff_ptr);
  381. return mg_mflash_do_read_sects(buff_ptr, sect_num, residue);
  382. }
  383. return ret;
  384. }
  385. static int mg_mflash_do_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt,
  386. mg_io_type_cmd cmd)
  387. {
  388. uint32_t i, address;
  389. int ret;
  390. struct target *target = mflash_bank->target;
  391. uint8_t *buff_ptr = buff;
  392. if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, cmd)) != ERROR_OK)
  393. return ret;
  394. address = mflash_bank->base + MG_BUFFER_OFFSET;
  395. struct duration bench;
  396. duration_start(&bench);
  397. for (i = 0; i < sect_cnt; i++) {
  398. ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL);
  399. if (ret != ERROR_OK)
  400. return ret;
  401. ret = target_write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
  402. if (ret != ERROR_OK)
  403. return ret;
  404. buff_ptr += MG_MFLASH_SECTOR_SIZE;
  405. ret = target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_write);
  406. if (ret != ERROR_OK)
  407. return ret;
  408. LOG_DEBUG("mflash: %" PRIu32 " (0x%8.8" PRIx32 ") sector write", sect_num + i, (sect_num + i) * MG_MFLASH_SECTOR_SIZE);
  409. ret = duration_measure(&bench);
  410. if ((ERROR_OK == ret) && (duration_elapsed(&bench) > 3)) {
  411. LOG_INFO("mflash: wrote %" PRIu32 "'th sectors", sect_num + i);
  412. duration_start(&bench);
  413. }
  414. }
  415. if (cmd == mg_io_cmd_write)
  416. ret = mg_dsk_wait(mg_io_wait_rdy, MG_OEM_DISK_WAIT_TIME_NORMAL);
  417. else
  418. ret = mg_dsk_wait(mg_io_wait_rdy, MG_OEM_DISK_WAIT_TIME_LONG);
  419. return ret;
  420. }
  421. static int mg_mflash_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt)
  422. {
  423. uint32_t quotient, residue, i;
  424. uint8_t *buff_ptr = buff;
  425. int ret = ERROR_OK;
  426. quotient = sect_cnt >> 8;
  427. residue = sect_cnt % 256;
  428. for (i = 0; i < quotient; i++) {
  429. LOG_DEBUG("mflash: sect num : %" PRIu32 "buff : %p", sect_num,
  430. buff_ptr);
  431. ret = mg_mflash_do_write_sects(buff_ptr, sect_num, 256, mg_io_cmd_write);
  432. if (ret != ERROR_OK)
  433. return ret;
  434. sect_num += 256;
  435. buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
  436. }
  437. if (residue) {
  438. LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p", sect_num,
  439. buff_ptr);
  440. return mg_mflash_do_write_sects(buff_ptr, sect_num, residue, mg_io_cmd_write);
  441. }
  442. return ret;
  443. }
  444. static int mg_mflash_read (uint32_t addr, uint8_t *buff, uint32_t len)
  445. {
  446. uint8_t *buff_ptr = buff;
  447. uint8_t sect_buff[MG_MFLASH_SECTOR_SIZE];
  448. uint32_t cur_addr, next_sec_addr, end_addr, cnt, sect_num;
  449. int ret = ERROR_OK;
  450. cnt = 0;
  451. cur_addr = addr;
  452. end_addr = addr + len;
  453. if (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK) {
  454. next_sec_addr = (cur_addr + MG_MFLASH_SECTOR_SIZE) & ~MG_MFLASH_SECTOR_SIZE_MASK;
  455. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  456. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  457. if (ret != ERROR_OK)
  458. return ret;
  459. if (end_addr < next_sec_addr) {
  460. memcpy(buff_ptr, sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), end_addr - cur_addr);
  461. LOG_DEBUG("mflash: copies %" PRIu32 " byte from sector offset 0x%8.8" PRIx32 "", end_addr - cur_addr, cur_addr);
  462. cur_addr = end_addr;
  463. } else {
  464. memcpy(buff_ptr, sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), next_sec_addr - cur_addr);
  465. LOG_DEBUG("mflash: copies %" PRIu32 " byte from sector offset 0x%8.8" PRIx32 "", next_sec_addr - cur_addr, cur_addr);
  466. buff_ptr += (next_sec_addr - cur_addr);
  467. cur_addr = next_sec_addr;
  468. }
  469. }
  470. if (cur_addr < end_addr) {
  471. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  472. next_sec_addr = cur_addr + MG_MFLASH_SECTOR_SIZE;
  473. while (next_sec_addr <= end_addr) {
  474. cnt++;
  475. next_sec_addr += MG_MFLASH_SECTOR_SIZE;
  476. }
  477. if (cnt)
  478. if ((ret = mg_mflash_read_sects(buff_ptr, sect_num, cnt)) != ERROR_OK)
  479. return ret;
  480. buff_ptr += cnt * MG_MFLASH_SECTOR_SIZE;
  481. cur_addr += cnt * MG_MFLASH_SECTOR_SIZE;
  482. if (cur_addr < end_addr) {
  483. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  484. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  485. if (ret != ERROR_OK)
  486. return ret;
  487. memcpy(buff_ptr, sect_buff, end_addr - cur_addr);
  488. LOG_DEBUG("mflash: copies %u byte", (unsigned)(end_addr - cur_addr));
  489. }
  490. }
  491. return ret;
  492. }
  493. static int mg_mflash_write(uint32_t addr, uint8_t *buff, uint32_t len)
  494. {
  495. uint8_t *buff_ptr = buff;
  496. uint8_t sect_buff[MG_MFLASH_SECTOR_SIZE];
  497. uint32_t cur_addr, next_sec_addr, end_addr, cnt, sect_num;
  498. int ret = ERROR_OK;
  499. cnt = 0;
  500. cur_addr = addr;
  501. end_addr = addr + len;
  502. if (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK) {
  503. next_sec_addr = (cur_addr + MG_MFLASH_SECTOR_SIZE) & ~MG_MFLASH_SECTOR_SIZE_MASK;
  504. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  505. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  506. if (ret != ERROR_OK)
  507. return ret;
  508. if (end_addr < next_sec_addr) {
  509. memcpy(sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), buff_ptr, end_addr - cur_addr);
  510. LOG_DEBUG("mflash: copies %" PRIu32 " byte to sector offset 0x%8.8" PRIx32 "", end_addr - cur_addr, cur_addr);
  511. cur_addr = end_addr;
  512. } else {
  513. memcpy(sect_buff + (cur_addr & MG_MFLASH_SECTOR_SIZE_MASK), buff_ptr, next_sec_addr - cur_addr);
  514. LOG_DEBUG("mflash: copies %" PRIu32 " byte to sector offset 0x%8.8" PRIx32 "", next_sec_addr - cur_addr, cur_addr);
  515. buff_ptr += (next_sec_addr - cur_addr);
  516. cur_addr = next_sec_addr;
  517. }
  518. ret = mg_mflash_write_sects(sect_buff, sect_num, 1);
  519. if (ret != ERROR_OK)
  520. return ret;
  521. }
  522. if (cur_addr < end_addr) {
  523. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  524. next_sec_addr = cur_addr + MG_MFLASH_SECTOR_SIZE;
  525. while (next_sec_addr <= end_addr) {
  526. cnt++;
  527. next_sec_addr += MG_MFLASH_SECTOR_SIZE;
  528. }
  529. if (cnt)
  530. if ((ret = mg_mflash_write_sects(buff_ptr, sect_num, cnt)) != ERROR_OK)
  531. return ret;
  532. buff_ptr += cnt * MG_MFLASH_SECTOR_SIZE;
  533. cur_addr += cnt * MG_MFLASH_SECTOR_SIZE;
  534. if (cur_addr < end_addr) {
  535. sect_num = cur_addr >> MG_MFLASH_SECTOR_SIZE_SHIFT;
  536. ret = mg_mflash_read_sects(sect_buff, sect_num, 1);
  537. if (ret != ERROR_OK)
  538. return ret;
  539. memcpy(sect_buff, buff_ptr, end_addr - cur_addr);
  540. LOG_DEBUG("mflash: copies %" PRIu32 " byte", end_addr - cur_addr);
  541. ret = mg_mflash_write_sects(sect_buff, sect_num, 1);
  542. }
  543. }
  544. return ret;
  545. }
  546. COMMAND_HANDLER(mg_write_cmd)
  547. {
  548. uint32_t address, cnt, res, i;
  549. uint8_t *buffer;
  550. struct fileio fileio;
  551. int ret;
  552. if (CMD_ARGC != 3) {
  553. return ERROR_COMMAND_SYNTAX_ERROR;
  554. }
  555. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
  556. ret = fileio_open(&fileio, CMD_ARGV[1], FILEIO_READ, FILEIO_BINARY);
  557. if (ret != ERROR_OK)
  558. return ret;
  559. int filesize;
  560. buffer = malloc(MG_FILEIO_CHUNK);
  561. if (!buffer) {
  562. fileio_close(&fileio);
  563. return ERROR_FAIL;
  564. }
  565. int retval = fileio_size(&fileio, &filesize);
  566. if (retval != ERROR_OK) {
  567. fileio_close(&fileio);
  568. return retval;
  569. }
  570. cnt = filesize / MG_FILEIO_CHUNK;
  571. res = filesize % MG_FILEIO_CHUNK;
  572. struct duration bench;
  573. duration_start(&bench);
  574. size_t buf_cnt;
  575. for (i = 0; i < cnt; i++) {
  576. if ((ret = fileio_read(&fileio, MG_FILEIO_CHUNK, buffer, &buf_cnt)) !=
  577. ERROR_OK)
  578. goto mg_write_cmd_err;
  579. if ((ret = mg_mflash_write(address, buffer, MG_FILEIO_CHUNK)) != ERROR_OK)
  580. goto mg_write_cmd_err;
  581. address += MG_FILEIO_CHUNK;
  582. }
  583. if (res) {
  584. if ((ret = fileio_read(&fileio, res, buffer, &buf_cnt)) != ERROR_OK)
  585. goto mg_write_cmd_err;
  586. if ((ret = mg_mflash_write(address, buffer, res)) != ERROR_OK)
  587. goto mg_write_cmd_err;
  588. }
  589. if (duration_measure(&bench) == ERROR_OK)
  590. {
  591. command_print(CMD_CTX, "wrote %ld bytes from file %s "
  592. "in %fs (%0.3f kB/s)", (long)filesize, CMD_ARGV[1],
  593. duration_elapsed(&bench), duration_kbps(&bench, filesize));
  594. }
  595. free(buffer);
  596. fileio_close(&fileio);
  597. return ERROR_OK;
  598. mg_write_cmd_err:
  599. free(buffer);
  600. fileio_close(&fileio);
  601. return ret;
  602. }
  603. COMMAND_HANDLER(mg_dump_cmd)
  604. {
  605. uint32_t address, size, cnt, res, i;
  606. uint8_t *buffer;
  607. struct fileio fileio;
  608. int ret;
  609. if (CMD_ARGC != 4) {
  610. return ERROR_COMMAND_SYNTAX_ERROR;
  611. }
  612. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
  613. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], size);
  614. ret = fileio_open(&fileio, CMD_ARGV[1], FILEIO_WRITE, FILEIO_BINARY);
  615. if (ret != ERROR_OK)
  616. return ret;
  617. buffer = malloc(MG_FILEIO_CHUNK);
  618. if (!buffer) {
  619. fileio_close(&fileio);
  620. return ERROR_FAIL;
  621. }
  622. cnt = size / MG_FILEIO_CHUNK;
  623. res = size % MG_FILEIO_CHUNK;
  624. struct duration bench;
  625. duration_start(&bench);
  626. size_t size_written;
  627. for (i = 0; i < cnt; i++) {
  628. if ((ret = mg_mflash_read(address, buffer, MG_FILEIO_CHUNK)) != ERROR_OK)
  629. goto mg_dump_cmd_err;
  630. if ((ret = fileio_write(&fileio, MG_FILEIO_CHUNK, buffer, &size_written))
  631. != ERROR_OK)
  632. goto mg_dump_cmd_err;
  633. address += MG_FILEIO_CHUNK;
  634. }
  635. if (res) {
  636. if ((ret = mg_mflash_read(address, buffer, res)) != ERROR_OK)
  637. goto mg_dump_cmd_err;
  638. if ((ret = fileio_write(&fileio, res, buffer, &size_written)) != ERROR_OK)
  639. goto mg_dump_cmd_err;
  640. }
  641. if (duration_measure(&bench) == ERROR_OK)
  642. {
  643. command_print(CMD_CTX, "dump image (address 0x%8.8" PRIx32 " "
  644. "size %" PRIu32 ") to file %s in %fs (%0.3f kB/s)",
  645. address, size, CMD_ARGV[1],
  646. duration_elapsed(&bench), duration_kbps(&bench, size));
  647. }
  648. free(buffer);
  649. fileio_close(&fileio);
  650. return ERROR_OK;
  651. mg_dump_cmd_err:
  652. free(buffer);
  653. fileio_close(&fileio);
  654. return ret;
  655. }
  656. static int mg_set_feature(mg_feature_id feature, mg_feature_val config)
  657. {
  658. struct target *target = mflash_bank->target;
  659. uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
  660. int ret;
  661. if ((ret = mg_dsk_wait(mg_io_wait_rdy_noerr, MG_OEM_DISK_WAIT_TIME_NORMAL))
  662. != ERROR_OK)
  663. return ret;
  664. ret = target_write_u8(target, mg_task_reg + MG_REG_FEATURE, feature);
  665. ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_CNT, config);
  666. ret |= target_write_u8(target, mg_task_reg + MG_REG_COMMAND,
  667. mg_io_cmd_set_feature);
  668. return ret;
  669. }
  670. static int mg_is_valid_pll(double XIN, int N, double CLK_OUT, int NO)
  671. {
  672. double v1 = XIN / N;
  673. double v2 = CLK_OUT * NO;
  674. if (v1 <1000000 || v1 > 15000000 || v2 < 100000000 || v2 > 500000000)
  675. return ERROR_MG_INVALID_PLL;
  676. return ERROR_OK;
  677. }
  678. static int mg_pll_get_M(unsigned short feedback_div)
  679. {
  680. int i, M;
  681. for (i = 1, M = 0; i < 512; i <<= 1, feedback_div >>= 1)
  682. M += (feedback_div & 1) * i;
  683. return M + 2;
  684. }
  685. static int mg_pll_get_N(unsigned char input_div)
  686. {
  687. int i, N;
  688. for (i = 1, N = 0; i < 32; i <<= 1, input_div >>= 1)
  689. N += (input_div & 1) * i;
  690. return N + 2;
  691. }
  692. static int mg_pll_get_NO(unsigned char output_div)
  693. {
  694. int i, NO;
  695. for (i = 0, NO = 1; i < 2; ++i, output_div >>= 1)
  696. if (output_div & 1)
  697. NO = NO << 1;
  698. return NO;
  699. }
  700. static double mg_do_calc_pll(double XIN, mg_pll_t * p_pll_val, int is_approximate)
  701. {
  702. unsigned short i;
  703. unsigned char j, k;
  704. int M, N, NO;
  705. double CLK_OUT;
  706. double DIV = 1;
  707. double ROUND = 0;
  708. if (is_approximate) {
  709. DIV = 1000000;
  710. ROUND = 500000;
  711. }
  712. for (i = 0; i < MG_PLL_MAX_FEEDBACKDIV_VAL ; ++i) {
  713. M = mg_pll_get_M(i);
  714. for (j = 0; j < MG_PLL_MAX_INPUTDIV_VAL ; ++j) {
  715. N = mg_pll_get_N(j);
  716. for (k = 0; k < MG_PLL_MAX_OUTPUTDIV_VAL ; ++k) {
  717. NO = mg_pll_get_NO(k);
  718. CLK_OUT = XIN * ((double)M / N) / NO;
  719. if ((int)((CLK_OUT + ROUND) / DIV)
  720. == (int)(MG_PLL_CLK_OUT / DIV)) {
  721. if (mg_is_valid_pll(XIN, N, CLK_OUT, NO) == ERROR_OK)
  722. {
  723. p_pll_val->lock_cyc = (int)(XIN * MG_PLL_STD_LOCKCYCLE / MG_PLL_STD_INPUTCLK);
  724. p_pll_val->feedback_div = i;
  725. p_pll_val->input_div = j;
  726. p_pll_val->output_div = k;
  727. return CLK_OUT;
  728. }
  729. }
  730. }
  731. }
  732. }
  733. return 0;
  734. }
  735. static double mg_calc_pll(double XIN, mg_pll_t *p_pll_val)
  736. {
  737. double CLK_OUT;
  738. CLK_OUT = mg_do_calc_pll(XIN, p_pll_val, 0);
  739. if (!CLK_OUT)
  740. return mg_do_calc_pll(XIN, p_pll_val, 1);
  741. else
  742. return CLK_OUT;
  743. }
  744. static int mg_verify_interface(void)
  745. {
  746. uint16_t buff[MG_MFLASH_SECTOR_SIZE >> 1];
  747. uint16_t i, j;
  748. uint32_t address = mflash_bank->base + MG_BUFFER_OFFSET;
  749. struct target *target = mflash_bank->target;
  750. int ret;
  751. for (j = 0; j < 10; j++) {
  752. for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++)
  753. buff[i] = i;
  754. ret = target_write_memory(target, address, 2,
  755. MG_MFLASH_SECTOR_SIZE / 2, (uint8_t *)buff);
  756. if (ret != ERROR_OK)
  757. return ret;
  758. memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE);
  759. ret = target_read_memory(target, address, 2,
  760. MG_MFLASH_SECTOR_SIZE / 2, (uint8_t *)buff);
  761. if (ret != ERROR_OK)
  762. return ret;
  763. for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++) {
  764. if (buff[i] != i) {
  765. LOG_ERROR("mflash: verify interface fail");
  766. return ERROR_MG_INTERFACE;
  767. }
  768. }
  769. }
  770. LOG_INFO("mflash: verify interface ok");
  771. return ret;
  772. }
  773. static const char g_strSEG_SerialNum[20] = {
  774. 'G','m','n','i','-','e','e','S','g','a','e','l',
  775. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  776. };
  777. static const char g_strSEG_FWRev[8] = {
  778. 'F','X','L','T','2','v','0','.'
  779. };
  780. static const char g_strSEG_ModelNum[40] = {
  781. 'F','X','A','L','H','S','2',0x20,'0','0','s','7',
  782. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  783. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  784. 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  785. };
  786. static void mg_gen_ataid(mg_io_type_drv_info *pSegIdDrvInfo)
  787. {
  788. /* b15 is ATA device(0) , b7 is Removable Media Device */
  789. pSegIdDrvInfo->general_configuration = 0x045A;
  790. /* 128MB : Cylinder=> 977 , Heads=> 8 , Sectors=> 32
  791. * 256MB : Cylinder=> 980 , Heads=> 16 , Sectors=> 32
  792. * 384MB : Cylinder=> 745 , Heads=> 16 , Sectors=> 63
  793. */
  794. pSegIdDrvInfo->number_of_cylinders = 0x02E9;
  795. pSegIdDrvInfo->reserved1 = 0x0;
  796. pSegIdDrvInfo->number_of_heads = 0x10;
  797. pSegIdDrvInfo->unformatted_bytes_per_track = 0x0;
  798. pSegIdDrvInfo->unformatted_bytes_per_sector = 0x0;
  799. pSegIdDrvInfo->sectors_per_track = 0x3F;
  800. pSegIdDrvInfo->vendor_unique1[0] = 0x000B;
  801. pSegIdDrvInfo->vendor_unique1[1] = 0x7570;
  802. pSegIdDrvInfo->vendor_unique1[2] = 0x8888;
  803. memcpy(pSegIdDrvInfo->serial_number, (void *)g_strSEG_SerialNum,20);
  804. /* 0x2 : dual buffer */
  805. pSegIdDrvInfo->buffer_type = 0x2;
  806. /* buffer size : 2KB */
  807. pSegIdDrvInfo->buffer_sector_size = 0x800;
  808. pSegIdDrvInfo->number_of_ecc_bytes = 0;
  809. memcpy(pSegIdDrvInfo->firmware_revision, (void *)g_strSEG_FWRev,8);
  810. memcpy(pSegIdDrvInfo->model_number, (void *)g_strSEG_ModelNum,40);
  811. pSegIdDrvInfo->maximum_block_transfer = 0x4;
  812. pSegIdDrvInfo->vendor_unique2 = 0x0;
  813. pSegIdDrvInfo->dword_io = 0x00;
  814. /* b11 : IORDY support(PIO Mode 4), b10 : Disable/Enbale IORDY
  815. * b9 : LBA support, b8 : DMA mode support
  816. */
  817. pSegIdDrvInfo->capabilities = 0x1 << 9;
  818. pSegIdDrvInfo->reserved2 = 0x4000;
  819. pSegIdDrvInfo->vendor_unique3 = 0x00;
  820. /* PIOMode-2 support */
  821. pSegIdDrvInfo->pio_cycle_timing_mode = 0x02;
  822. pSegIdDrvInfo->vendor_unique4 = 0x00;
  823. /* MultiWord-2 support */
  824. pSegIdDrvInfo->dma_cycle_timing_mode = 0x00;
  825. /* b1 : word64~70 is valid
  826. * b0 : word54~58 are valid and reflect the current numofcyls,heads,sectors
  827. * b2 : If device supports Ultra DMA , set to one to vaildate word88
  828. */
  829. pSegIdDrvInfo->translation_fields_valid = (0x1 << 1) | (0x1 << 0);
  830. pSegIdDrvInfo->number_of_current_cylinders = 0x02E9;
  831. pSegIdDrvInfo->number_of_current_heads = 0x10;
  832. pSegIdDrvInfo->current_sectors_per_track = 0x3F;
  833. pSegIdDrvInfo->current_sector_capacity_lo = 0x7570;
  834. pSegIdDrvInfo->current_sector_capacity_hi = 0x000B;
  835. pSegIdDrvInfo->multi_sector_count = 0x04;
  836. /* b8 : Multiple secotr setting valid , b[7:0] num of secotrs per block */
  837. pSegIdDrvInfo->multi_sector_setting_valid = 0x01;
  838. pSegIdDrvInfo->total_user_addressable_sectors_lo = 0x7570;
  839. pSegIdDrvInfo->total_user_addressable_sectors_hi = 0x000B;
  840. pSegIdDrvInfo->single_dma_modes_supported = 0x00;
  841. pSegIdDrvInfo->single_dma_transfer_active = 0x00;
  842. /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
  843. pSegIdDrvInfo->multi_dma_modes_supported = (0x1 << 0);
  844. /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
  845. pSegIdDrvInfo->multi_dma_transfer_active = (0x1 << 0);
  846. /* b0 : PIO Mode-3 support, b1 : PIO Mode-4 support */
  847. pSegIdDrvInfo->adv_pio_mode = 0x00;
  848. /* 480(0x1E0)nsec for Multi-word DMA mode0
  849. * 150(0x96) nsec for Multi-word DMA mode1
  850. * 120(0x78) nsec for Multi-word DMA mode2
  851. */
  852. pSegIdDrvInfo->min_dma_cyc = 0x1E0;
  853. pSegIdDrvInfo->recommend_dma_cyc = 0x1E0;
  854. pSegIdDrvInfo->min_pio_cyc_no_iordy = 0x1E0;
  855. pSegIdDrvInfo->min_pio_cyc_with_iordy = 0x1E0;
  856. memset((void *)pSegIdDrvInfo->reserved3, 0x00, 22);
  857. /* b7 : ATA/ATAPI-7 ,b6 : ATA/ATAPI-6 ,b5 : ATA/ATAPI-5,b4 : ATA/ATAPI-4 */
  858. pSegIdDrvInfo->major_ver_num = 0x7E;
  859. /* 0x1C : ATA/ATAPI-6 T13 1532D revision1 */
  860. pSegIdDrvInfo->minor_ver_num = 0x19;
  861. /* NOP/READ BUFFER/WRITE BUFFER/Power management feature set support */
  862. pSegIdDrvInfo->feature_cmd_set_suprt0 = 0x7068;
  863. /* Features/command set is valid/Advanced Pwr management/CFA feature set
  864. * not support
  865. */
  866. pSegIdDrvInfo->feature_cmd_set_suprt1 = 0x400C;
  867. pSegIdDrvInfo->feature_cmd_set_suprt2 = 0x4000;
  868. /* READ/WRITE BUFFER/PWR Management enable */
  869. pSegIdDrvInfo->feature_cmd_set_en0 = 0x7000;
  870. /* CFA feature is disabled / Advancde power management disable */
  871. pSegIdDrvInfo->feature_cmd_set_en1 = 0x0;
  872. pSegIdDrvInfo->feature_cmd_set_en2 = 0x4000;
  873. pSegIdDrvInfo->reserved4 = 0x0;
  874. /* 0x1 * 2minutes */
  875. pSegIdDrvInfo->req_time_for_security_er_done = 0x19;
  876. pSegIdDrvInfo->req_time_for_enhan_security_er_done = 0x19;
  877. /* Advanced power management level 1 */
  878. pSegIdDrvInfo->adv_pwr_mgm_lvl_val = 0x0;
  879. pSegIdDrvInfo->reserved5 = 0x0;
  880. memset((void *)pSegIdDrvInfo->reserved6, 0x00, 68);
  881. /* Security mode feature is disabled */
  882. pSegIdDrvInfo->security_stas = 0x0;
  883. memset((void *)pSegIdDrvInfo->vendor_uniq_bytes, 0x00, 62);
  884. /* CFA power mode 1 support in maximum 200mA */
  885. pSegIdDrvInfo->cfa_pwr_mode = 0x0100;
  886. memset((void *)pSegIdDrvInfo->reserved7, 0x00, 190);
  887. }
  888. static int mg_storage_config(void)
  889. {
  890. uint8_t buff[512];
  891. int ret;
  892. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  893. != ERROR_OK)
  894. return ret;
  895. mg_gen_ataid((mg_io_type_drv_info *)(void *)buff);
  896. if ((ret = mg_mflash_do_write_sects(buff, 0, 1, mg_vcmd_update_stgdrvinfo))
  897. != ERROR_OK)
  898. return ret;
  899. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  900. != ERROR_OK)
  901. return ret;
  902. LOG_INFO("mflash: storage config ok");
  903. return ret;
  904. }
  905. static int mg_boot_config(void)
  906. {
  907. uint8_t buff[512];
  908. int ret;
  909. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  910. != ERROR_OK)
  911. return ret;
  912. memset(buff, 0xff, 512);
  913. buff[0] = mg_op_mode_snd; /* operation mode */
  914. buff[1] = MG_UNLOCK_OTP_AREA;
  915. buff[2] = 4; /* boot size */
  916. *((uint32_t *)(void *)(buff + 4)) = 0; /* XIP size */
  917. if ((ret = mg_mflash_do_write_sects(buff, 0, 1, mg_vcmd_update_xipinfo))
  918. != ERROR_OK)
  919. return ret;
  920. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  921. != ERROR_OK)
  922. return ret;
  923. LOG_INFO("mflash: boot config ok");
  924. return ret;
  925. }
  926. static int mg_set_pll(mg_pll_t *pll)
  927. {
  928. uint8_t buff[512];
  929. int ret;
  930. memset(buff, 0xff, 512);
  931. /* PLL Lock cycle and Feedback 9bit Divider */
  932. memcpy(buff, &pll->lock_cyc, sizeof(uint32_t));
  933. memcpy(buff + 4, &pll->feedback_div, sizeof(uint16_t));
  934. buff[6] = pll->input_div; /* PLL Input 5bit Divider */
  935. buff[7] = pll->output_div; /* PLL Output Divider */
  936. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  937. != ERROR_OK)
  938. return ret;
  939. if ((ret = mg_mflash_do_write_sects(buff, 0, 1, mg_vcmd_wr_pll))
  940. != ERROR_OK)
  941. return ret;
  942. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  943. != ERROR_OK)
  944. return ret;
  945. LOG_INFO("mflash: set pll ok");
  946. return ret;
  947. }
  948. static int mg_erase_nand(void)
  949. {
  950. int ret;
  951. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
  952. != ERROR_OK)
  953. return ret;
  954. if ((ret = mg_mflash_do_write_sects(NULL, 0, 0, mg_vcmd_purge_nand))
  955. != ERROR_OK)
  956. return ret;
  957. if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_default))
  958. != ERROR_OK)
  959. return ret;
  960. LOG_INFO("mflash: erase nand ok");
  961. return ret;
  962. }
  963. COMMAND_HANDLER(mg_config_cmd)
  964. {
  965. double fin, fout;
  966. mg_pll_t pll;
  967. int ret;
  968. if ((ret = mg_verify_interface()) != ERROR_OK)
  969. return ret;
  970. if ((ret = mg_mflash_rst()) != ERROR_OK)
  971. return ret;
  972. switch (CMD_ARGC) {
  973. case 2:
  974. if (!strcmp(CMD_ARGV[1], "boot"))
  975. return mg_boot_config();
  976. else if (!strcmp(CMD_ARGV[1], "storage"))
  977. return mg_storage_config();
  978. else
  979. return ERROR_COMMAND_NOTFOUND;
  980. break;
  981. case 3:
  982. if (!strcmp(CMD_ARGV[1], "pll")) {
  983. unsigned long freq;
  984. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], freq);
  985. fin = freq;
  986. if (fin > MG_PLL_CLK_OUT) {
  987. LOG_ERROR("mflash: input freq. is too large");
  988. return ERROR_MG_INVALID_OSC;
  989. }
  990. fout = mg_calc_pll(fin, &pll);
  991. if (!fout) {
  992. LOG_ERROR("mflash: cannot generate valid pll");
  993. return ERROR_MG_INVALID_PLL;
  994. }
  995. LOG_INFO("mflash: Fout=%" PRIu32 " Hz, feedback=%u,"
  996. "indiv=%u, outdiv=%u, lock=%u",
  997. (uint32_t)fout, pll.feedback_div,
  998. pll.input_div, pll.output_div,
  999. pll.lock_cyc);
  1000. if ((ret = mg_erase_nand()) != ERROR_OK)
  1001. return ret;
  1002. return mg_set_pll(&pll);
  1003. } else
  1004. return ERROR_COMMAND_NOTFOUND;
  1005. break;
  1006. default:
  1007. return ERROR_COMMAND_SYNTAX_ERROR;
  1008. }
  1009. }
  1010. static const struct command_registration mflash_exec_command_handlers[] = {
  1011. {
  1012. .name = "probe",
  1013. .handler = mg_probe_cmd,
  1014. .mode = COMMAND_EXEC,
  1015. .help = "Detect bank configuration information",
  1016. },
  1017. {
  1018. .name = "write",
  1019. .handler = mg_write_cmd,
  1020. .mode = COMMAND_EXEC,
  1021. /* FIXME bank_num is unused */
  1022. .usage = "bank_num filename address",
  1023. .help = "Write binary file at the specified address.",
  1024. },
  1025. {
  1026. .name = "dump",
  1027. .handler = mg_dump_cmd,
  1028. .mode = COMMAND_EXEC,
  1029. /* FIXME bank_num is unused */
  1030. .usage = "bank_num filename address size",
  1031. .help = "Write specified number of bytes from a binary file "
  1032. "to the specified, address.",
  1033. },
  1034. {
  1035. .name = "config",
  1036. .handler = mg_config_cmd,
  1037. .mode = COMMAND_EXEC,
  1038. .help = "Configure MFLASH options.",
  1039. .usage = "('boot'|'storage'|'pll' frequency)",
  1040. },
  1041. COMMAND_REGISTRATION_DONE
  1042. };
  1043. static int mflash_init_drivers(struct command_context *cmd_ctx)
  1044. {
  1045. if (!mflash_bank)
  1046. return ERROR_OK;
  1047. return register_commands(cmd_ctx, NULL, mflash_exec_command_handlers);
  1048. }
  1049. COMMAND_HANDLER(handle_mflash_init_command)
  1050. {
  1051. if (CMD_ARGC != 0)
  1052. return ERROR_COMMAND_SYNTAX_ERROR;
  1053. static bool mflash_initialized = false;
  1054. if (mflash_initialized)
  1055. {
  1056. LOG_INFO("'mflash init' has already been called");
  1057. return ERROR_OK;
  1058. }
  1059. mflash_initialized = true;
  1060. LOG_DEBUG("Initializing mflash devices...");
  1061. return mflash_init_drivers(CMD_CTX);
  1062. }
  1063. COMMAND_HANDLER(mg_bank_cmd)
  1064. {
  1065. struct target *target;
  1066. int i;
  1067. if (CMD_ARGC < 4)
  1068. {
  1069. return ERROR_COMMAND_SYNTAX_ERROR;
  1070. }
  1071. if ((target = get_target(CMD_ARGV[3])) == NULL)
  1072. {
  1073. LOG_ERROR("target '%s' not defined", CMD_ARGV[3]);
  1074. return ERROR_FAIL;
  1075. }
  1076. mflash_bank = calloc(sizeof(struct mflash_bank), 1);
  1077. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], mflash_bank->base);
  1078. /// @todo Verify how this parsing should work, then document it.
  1079. char *str;
  1080. mflash_bank->rst_pin.num = strtoul(CMD_ARGV[2], &str, 0);
  1081. if (*str)
  1082. mflash_bank->rst_pin.port[0] = (uint16_t)
  1083. tolower((unsigned)str[0]);
  1084. mflash_bank->target = target;
  1085. for (i = 0; mflash_gpio[i] ; i++) {
  1086. if (! strcmp(mflash_gpio[i]->name, CMD_ARGV[0])) {
  1087. mflash_bank->gpio_drv = mflash_gpio[i];
  1088. }
  1089. }
  1090. if (! mflash_bank->gpio_drv) {
  1091. LOG_ERROR("%s is unsupported soc", CMD_ARGV[0]);
  1092. return ERROR_MG_UNSUPPORTED_SOC;
  1093. }
  1094. return ERROR_OK;
  1095. }
  1096. static const struct command_registration mflash_config_command_handlers[] = {
  1097. {
  1098. .name = "bank",
  1099. .handler = mg_bank_cmd,
  1100. .mode = COMMAND_CONFIG,
  1101. .help = "configure a mflash device bank",
  1102. .usage = "soc_type base_addr pin_id target",
  1103. },
  1104. {
  1105. .name = "init",
  1106. .mode = COMMAND_CONFIG,
  1107. .handler = handle_mflash_init_command,
  1108. .help = "initialize mflash devices",
  1109. },
  1110. COMMAND_REGISTRATION_DONE
  1111. };
  1112. static const struct command_registration mflash_command_handler[] = {
  1113. {
  1114. .name = "mflash",
  1115. .mode = COMMAND_ANY,
  1116. .help = "mflash command group",
  1117. .chain = mflash_config_command_handlers,
  1118. },
  1119. COMMAND_REGISTRATION_DONE
  1120. };
  1121. int mflash_register_commands(struct command_context *cmd_ctx)
  1122. {
  1123. return register_commands(cmd_ctx, NULL, mflash_command_handler);
  1124. }