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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 by Clement Burin des Roziers *
  9. * clement.burin-des-roziers@hikob.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program. If not, see <http://www.gnu.org/licenses/>. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "imp.h"
  28. #include <helper/binarybuffer.h>
  29. #include <target/algorithm.h>
  30. #include <target/armv7m.h>
  31. #include <target/cortex_m.h>
  32. /* stm32lx flash register locations */
  33. #define FLASH_ACR 0x00
  34. #define FLASH_PECR 0x04
  35. #define FLASH_PDKEYR 0x08
  36. #define FLASH_PEKEYR 0x0C
  37. #define FLASH_PRGKEYR 0x10
  38. #define FLASH_OPTKEYR 0x14
  39. #define FLASH_SR 0x18
  40. #define FLASH_OBR 0x1C
  41. #define FLASH_WRPR 0x20
  42. /* FLASH_ACR bites */
  43. #define FLASH_ACR__LATENCY (1<<0)
  44. #define FLASH_ACR__PRFTEN (1<<1)
  45. #define FLASH_ACR__ACC64 (1<<2)
  46. #define FLASH_ACR__SLEEP_PD (1<<3)
  47. #define FLASH_ACR__RUN_PD (1<<4)
  48. /* FLASH_PECR bits */
  49. #define FLASH_PECR__PELOCK (1<<0)
  50. #define FLASH_PECR__PRGLOCK (1<<1)
  51. #define FLASH_PECR__OPTLOCK (1<<2)
  52. #define FLASH_PECR__PROG (1<<3)
  53. #define FLASH_PECR__DATA (1<<4)
  54. #define FLASH_PECR__FTDW (1<<8)
  55. #define FLASH_PECR__ERASE (1<<9)
  56. #define FLASH_PECR__FPRG (1<<10)
  57. #define FLASH_PECR__EOPIE (1<<16)
  58. #define FLASH_PECR__ERRIE (1<<17)
  59. #define FLASH_PECR__OBL_LAUNCH (1<<18)
  60. /* FLASH_SR bits */
  61. #define FLASH_SR__BSY (1<<0)
  62. #define FLASH_SR__EOP (1<<1)
  63. #define FLASH_SR__ENDHV (1<<2)
  64. #define FLASH_SR__READY (1<<3)
  65. #define FLASH_SR__WRPERR (1<<8)
  66. #define FLASH_SR__PGAERR (1<<9)
  67. #define FLASH_SR__SIZERR (1<<10)
  68. #define FLASH_SR__OPTVERR (1<<11)
  69. /* Unlock keys */
  70. #define PEKEY1 0x89ABCDEF
  71. #define PEKEY2 0x02030405
  72. #define PRGKEY1 0x8C9DAEBF
  73. #define PRGKEY2 0x13141516
  74. #define OPTKEY1 0xFBEAD9C8
  75. #define OPTKEY2 0x24252627
  76. /* other registers */
  77. #define DBGMCU_IDCODE 0xE0042000
  78. #define DBGMCU_IDCODE_L0 0x40015800
  79. /* Constants */
  80. #define FLASH_SECTOR_SIZE 4096
  81. #define FLASH_BANK0_ADDRESS 0x08000000
  82. /* option bytes */
  83. #define OPTION_BYTES_ADDRESS 0x1FF80000
  84. #define OPTION_BYTE_0_PR1 0xFFFF0000
  85. #define OPTION_BYTE_0_PR0 0xFF5500AA
  86. static int stm32lx_unlock_program_memory(struct flash_bank *bank);
  87. static int stm32lx_lock_program_memory(struct flash_bank *bank);
  88. static int stm32lx_enable_write_half_page(struct flash_bank *bank);
  89. static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
  90. static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
  91. static int stm32lx_lock(struct flash_bank *bank);
  92. static int stm32lx_unlock(struct flash_bank *bank);
  93. static int stm32lx_mass_erase(struct flash_bank *bank);
  94. static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
  95. static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb);
  96. struct stm32lx_rev {
  97. uint16_t rev;
  98. const char *str;
  99. };
  100. struct stm32lx_part_info {
  101. uint16_t id;
  102. const char *device_str;
  103. const struct stm32lx_rev *revs;
  104. size_t num_revs;
  105. unsigned int page_size;
  106. unsigned int pages_per_sector;
  107. uint16_t max_flash_size_kb;
  108. uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
  109. bool has_dual_banks;
  110. uint32_t flash_base; /* Flash controller registers location */
  111. uint32_t fsize_base; /* Location of FSIZE register */
  112. };
  113. struct stm32lx_flash_bank {
  114. int probed;
  115. uint32_t idcode;
  116. uint32_t user_bank_size;
  117. uint32_t flash_base;
  118. struct stm32lx_part_info part_info;
  119. };
  120. static const struct stm32lx_rev stm32_416_revs[] = {
  121. { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
  122. };
  123. static const struct stm32lx_rev stm32_417_revs[] = {
  124. { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
  125. };
  126. static const struct stm32lx_rev stm32_425_revs[] = {
  127. { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
  128. };
  129. static const struct stm32lx_rev stm32_427_revs[] = {
  130. { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
  131. };
  132. static const struct stm32lx_rev stm32_429_revs[] = {
  133. { 0x1000, "A" }, { 0x1018, "Z" },
  134. };
  135. static const struct stm32lx_rev stm32_436_revs[] = {
  136. { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
  137. };
  138. static const struct stm32lx_rev stm32_437_revs[] = {
  139. { 0x1000, "A" },
  140. };
  141. static const struct stm32lx_rev stm32_447_revs[] = {
  142. { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
  143. };
  144. static const struct stm32lx_rev stm32_457_revs[] = {
  145. { 0x1000, "A" }, { 0x1008, "Z" },
  146. };
  147. static const struct stm32lx_part_info stm32lx_parts[] = {
  148. {
  149. .id = 0x416,
  150. .revs = stm32_416_revs,
  151. .num_revs = ARRAY_SIZE(stm32_416_revs),
  152. .device_str = "STM32L1xx (Cat.1 - Low/Medium Density)",
  153. .page_size = 256,
  154. .pages_per_sector = 16,
  155. .max_flash_size_kb = 128,
  156. .has_dual_banks = false,
  157. .flash_base = 0x40023C00,
  158. .fsize_base = 0x1FF8004C,
  159. },
  160. {
  161. .id = 0x417,
  162. .revs = stm32_417_revs,
  163. .num_revs = ARRAY_SIZE(stm32_417_revs),
  164. .device_str = "STM32L0xx (Cat. 3)",
  165. .page_size = 128,
  166. .pages_per_sector = 32,
  167. .max_flash_size_kb = 64,
  168. .has_dual_banks = false,
  169. .flash_base = 0x40022000,
  170. .fsize_base = 0x1FF8007C,
  171. },
  172. {
  173. .id = 0x425,
  174. .revs = stm32_425_revs,
  175. .num_revs = ARRAY_SIZE(stm32_425_revs),
  176. .device_str = "STM32L0xx (Cat. 2)",
  177. .page_size = 128,
  178. .pages_per_sector = 32,
  179. .max_flash_size_kb = 32,
  180. .has_dual_banks = false,
  181. .flash_base = 0x40022000,
  182. .fsize_base = 0x1FF8007C,
  183. },
  184. {
  185. .id = 0x427,
  186. .revs = stm32_427_revs,
  187. .num_revs = ARRAY_SIZE(stm32_427_revs),
  188. .device_str = "STM32L1xx (Cat.3 - Medium+ Density)",
  189. .page_size = 256,
  190. .pages_per_sector = 16,
  191. .max_flash_size_kb = 256,
  192. .has_dual_banks = false,
  193. .flash_base = 0x40023C00,
  194. .fsize_base = 0x1FF800CC,
  195. },
  196. {
  197. .id = 0x429,
  198. .revs = stm32_429_revs,
  199. .num_revs = ARRAY_SIZE(stm32_429_revs),
  200. .device_str = "STM32L1xx (Cat.2)",
  201. .page_size = 256,
  202. .pages_per_sector = 16,
  203. .max_flash_size_kb = 128,
  204. .has_dual_banks = false,
  205. .flash_base = 0x40023C00,
  206. .fsize_base = 0x1FF8004C,
  207. },
  208. {
  209. .id = 0x436,
  210. .revs = stm32_436_revs,
  211. .num_revs = ARRAY_SIZE(stm32_436_revs),
  212. .device_str = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
  213. .page_size = 256,
  214. .pages_per_sector = 16,
  215. .max_flash_size_kb = 384,
  216. .first_bank_size_kb = 192,
  217. .has_dual_banks = true,
  218. .flash_base = 0x40023C00,
  219. .fsize_base = 0x1FF800CC,
  220. },
  221. {
  222. .id = 0x437,
  223. .revs = stm32_437_revs,
  224. .num_revs = ARRAY_SIZE(stm32_437_revs),
  225. .device_str = "STM32L1xx (Cat.5/Cat.6)",
  226. .page_size = 256,
  227. .pages_per_sector = 16,
  228. .max_flash_size_kb = 512,
  229. .first_bank_size_kb = 0, /* determined in runtime */
  230. .has_dual_banks = true,
  231. .flash_base = 0x40023C00,
  232. .fsize_base = 0x1FF800CC,
  233. },
  234. {
  235. .id = 0x447,
  236. .revs = stm32_447_revs,
  237. .num_revs = ARRAY_SIZE(stm32_447_revs),
  238. .device_str = "STM32L0xx (Cat.5)",
  239. .page_size = 128,
  240. .pages_per_sector = 32,
  241. .max_flash_size_kb = 192,
  242. .first_bank_size_kb = 0, /* determined in runtime */
  243. .has_dual_banks = false, /* determined in runtime */
  244. .flash_base = 0x40022000,
  245. .fsize_base = 0x1FF8007C,
  246. },
  247. {
  248. .id = 0x457,
  249. .revs = stm32_457_revs,
  250. .num_revs = ARRAY_SIZE(stm32_457_revs),
  251. .device_str = "STM32L0xx (Cat.1)",
  252. .page_size = 128,
  253. .pages_per_sector = 32,
  254. .max_flash_size_kb = 16,
  255. .has_dual_banks = false,
  256. .flash_base = 0x40022000,
  257. .fsize_base = 0x1FF8007C,
  258. },
  259. };
  260. /* flash bank stm32lx <base> <size> 0 0 <target#>
  261. */
  262. FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
  263. {
  264. struct stm32lx_flash_bank *stm32lx_info;
  265. if (CMD_ARGC < 6)
  266. return ERROR_COMMAND_SYNTAX_ERROR;
  267. /* Create the bank structure */
  268. stm32lx_info = calloc(1, sizeof(*stm32lx_info));
  269. /* Check allocation */
  270. if (stm32lx_info == NULL) {
  271. LOG_ERROR("failed to allocate bank structure");
  272. return ERROR_FAIL;
  273. }
  274. bank->driver_priv = stm32lx_info;
  275. stm32lx_info->probed = 0;
  276. stm32lx_info->user_bank_size = bank->size;
  277. /* the stm32l erased value is 0x00 */
  278. bank->default_padded_value = bank->erased_value = 0x00;
  279. return ERROR_OK;
  280. }
  281. COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
  282. {
  283. int i;
  284. if (CMD_ARGC < 1)
  285. return ERROR_COMMAND_SYNTAX_ERROR;
  286. struct flash_bank *bank;
  287. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  288. if (ERROR_OK != retval)
  289. return retval;
  290. retval = stm32lx_mass_erase(bank);
  291. if (retval == ERROR_OK) {
  292. /* set all sectors as erased */
  293. for (i = 0; i < bank->num_sectors; i++)
  294. bank->sectors[i].is_erased = 1;
  295. command_print(CMD, "stm32lx mass erase complete");
  296. } else {
  297. command_print(CMD, "stm32lx mass erase failed");
  298. }
  299. return retval;
  300. }
  301. COMMAND_HANDLER(stm32lx_handle_lock_command)
  302. {
  303. if (CMD_ARGC < 1)
  304. return ERROR_COMMAND_SYNTAX_ERROR;
  305. struct flash_bank *bank;
  306. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  307. if (ERROR_OK != retval)
  308. return retval;
  309. retval = stm32lx_lock(bank);
  310. if (retval == ERROR_OK)
  311. command_print(CMD, "STM32Lx locked, takes effect after power cycle.");
  312. else
  313. command_print(CMD, "STM32Lx lock failed");
  314. return retval;
  315. }
  316. COMMAND_HANDLER(stm32lx_handle_unlock_command)
  317. {
  318. if (CMD_ARGC < 1)
  319. return ERROR_COMMAND_SYNTAX_ERROR;
  320. struct flash_bank *bank;
  321. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  322. if (ERROR_OK != retval)
  323. return retval;
  324. retval = stm32lx_unlock(bank);
  325. if (retval == ERROR_OK)
  326. command_print(CMD, "STM32Lx unlocked, takes effect after power cycle.");
  327. else
  328. command_print(CMD, "STM32Lx unlock failed");
  329. return retval;
  330. }
  331. static int stm32lx_protect_check(struct flash_bank *bank)
  332. {
  333. int retval;
  334. struct target *target = bank->target;
  335. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  336. uint32_t wrpr;
  337. /*
  338. * Read the WRPR word, and check each bit (corresponding to each
  339. * flash sector
  340. */
  341. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
  342. &wrpr);
  343. if (retval != ERROR_OK)
  344. return retval;
  345. for (int i = 0; i < bank->num_sectors; i++) {
  346. if (wrpr & (1 << i))
  347. bank->sectors[i].is_protected = 1;
  348. else
  349. bank->sectors[i].is_protected = 0;
  350. }
  351. return ERROR_OK;
  352. }
  353. static int stm32lx_erase(struct flash_bank *bank, int first, int last)
  354. {
  355. int retval;
  356. /*
  357. * It could be possible to do a mass erase if all sectors must be
  358. * erased, but it is not implemented yet.
  359. */
  360. if (bank->target->state != TARGET_HALTED) {
  361. LOG_ERROR("Target not halted");
  362. return ERROR_TARGET_NOT_HALTED;
  363. }
  364. /*
  365. * Loop over the selected sectors and erase them
  366. */
  367. for (int i = first; i <= last; i++) {
  368. retval = stm32lx_erase_sector(bank, i);
  369. if (retval != ERROR_OK)
  370. return retval;
  371. bank->sectors[i].is_erased = 1;
  372. }
  373. return ERROR_OK;
  374. }
  375. static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
  376. uint32_t offset, uint32_t count)
  377. {
  378. struct target *target = bank->target;
  379. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  380. uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
  381. uint32_t buffer_size = 16384;
  382. struct working_area *write_algorithm;
  383. struct working_area *source;
  384. uint32_t address = bank->base + offset;
  385. struct reg_param reg_params[3];
  386. struct armv7m_algorithm armv7m_info;
  387. int retval = ERROR_OK;
  388. static const uint8_t stm32lx_flash_write_code[] = {
  389. #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
  390. };
  391. /* Make sure we're performing a half-page aligned write. */
  392. if (count % hp_nb) {
  393. LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIi32 "B)", hp_nb, count);
  394. return ERROR_FAIL;
  395. }
  396. /* flash write code */
  397. if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
  398. &write_algorithm) != ERROR_OK) {
  399. LOG_DEBUG("no working area for block memory writes");
  400. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  401. }
  402. /* Write the flashing code */
  403. retval = target_write_buffer(target,
  404. write_algorithm->address,
  405. sizeof(stm32lx_flash_write_code),
  406. stm32lx_flash_write_code);
  407. if (retval != ERROR_OK) {
  408. target_free_working_area(target, write_algorithm);
  409. return retval;
  410. }
  411. /* Allocate half pages memory */
  412. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  413. if (buffer_size > 1024)
  414. buffer_size -= 1024;
  415. else
  416. buffer_size /= 2;
  417. if (buffer_size <= stm32lx_info->part_info.page_size) {
  418. /* we already allocated the writing code, but failed to get a
  419. * buffer, free the algorithm */
  420. target_free_working_area(target, write_algorithm);
  421. LOG_WARNING("no large enough working area available, can't do block memory writes");
  422. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  423. }
  424. }
  425. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  426. armv7m_info.core_mode = ARM_MODE_THREAD;
  427. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  428. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  429. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  430. /* Enable half-page write */
  431. retval = stm32lx_enable_write_half_page(bank);
  432. if (retval != ERROR_OK) {
  433. target_free_working_area(target, source);
  434. target_free_working_area(target, write_algorithm);
  435. destroy_reg_param(&reg_params[0]);
  436. destroy_reg_param(&reg_params[1]);
  437. destroy_reg_param(&reg_params[2]);
  438. return retval;
  439. }
  440. struct armv7m_common *armv7m = target_to_armv7m(target);
  441. if (armv7m == NULL) {
  442. /* something is very wrong if armv7m is NULL */
  443. LOG_ERROR("unable to get armv7m target");
  444. return retval;
  445. }
  446. /* save any DEMCR flags and configure target to catch any Hard Faults */
  447. uint32_t demcr_save = armv7m->demcr;
  448. armv7m->demcr = VC_HARDERR;
  449. /* Loop while there are bytes to write */
  450. while (count > 0) {
  451. uint32_t this_count;
  452. this_count = (count > buffer_size) ? buffer_size : count;
  453. /* Write the next half pages */
  454. retval = target_write_buffer(target, source->address, this_count, buffer);
  455. if (retval != ERROR_OK)
  456. break;
  457. /* 4: Store useful information in the registers */
  458. /* the destination address of the copy (R0) */
  459. buf_set_u32(reg_params[0].value, 0, 32, address);
  460. /* The source address of the copy (R1) */
  461. buf_set_u32(reg_params[1].value, 0, 32, source->address);
  462. /* The length of the copy (R2) */
  463. buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
  464. /* 5: Execute the bunch of code */
  465. retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
  466. / sizeof(*reg_params), reg_params,
  467. write_algorithm->address, 0, 10000, &armv7m_info);
  468. if (retval != ERROR_OK)
  469. break;
  470. /* check for Hard Fault */
  471. if (armv7m->exception_number == 3)
  472. break;
  473. /* 6: Wait while busy */
  474. retval = stm32lx_wait_until_bsy_clear(bank);
  475. if (retval != ERROR_OK)
  476. break;
  477. buffer += this_count;
  478. address += this_count;
  479. count -= this_count;
  480. }
  481. /* restore previous flags */
  482. armv7m->demcr = demcr_save;
  483. if (armv7m->exception_number == 3) {
  484. /* the stm32l15x devices seem to have an issue when blank.
  485. * if a ram loader is executed on a blank device it will
  486. * Hard Fault, this issue does not happen for a already programmed device.
  487. * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
  488. * The workaround of handling the Hard Fault exception does work, but makes the
  489. * loader more complicated, as a compromise we manually write the pages, programming time
  490. * is reduced by 50% using this slower method.
  491. */
  492. LOG_WARNING("Couldn't use loader, falling back to page memory writes");
  493. while (count > 0) {
  494. uint32_t this_count;
  495. this_count = (count > hp_nb) ? hp_nb : count;
  496. /* Write the next half pages */
  497. retval = target_write_buffer(target, address, this_count, buffer);
  498. if (retval != ERROR_OK)
  499. break;
  500. /* Wait while busy */
  501. retval = stm32lx_wait_until_bsy_clear(bank);
  502. if (retval != ERROR_OK)
  503. break;
  504. buffer += this_count;
  505. address += this_count;
  506. count -= this_count;
  507. }
  508. }
  509. if (retval == ERROR_OK)
  510. retval = stm32lx_lock_program_memory(bank);
  511. target_free_working_area(target, source);
  512. target_free_working_area(target, write_algorithm);
  513. destroy_reg_param(&reg_params[0]);
  514. destroy_reg_param(&reg_params[1]);
  515. destroy_reg_param(&reg_params[2]);
  516. return retval;
  517. }
  518. static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
  519. uint32_t offset, uint32_t count)
  520. {
  521. struct target *target = bank->target;
  522. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  523. uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
  524. uint32_t halfpages_number;
  525. uint32_t bytes_remaining = 0;
  526. uint32_t address = bank->base + offset;
  527. uint32_t bytes_written = 0;
  528. int retval, retval2;
  529. if (bank->target->state != TARGET_HALTED) {
  530. LOG_ERROR("Target not halted");
  531. return ERROR_TARGET_NOT_HALTED;
  532. }
  533. if (offset & 0x3) {
  534. LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
  535. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  536. }
  537. retval = stm32lx_unlock_program_memory(bank);
  538. if (retval != ERROR_OK)
  539. return retval;
  540. /* first we need to write any unaligned head bytes upto
  541. * the next 128 byte page */
  542. if (offset % hp_nb)
  543. bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
  544. while (bytes_remaining > 0) {
  545. uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
  546. /* copy remaining bytes into the write buffer */
  547. uint32_t bytes_to_write = MIN(4, bytes_remaining);
  548. memcpy(value, buffer + bytes_written, bytes_to_write);
  549. retval = target_write_buffer(target, address, 4, value);
  550. if (retval != ERROR_OK)
  551. goto reset_pg_and_lock;
  552. bytes_written += bytes_to_write;
  553. bytes_remaining -= bytes_to_write;
  554. address += 4;
  555. retval = stm32lx_wait_until_bsy_clear(bank);
  556. if (retval != ERROR_OK)
  557. goto reset_pg_and_lock;
  558. }
  559. offset += bytes_written;
  560. count -= bytes_written;
  561. /* this should always pass this check here */
  562. assert((offset % hp_nb) == 0);
  563. /* calculate half pages */
  564. halfpages_number = count / hp_nb;
  565. if (halfpages_number) {
  566. retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
  567. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  568. /* attempt slow memory writes */
  569. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  570. halfpages_number = 0;
  571. } else {
  572. if (retval != ERROR_OK)
  573. return ERROR_FAIL;
  574. }
  575. }
  576. /* write any remaining bytes */
  577. uint32_t page_bytes_written = hp_nb * halfpages_number;
  578. bytes_written += page_bytes_written;
  579. address += page_bytes_written;
  580. bytes_remaining = count - page_bytes_written;
  581. retval = stm32lx_unlock_program_memory(bank);
  582. if (retval != ERROR_OK)
  583. return retval;
  584. while (bytes_remaining > 0) {
  585. uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
  586. /* copy remaining bytes into the write buffer */
  587. uint32_t bytes_to_write = MIN(4, bytes_remaining);
  588. memcpy(value, buffer + bytes_written, bytes_to_write);
  589. retval = target_write_buffer(target, address, 4, value);
  590. if (retval != ERROR_OK)
  591. goto reset_pg_and_lock;
  592. bytes_written += bytes_to_write;
  593. bytes_remaining -= bytes_to_write;
  594. address += 4;
  595. retval = stm32lx_wait_until_bsy_clear(bank);
  596. if (retval != ERROR_OK)
  597. goto reset_pg_and_lock;
  598. }
  599. reset_pg_and_lock:
  600. retval2 = stm32lx_lock_program_memory(bank);
  601. if (retval == ERROR_OK)
  602. retval = retval2;
  603. return retval;
  604. }
  605. static int stm32lx_read_id_code(struct target *target, uint32_t *id)
  606. {
  607. struct armv7m_common *armv7m = target_to_armv7m(target);
  608. int retval;
  609. if (armv7m->arm.is_armv6m == true)
  610. retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
  611. else
  612. /* read stm32 device id register */
  613. retval = target_read_u32(target, DBGMCU_IDCODE, id);
  614. return retval;
  615. }
  616. static int stm32lx_probe(struct flash_bank *bank)
  617. {
  618. struct target *target = bank->target;
  619. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  620. int i;
  621. uint16_t flash_size_in_kb;
  622. uint32_t device_id;
  623. uint32_t base_address = FLASH_BANK0_ADDRESS;
  624. uint32_t second_bank_base;
  625. unsigned int n;
  626. stm32lx_info->probed = 0;
  627. int retval = stm32lx_read_id_code(bank->target, &device_id);
  628. if (retval != ERROR_OK)
  629. return retval;
  630. stm32lx_info->idcode = device_id;
  631. LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
  632. for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
  633. if ((device_id & 0xfff) == stm32lx_parts[n].id) {
  634. stm32lx_info->part_info = stm32lx_parts[n];
  635. break;
  636. }
  637. }
  638. if (n == ARRAY_SIZE(stm32lx_parts)) {
  639. LOG_ERROR("Cannot identify target as an STM32 L0 or L1 family device.");
  640. return ERROR_FAIL;
  641. } else {
  642. LOG_INFO("Device: %s", stm32lx_info->part_info.device_str);
  643. }
  644. stm32lx_info->flash_base = stm32lx_info->part_info.flash_base;
  645. /* Get the flash size from target. */
  646. retval = target_read_u16(target, stm32lx_info->part_info.fsize_base,
  647. &flash_size_in_kb);
  648. /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
  649. * or 256K, respectively. Please see RM0038 r8 or newer and refer to
  650. * section 30.1.1. */
  651. if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
  652. if (flash_size_in_kb == 0)
  653. flash_size_in_kb = 384;
  654. else if (flash_size_in_kb == 1)
  655. flash_size_in_kb = 256;
  656. }
  657. /* 0x429 devices only use the lowest 8 bits of the flash size register */
  658. if (retval == ERROR_OK && (device_id & 0xfff) == 0x429) {
  659. flash_size_in_kb &= 0xff;
  660. }
  661. /* Failed reading flash size or flash size invalid (early silicon),
  662. * default to max target family */
  663. if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
  664. LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
  665. stm32lx_info->part_info.max_flash_size_kb);
  666. flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
  667. } else if (flash_size_in_kb > stm32lx_info->part_info.max_flash_size_kb) {
  668. LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
  669. flash_size_in_kb, stm32lx_info->part_info.max_flash_size_kb,
  670. stm32lx_info->part_info.max_flash_size_kb);
  671. flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
  672. }
  673. /* Overwrite default dual-bank configuration */
  674. retval = stm32lx_update_part_info(bank, flash_size_in_kb);
  675. if (retval != ERROR_OK)
  676. return ERROR_FAIL;
  677. if (stm32lx_info->part_info.has_dual_banks) {
  678. /* Use the configured base address to determine if this is the first or second flash bank.
  679. * Verify that the base address is reasonably correct and determine the flash bank size
  680. */
  681. second_bank_base = base_address +
  682. stm32lx_info->part_info.first_bank_size_kb * 1024;
  683. if (bank->base == second_bank_base || !bank->base) {
  684. /* This is the second bank */
  685. base_address = second_bank_base;
  686. flash_size_in_kb = flash_size_in_kb -
  687. stm32lx_info->part_info.first_bank_size_kb;
  688. } else if (bank->base == base_address) {
  689. /* This is the first bank */
  690. flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
  691. } else {
  692. LOG_WARNING("STM32L flash bank base address config is incorrect. "
  693. TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
  694. " or 0x%" PRIx32,
  695. bank->base, base_address, second_bank_base);
  696. return ERROR_FAIL;
  697. }
  698. LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
  699. bank->bank_number, flash_size_in_kb, base_address);
  700. } else {
  701. LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
  702. }
  703. /* if the user sets the size manually then ignore the probed value
  704. * this allows us to work around devices that have a invalid flash size register value */
  705. if (stm32lx_info->user_bank_size) {
  706. flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
  707. LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
  708. }
  709. /* calculate numbers of sectors (4kB per sector) */
  710. int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
  711. if (bank->sectors) {
  712. free(bank->sectors);
  713. bank->sectors = NULL;
  714. }
  715. bank->size = flash_size_in_kb * 1024;
  716. bank->base = base_address;
  717. bank->num_sectors = num_sectors;
  718. bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
  719. if (bank->sectors == NULL) {
  720. LOG_ERROR("failed to allocate bank sectors");
  721. return ERROR_FAIL;
  722. }
  723. for (i = 0; i < num_sectors; i++) {
  724. bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
  725. bank->sectors[i].size = FLASH_SECTOR_SIZE;
  726. bank->sectors[i].is_erased = -1;
  727. bank->sectors[i].is_protected = -1;
  728. }
  729. stm32lx_info->probed = 1;
  730. return ERROR_OK;
  731. }
  732. static int stm32lx_auto_probe(struct flash_bank *bank)
  733. {
  734. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  735. if (stm32lx_info->probed)
  736. return ERROR_OK;
  737. return stm32lx_probe(bank);
  738. }
  739. /* This method must return a string displaying information about the bank */
  740. static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
  741. {
  742. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  743. const struct stm32lx_part_info *info = &stm32lx_info->part_info;
  744. uint16_t rev_id = stm32lx_info->idcode >> 16;
  745. const char *rev_str = NULL;
  746. if (!stm32lx_info->probed) {
  747. int retval = stm32lx_probe(bank);
  748. if (retval != ERROR_OK) {
  749. snprintf(buf, buf_size,
  750. "Unable to find bank information.");
  751. return retval;
  752. }
  753. }
  754. for (unsigned int i = 0; i < info->num_revs; i++)
  755. if (rev_id == info->revs[i].rev)
  756. rev_str = info->revs[i].str;
  757. if (rev_str != NULL) {
  758. snprintf(buf, buf_size,
  759. "%s - Rev: %s",
  760. info->device_str, rev_str);
  761. } else {
  762. snprintf(buf, buf_size,
  763. "%s - Rev: unknown (0x%04x)",
  764. info->device_str, rev_id);
  765. }
  766. return ERROR_OK;
  767. }
  768. static const struct command_registration stm32lx_exec_command_handlers[] = {
  769. {
  770. .name = "mass_erase",
  771. .handler = stm32lx_handle_mass_erase_command,
  772. .mode = COMMAND_EXEC,
  773. .usage = "bank_id",
  774. .help = "Erase entire flash device. including available EEPROM",
  775. },
  776. {
  777. .name = "lock",
  778. .handler = stm32lx_handle_lock_command,
  779. .mode = COMMAND_EXEC,
  780. .usage = "bank_id",
  781. .help = "Increase the readout protection to Level 1.",
  782. },
  783. {
  784. .name = "unlock",
  785. .handler = stm32lx_handle_unlock_command,
  786. .mode = COMMAND_EXEC,
  787. .usage = "bank_id",
  788. .help = "Lower the readout protection from Level 1 to 0.",
  789. },
  790. COMMAND_REGISTRATION_DONE
  791. };
  792. static const struct command_registration stm32lx_command_handlers[] = {
  793. {
  794. .name = "stm32lx",
  795. .mode = COMMAND_ANY,
  796. .help = "stm32lx flash command group",
  797. .usage = "",
  798. .chain = stm32lx_exec_command_handlers,
  799. },
  800. COMMAND_REGISTRATION_DONE
  801. };
  802. const struct flash_driver stm32lx_flash = {
  803. .name = "stm32lx",
  804. .commands = stm32lx_command_handlers,
  805. .flash_bank_command = stm32lx_flash_bank_command,
  806. .erase = stm32lx_erase,
  807. .write = stm32lx_write,
  808. .read = default_flash_read,
  809. .probe = stm32lx_probe,
  810. .auto_probe = stm32lx_auto_probe,
  811. .erase_check = default_flash_blank_check,
  812. .protect_check = stm32lx_protect_check,
  813. .info = stm32lx_get_info,
  814. .free_driver_priv = default_flash_free_driver_priv,
  815. };
  816. /* Static methods implementation */
  817. static int stm32lx_unlock_program_memory(struct flash_bank *bank)
  818. {
  819. struct target *target = bank->target;
  820. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  821. int retval;
  822. uint32_t reg32;
  823. /*
  824. * Unlocking the program memory is done by unlocking the PECR,
  825. * then by writing the 2 PRGKEY to the PRGKEYR register
  826. */
  827. /* check flash is not already unlocked */
  828. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  829. &reg32);
  830. if (retval != ERROR_OK)
  831. return retval;
  832. if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
  833. return ERROR_OK;
  834. /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
  835. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
  836. PEKEY1);
  837. if (retval != ERROR_OK)
  838. return retval;
  839. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
  840. PEKEY2);
  841. if (retval != ERROR_OK)
  842. return retval;
  843. /* Make sure it worked */
  844. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  845. &reg32);
  846. if (retval != ERROR_OK)
  847. return retval;
  848. if (reg32 & FLASH_PECR__PELOCK) {
  849. LOG_ERROR("PELOCK is not cleared :(");
  850. return ERROR_FLASH_OPERATION_FAILED;
  851. }
  852. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
  853. PRGKEY1);
  854. if (retval != ERROR_OK)
  855. return retval;
  856. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
  857. PRGKEY2);
  858. if (retval != ERROR_OK)
  859. return retval;
  860. /* Make sure it worked */
  861. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  862. &reg32);
  863. if (retval != ERROR_OK)
  864. return retval;
  865. if (reg32 & FLASH_PECR__PRGLOCK) {
  866. LOG_ERROR("PRGLOCK is not cleared :(");
  867. return ERROR_FLASH_OPERATION_FAILED;
  868. }
  869. return ERROR_OK;
  870. }
  871. static int stm32lx_enable_write_half_page(struct flash_bank *bank)
  872. {
  873. struct target *target = bank->target;
  874. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  875. int retval;
  876. uint32_t reg32;
  877. /**
  878. * Unlock the program memory, then set the FPRG bit in the PECR register.
  879. */
  880. retval = stm32lx_unlock_program_memory(bank);
  881. if (retval != ERROR_OK)
  882. return retval;
  883. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  884. &reg32);
  885. if (retval != ERROR_OK)
  886. return retval;
  887. reg32 |= FLASH_PECR__FPRG;
  888. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  889. reg32);
  890. if (retval != ERROR_OK)
  891. return retval;
  892. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  893. &reg32);
  894. if (retval != ERROR_OK)
  895. return retval;
  896. reg32 |= FLASH_PECR__PROG;
  897. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  898. reg32);
  899. return retval;
  900. }
  901. static int stm32lx_lock_program_memory(struct flash_bank *bank)
  902. {
  903. struct target *target = bank->target;
  904. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  905. int retval;
  906. uint32_t reg32;
  907. /* To lock the program memory, simply set the lock bit and lock PECR */
  908. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  909. &reg32);
  910. if (retval != ERROR_OK)
  911. return retval;
  912. reg32 |= FLASH_PECR__PRGLOCK;
  913. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  914. reg32);
  915. if (retval != ERROR_OK)
  916. return retval;
  917. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  918. &reg32);
  919. if (retval != ERROR_OK)
  920. return retval;
  921. reg32 |= FLASH_PECR__PELOCK;
  922. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  923. reg32);
  924. if (retval != ERROR_OK)
  925. return retval;
  926. return ERROR_OK;
  927. }
  928. static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
  929. {
  930. struct target *target = bank->target;
  931. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  932. int retval;
  933. uint32_t reg32;
  934. /*
  935. * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
  936. * first unlock the memory, loop over the pages of this sector
  937. * and write 0x0 to its first word.
  938. */
  939. retval = stm32lx_unlock_program_memory(bank);
  940. if (retval != ERROR_OK)
  941. return retval;
  942. for (int page = 0; page < (int)stm32lx_info->part_info.pages_per_sector;
  943. page++) {
  944. reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
  945. retval = target_write_u32(target,
  946. stm32lx_info->flash_base + FLASH_PECR, reg32);
  947. if (retval != ERROR_OK)
  948. return retval;
  949. retval = stm32lx_wait_until_bsy_clear(bank);
  950. if (retval != ERROR_OK)
  951. return retval;
  952. uint32_t addr = bank->base + bank->sectors[sector].offset + (page
  953. * stm32lx_info->part_info.page_size);
  954. retval = target_write_u32(target, addr, 0x0);
  955. if (retval != ERROR_OK)
  956. return retval;
  957. retval = stm32lx_wait_until_bsy_clear(bank);
  958. if (retval != ERROR_OK)
  959. return retval;
  960. }
  961. retval = stm32lx_lock_program_memory(bank);
  962. if (retval != ERROR_OK)
  963. return retval;
  964. return ERROR_OK;
  965. }
  966. static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
  967. {
  968. struct target *target = bank->target;
  969. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  970. return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
  971. }
  972. static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
  973. {
  974. return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
  975. }
  976. static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
  977. {
  978. struct target *target = bank->target;
  979. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  980. int retval;
  981. uint32_t reg32;
  982. /*
  983. * Unlocking the options bytes is done by unlocking the PECR,
  984. * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
  985. */
  986. /* check flash is not already unlocked */
  987. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
  988. if (retval != ERROR_OK)
  989. return retval;
  990. if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
  991. return ERROR_OK;
  992. if ((reg32 & FLASH_PECR__PELOCK) != 0) {
  993. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
  994. if (retval != ERROR_OK)
  995. return retval;
  996. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
  997. if (retval != ERROR_OK)
  998. return retval;
  999. }
  1000. /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
  1001. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
  1002. if (retval != ERROR_OK)
  1003. return retval;
  1004. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
  1005. if (retval != ERROR_OK)
  1006. return retval;
  1007. return ERROR_OK;
  1008. }
  1009. static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
  1010. {
  1011. struct target *target = bank->target;
  1012. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  1013. uint32_t status;
  1014. int retval = ERROR_OK;
  1015. /* wait for busy to clear */
  1016. for (;;) {
  1017. retval = stm32lx_get_flash_status(bank, &status);
  1018. if (retval != ERROR_OK)
  1019. return retval;
  1020. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  1021. if ((status & FLASH_SR__BSY) == 0)
  1022. break;
  1023. if (timeout-- <= 0) {
  1024. LOG_ERROR("timed out waiting for flash");
  1025. return ERROR_FAIL;
  1026. }
  1027. alive_sleep(1);
  1028. }
  1029. if (status & FLASH_SR__WRPERR) {
  1030. LOG_ERROR("access denied / write protected");
  1031. retval = ERROR_FAIL;
  1032. }
  1033. if (status & FLASH_SR__PGAERR) {
  1034. LOG_ERROR("invalid program address");
  1035. retval = ERROR_FAIL;
  1036. }
  1037. /* Clear but report errors */
  1038. if (status & FLASH_SR__OPTVERR) {
  1039. /* If this operation fails, we ignore it and report the original retval */
  1040. target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
  1041. }
  1042. return retval;
  1043. }
  1044. static int stm32lx_obl_launch(struct flash_bank *bank)
  1045. {
  1046. struct target *target = bank->target;
  1047. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  1048. int retval;
  1049. /* This will fail as the target gets immediately rebooted */
  1050. target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
  1051. FLASH_PECR__OBL_LAUNCH);
  1052. size_t tries = 10;
  1053. do {
  1054. target_halt(target);
  1055. retval = target_poll(target);
  1056. } while (--tries > 0 &&
  1057. (retval != ERROR_OK || target->state != TARGET_HALTED));
  1058. return tries ? ERROR_OK : ERROR_FAIL;
  1059. }
  1060. static int stm32lx_lock(struct flash_bank *bank)
  1061. {
  1062. int retval;
  1063. struct target *target = bank->target;
  1064. if (target->state != TARGET_HALTED) {
  1065. LOG_ERROR("Target not halted");
  1066. return ERROR_TARGET_NOT_HALTED;
  1067. }
  1068. retval = stm32lx_unlock_options_bytes(bank);
  1069. if (retval != ERROR_OK)
  1070. return retval;
  1071. /* set the RDP protection level to 1 */
  1072. retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
  1073. if (retval != ERROR_OK)
  1074. return retval;
  1075. return ERROR_OK;
  1076. }
  1077. static int stm32lx_unlock(struct flash_bank *bank)
  1078. {
  1079. int retval;
  1080. struct target *target = bank->target;
  1081. if (target->state != TARGET_HALTED) {
  1082. LOG_ERROR("Target not halted");
  1083. return ERROR_TARGET_NOT_HALTED;
  1084. }
  1085. retval = stm32lx_unlock_options_bytes(bank);
  1086. if (retval != ERROR_OK)
  1087. return retval;
  1088. /* set the RDP protection level to 0 */
  1089. retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
  1090. if (retval != ERROR_OK)
  1091. return retval;
  1092. retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
  1093. if (retval != ERROR_OK)
  1094. return retval;
  1095. return ERROR_OK;
  1096. }
  1097. static int stm32lx_mass_erase(struct flash_bank *bank)
  1098. {
  1099. int retval;
  1100. struct target *target = bank->target;
  1101. struct stm32lx_flash_bank *stm32lx_info = NULL;
  1102. uint32_t reg32;
  1103. if (target->state != TARGET_HALTED) {
  1104. LOG_ERROR("Target not halted");
  1105. return ERROR_TARGET_NOT_HALTED;
  1106. }
  1107. stm32lx_info = bank->driver_priv;
  1108. retval = stm32lx_lock(bank);
  1109. if (retval != ERROR_OK)
  1110. return retval;
  1111. retval = stm32lx_obl_launch(bank);
  1112. if (retval != ERROR_OK)
  1113. return retval;
  1114. retval = stm32lx_unlock(bank);
  1115. if (retval != ERROR_OK)
  1116. return retval;
  1117. retval = stm32lx_obl_launch(bank);
  1118. if (retval != ERROR_OK)
  1119. return retval;
  1120. retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
  1121. if (retval != ERROR_OK)
  1122. return retval;
  1123. retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
  1124. if (retval != ERROR_OK)
  1125. return retval;
  1126. return ERROR_OK;
  1127. }
  1128. static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb)
  1129. {
  1130. struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
  1131. switch (stm32lx_info->part_info.id) {
  1132. case 0x447: /* STM32L0xx (Cat.5) devices */
  1133. if (flash_size_in_kb == 192 || flash_size_in_kb == 128) {
  1134. stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
  1135. stm32lx_info->part_info.has_dual_banks = true;
  1136. }
  1137. break;
  1138. case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
  1139. stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
  1140. break;
  1141. }
  1142. return ERROR_OK;
  1143. }