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51 lines
1.4 KiB

  1. # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
  2. if { [info exists CHIPNAME] } {
  3. set _CHIPNAME $CHIPNAME
  4. } else {
  5. set _CHIPNAME lpc1768
  6. }
  7. if { [info exists ENDIAN] } {
  8. set _ENDIAN $ENDIAN
  9. } else {
  10. set _ENDIAN little
  11. }
  12. if { [info exists CPUTAPID ] } {
  13. set _CPUTAPID $CPUTAPID
  14. } else {
  15. set _CPUTAPID 0x4ba00477
  16. }
  17. #delays on reset lines
  18. jtag_nsrst_delay 200
  19. jtag_ntrst_delay 200
  20. # LPC2000 & LPC1700 -> SRST causes TRST
  21. reset_config trst_and_srst srst_pulls_trst
  22. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  23. set _TARGETNAME $_CHIPNAME.cpu
  24. target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
  25. # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
  26. $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
  27. $_TARGETNAME configure -event reset-init {
  28. # Force target into ARM state
  29. armv4_5 core_state arm
  30. #do not remap 0x0000-0x0020 to anything but the flash
  31. # mwb 0xE01FC040 0x01
  32. mwb 0xE000ED08 0x00
  33. }
  34. # LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
  35. # flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
  36. flash bank lpc2000 0x0 0x80000 0 0 0 lpc1700 12000 calc_checksum
  37. # 4MHz / 6 = 666kHz, so use 500
  38. jtag_khz 500