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- # Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
- #
- # !!!!!!
- #
- # This file should not be included directly, rather by the lpc11xx.cfg,
- # lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
- # appropriate values.
- #
- # !!!!!!
-
- # LPC8xx chips support only SWD transport.
- # LPC11xx chips support only SWD transport.
- # LPC12xx chips support only SWD transport.
- # LPC11Uxx chips support only SWD transports.
- # LPC13xx chips support only SWD transports.
- # LPC17xx chips support both JTAG and SWD transports.
- # LPC40xx chips support both JTAG and SWD transports.
- # Adapt based on what transport is active.
- source [find target/swj-dp.tcl]
-
- if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
- } else {
- error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
- }
-
- if { [info exists CHIPSERIES] } {
- # Validate chip series is supported
- if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
- error "Unsupported LPC1xxx chip series specified."
- }
- set _CHIPSERIES $CHIPSERIES
- } else {
- error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
- }
-
- # After reset, the chip is clocked by an internal RC oscillator.
- # When board-specific code (reset-init handler or device firmware)
- # configures another oscillator and/or PLL0, set CCLK to match; if
- # you don't, then flash erase and write operations may misbehave.
- # (The ROM code doing those updates cares about core clock speed...)
- # CCLK is the core clock frequency in KHz
- if { [info exists CCLK] } {
- # Allow user override
- set _CCLK $CCLK
- } else {
- # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
- if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
- set _CCLK 12000
- } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
- set _CCLK 4000
- }
- }
-
- if { [info exists CPUTAPID] } {
- # Allow user override
- set _CPUTAPID $CPUTAPID
- } else {
- # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
- if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
- set _CPUTAPID 0x0bb11477
- } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
- }
- }
-
- if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
- } else {
- error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
- }
-
- swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
- set _TARGETNAME $_CHIPNAME.cpu
- target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
- # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
- # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
- # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
- # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
- # The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
- # The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
- $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
-
- # The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
- # The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
- # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
- # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
- # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
- # The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
- #
- # All are compatible with the "lpc1700" variant of the LPC2000 flash driver
- # (same cmd51 destination boundary alignment, and all three support 256 byte
- # transfers).
- #
- # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
- set _FLASHNAME $_CHIPNAME.flash
- flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
- auto $_CCLK calc_checksum
-
- if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
- # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
- # Bit Symbol Value Description
- # 1:0 MAP System memory remap
- # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
- # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
- # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
- # 31:2 - - Reserved.
- $_TARGETNAME configure -event reset-init {
- mww 0x40048000 0x02
- }
- } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
- # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
- # Bit Symbol Value Description Reset
- # value
- # 0 MAP Memory map control. 0
- # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
- # 1 User mode. The on-chip Flash memory is mapped to address 0.
- # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
- #
- # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
- $_TARGETNAME configure -event reset-init {
- mww 0x400FC040 0x01
- }
- }
-
- # Run with *real slow* clock by default since the
- # boot rom could have been playing with the PLL, so
- # we have no idea what clock the target is running at.
- adapter_khz 10
-
- # delays on reset lines
- adapter_nsrst_delay 200
- if {[using_jtag]} {
- jtag_ntrst_delay 200
- }
-
- # LPC8xx (Cortex-M0+ core) support SYSRESETREQ
- # LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
- # LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
- # LPC40xx (Cortex-M4F core) support SYSRESETREQ
- if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
- }
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