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  1. # Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
  2. #
  3. # !!!!!!
  4. #
  5. # This file should not be included directly, rather by the lpc11xx.cfg,
  6. # lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
  7. # appropriate values.
  8. #
  9. # !!!!!!
  10. # LPC8xx chips support only SWD transport.
  11. # LPC11xx chips support only SWD transport.
  12. # LPC12xx chips support only SWD transport.
  13. # LPC11Uxx chips support only SWD transports.
  14. # LPC13xx chips support only SWD transports.
  15. # LPC17xx chips support both JTAG and SWD transports.
  16. # LPC40xx chips support both JTAG and SWD transports.
  17. # Adapt based on what transport is active.
  18. source [find target/swj-dp.tcl]
  19. if { [info exists CHIPNAME] } {
  20. set _CHIPNAME $CHIPNAME
  21. } else {
  22. error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
  23. }
  24. if { [info exists CHIPSERIES] } {
  25. # Validate chip series is supported
  26. if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
  27. error "Unsupported LPC1xxx chip series specified."
  28. }
  29. set _CHIPSERIES $CHIPSERIES
  30. } else {
  31. error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
  32. }
  33. # After reset, the chip is clocked by an internal RC oscillator.
  34. # When board-specific code (reset-init handler or device firmware)
  35. # configures another oscillator and/or PLL0, set CCLK to match; if
  36. # you don't, then flash erase and write operations may misbehave.
  37. # (The ROM code doing those updates cares about core clock speed...)
  38. # CCLK is the core clock frequency in KHz
  39. if { [info exists CCLK] } {
  40. # Allow user override
  41. set _CCLK $CCLK
  42. } else {
  43. # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
  44. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
  45. set _CCLK 12000
  46. } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  47. set _CCLK 4000
  48. }
  49. }
  50. if { [info exists CPUTAPID] } {
  51. # Allow user override
  52. set _CPUTAPID $CPUTAPID
  53. } else {
  54. # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
  55. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
  56. set _CPUTAPID 0x0bb11477
  57. } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  58. if { [using_jtag] } {
  59. set _CPUTAPID 0x4ba00477
  60. } {
  61. set _CPUTAPID 0x2ba01477
  62. }
  63. }
  64. }
  65. if { [info exists WORKAREASIZE] } {
  66. set _WORKAREASIZE $WORKAREASIZE
  67. } else {
  68. error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
  69. }
  70. swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  71. set _TARGETNAME $_CHIPNAME.cpu
  72. target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
  73. # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  74. # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  75. # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  76. # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  77. # The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  78. # The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
  79. $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
  80. # The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
  81. # The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
  82. # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
  83. # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
  84. # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
  85. # The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
  86. #
  87. # All are compatible with the "lpc1700" variant of the LPC2000 flash driver
  88. # (same cmd51 destination boundary alignment, and all three support 256 byte
  89. # transfers).
  90. #
  91. # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
  92. set _FLASHNAME $_CHIPNAME.flash
  93. flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
  94. auto $_CCLK calc_checksum
  95. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
  96. # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
  97. # "User Flash Mode" where interrupt vectors are _not_ remapped,
  98. # and reside in flash instead).
  99. #
  100. # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
  101. # Bit Symbol Value Description
  102. # 1:0 MAP System memory remap
  103. # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
  104. # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
  105. # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
  106. # 31:2 - - Reserved.
  107. $_TARGETNAME configure -event reset-init {
  108. mww 0x40048000 0x02
  109. }
  110. } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  111. # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
  112. # "User Flash Mode" where interrupt vectors are _not_ remapped,
  113. # and reside in flash instead).
  114. #
  115. # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
  116. # Bit Symbol Value Description Reset
  117. # value
  118. # 0 MAP Memory map control. 0
  119. # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
  120. # 1 User mode. The on-chip Flash memory is mapped to address 0.
  121. # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
  122. #
  123. # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
  124. $_TARGETNAME configure -event reset-init {
  125. mww 0x400FC040 0x01
  126. }
  127. }
  128. # Run with *real slow* clock by default since the
  129. # boot rom could have been playing with the PLL, so
  130. # we have no idea what clock the target is running at.
  131. adapter_khz 10
  132. # delays on reset lines
  133. adapter_nsrst_delay 200
  134. if {[using_jtag]} {
  135. jtag_ntrst_delay 200
  136. }
  137. # LPC8xx (Cortex-M0+ core) support SYSRESETREQ
  138. # LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
  139. # LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
  140. # LPC40xx (Cortex-M4F core) support SYSRESETREQ
  141. if {![using_hla]} {
  142. # if srst is not fitted use SYSRESETREQ to
  143. # perform a soft reset
  144. cortex_m reset_config sysresetreq
  145. }