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  1. #
  2. # script for Nordic nRF51 series, a Cortex-M0 chip
  3. #
  4. source [find target/swj-dp.tcl]
  5. if { [info exists CHIPNAME] } {
  6. set _CHIPNAME $CHIPNAME
  7. } else {
  8. set _CHIPNAME nrf51
  9. }
  10. if { [info exists ENDIAN] } {
  11. set _ENDIAN $ENDIAN
  12. } else {
  13. set _ENDIAN little
  14. }
  15. # Work-area is a space in RAM used for flash programming
  16. # By default use 16kB
  17. if { [info exists WORKAREASIZE] } {
  18. set _WORKAREASIZE $WORKAREASIZE
  19. } else {
  20. set _WORKAREASIZE 0x4000
  21. }
  22. if { [info exists CPUTAPID] } {
  23. set _CPUTAPID $CPUTAPID
  24. } else {
  25. set _CPUTAPID 0x0bb11477
  26. }
  27. swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
  28. set _TARGETNAME $_CHIPNAME.cpu
  29. target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
  30. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  31. if {![using_hla]} {
  32. # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
  33. cortex_m reset_config sysresetreq
  34. }
  35. flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
  36. flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
  37. #
  38. # The chip should start up from internal 16Mhz RC, so setting adapter
  39. # clock to 1Mhz should be OK
  40. #
  41. adapter_khz 1000
  42. proc enable_all_ram {} {
  43. # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
  44. # are reliably enabled after reset on some revisions (contrary to spec.) So after
  45. # resetting we enable all banks via the RAMON register
  46. mww 0x40000524 0xF
  47. }
  48. $_TARGETNAME configure -event reset-end { enable_all_ram }