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- #
- # script for Nordic nRF51 series, a Cortex-M0 chip
- #
-
- source [find target/swj-dp.tcl]
-
- if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
- } else {
- set _CHIPNAME nrf51
- }
-
- if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
- } else {
- set _ENDIAN little
- }
-
- # Work-area is a space in RAM used for flash programming
- # By default use 16kB
- if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
- } else {
- set _WORKAREASIZE 0x4000
- }
-
- if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
- } else {
- set _CPUTAPID 0x0bb11477
- }
-
- swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
- set _TARGETNAME $_CHIPNAME.cpu
- target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
- $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
- if {![using_hla]} {
- # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
- cortex_m reset_config sysresetreq
- }
-
- flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
- flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
-
- #
- # The chip should start up from internal 16Mhz RC, so setting adapter
- # clock to 1Mhz should be OK
- #
- adapter_khz 1000
-
- proc enable_all_ram {} {
- # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
- # are reliably enabled after reset on some revisions (contrary to spec.) So after
- # resetting we enable all banks via the RAMON register
- mww 0x40000524 0xF
- }
- $_TARGETNAME configure -event reset-end { enable_all_ram }
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