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  1. #
  2. # Texas Instruments DaVinci family: TMS320DM6446
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME dm6446
  8. }
  9. #
  10. # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
  11. # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
  12. # Override by setting EMU01 to "-disable".
  13. #
  14. # Also note: when running without RTCK before the PLLs are set up, you
  15. # may need to slow the JTAG clock down quite a lot (under 2 MHz).
  16. #
  17. source [find target/icepick.cfg]
  18. set EMU01 "-enable"
  19. #set EMU01 "-disable"
  20. # Subsidiary TAP: unknown ... must enable via ICEpick
  21. jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
  22. jtag configure $_CHIPNAME.unknown -event tap-enable \
  23. "icepick_c_tapenable $_CHIPNAME.jrc 3"
  24. # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  25. jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  26. jtag configure $_CHIPNAME.dsp -event tap-enable \
  27. "icepick_c_tapenable $_CHIPNAME.jrc 2"
  28. # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  29. if { [info exists ETB_TAPID ] } {
  30. set _ETB_TAPID $ETB_TAPID
  31. } else {
  32. set _ETB_TAPID 0x2b900f0f
  33. }
  34. jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
  35. -expected-id $_ETB_TAPID $EMU01
  36. jtag configure $_CHIPNAME.etb -event tap-enable \
  37. "icepick_c_tapenable $_CHIPNAME.jrc 1"
  38. # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  39. if { [info exists CPU_TAPID ] } {
  40. set _CPU_TAPID $CPU_TAPID
  41. } else {
  42. set _CPU_TAPID 0x07926001
  43. }
  44. jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
  45. -expected-id $_CPU_TAPID $EMU01
  46. jtag configure $_CHIPNAME.arm -event tap-enable \
  47. "icepick_c_tapenable $_CHIPNAME.jrc 0"
  48. # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  49. if { [info exists JRC_TAPID ] } {
  50. set _JRC_TAPID $JRC_TAPID
  51. } else {
  52. set _JRC_TAPID 0x0b70002f
  53. }
  54. jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  55. -expected-id $_JRC_TAPID
  56. # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
  57. # and the ETB memory (4K) are other options, while trace is unused.
  58. # Little-endian; use the OpenOCD default.
  59. set _TARGETNAME $_CHIPNAME.arm
  60. target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  61. $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
  62. # be absolutely certain the JTAG clock will work with the worst-case
  63. # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
  64. # on the PLL and starts using it. OK to speed up after clock setup.
  65. jtag_rclk 1500
  66. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  67. arm7_9 fast_memory_access enable
  68. arm7_9 dcc_downloads enable
  69. # trace setup
  70. etm config $_TARGETNAME 16 normal full etb
  71. etb config $_TARGETNAME $_CHIPNAME.etb