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  1. /*
  2. * Copyright (C) 2005 by Dominic Rath
  3. * Dominic.Rath@gmx.de
  4. *
  5. * Copyright (C) 2008 by Spencer Oliver
  6. * spen@spen-soft.co.uk
  7. *
  8. * Copyright (C) 2009 by √ėyvind Harboe
  9. * oyvind.harboe@zylin.com
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the
  23. * Free Software Foundation, Inc.,
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  25. */
  26. #ifndef ARM_H
  27. #define ARM_H
  28. #include <helper/command.h>
  29. #include "target.h"
  30. /**
  31. * @file
  32. * Holds the interface to ARM cores.
  33. *
  34. * At this writing, only "classic ARM" cores built on the ARMv4 register
  35. * and mode model are supported. The Thumb2-only microcontroller profile
  36. * support has not yet been integrated, affecting Cortex-M parts.
  37. */
  38. /**
  39. * These numbers match the five low bits of the *PSR registers on
  40. * "classic ARM" processors, which build on the ARMv4 processor
  41. * modes and register set.
  42. */
  43. enum arm_mode {
  44. ARM_MODE_USR = 16,
  45. ARM_MODE_FIQ = 17,
  46. ARM_MODE_IRQ = 18,
  47. ARM_MODE_SVC = 19,
  48. ARM_MODE_ABT = 23,
  49. ARM_MODE_MON = 26,
  50. ARM_MODE_UND = 27,
  51. ARM_MODE_SYS = 31,
  52. ARM_MODE_ANY = -1
  53. };
  54. const char *arm_mode_name(unsigned psr_mode);
  55. bool is_arm_mode(unsigned psr_mode);
  56. /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  57. enum arm_state {
  58. ARM_STATE_ARM,
  59. ARM_STATE_THUMB,
  60. ARM_STATE_JAZELLE,
  61. ARM_STATE_THUMB_EE,
  62. };
  63. extern const char *arm_state_strings[];
  64. #define ARM_COMMON_MAGIC 0x0A450A45
  65. /**
  66. * Represents a generic ARM core, with standard application registers.
  67. *
  68. * There are sixteen application registers (including PC, SP, LR) and a PSR.
  69. * Cortex-M series cores do not support as many core states or shadowed
  70. * registers as traditional ARM cores, and only support Thumb2 instructions.
  71. */
  72. struct arm {
  73. int common_magic;
  74. struct reg_cache *core_cache;
  75. /** Handle to the CPSR; valid in all core modes. */
  76. struct reg *cpsr;
  77. /** Handle to the SPSR; valid only in core modes with an SPSR. */
  78. struct reg *spsr;
  79. /** Support for arm_reg_current() */
  80. const int *map;
  81. /**
  82. * Indicates what registers are in the ARM state core register set.
  83. * ARM_MODE_ANY indicates the standard set of 37 registers,
  84. * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
  85. * more registers are shadowed, for "Secure Monitor" mode.
  86. */
  87. enum arm_mode core_type;
  88. /** Record the current core mode: SVC, USR, or some other mode. */
  89. enum arm_mode core_mode;
  90. /** Record the current core state: ARM, Thumb, or otherwise. */
  91. enum arm_state core_state;
  92. /** Flag reporting unavailability of the BKPT instruction. */
  93. bool is_armv4;
  94. /** Flag reporting whether semihosting is active. */
  95. bool is_semihosting;
  96. /** Value to be returned by semihosting SYS_ERRNO request. */
  97. int semihosting_errno;
  98. /** Backpointer to the target. */
  99. struct target *target;
  100. /** Handle for the debug module, if one is present. */
  101. struct arm_dpm *dpm;
  102. /** Handle for the Embedded Trace Module, if one is present. */
  103. struct etm_context *etm;
  104. /* FIXME all these methods should take "struct arm *" not target */
  105. /** Retrieve all core registers, for display. */
  106. int (*full_context)(struct target *target);
  107. /** Retrieve a single core register. */
  108. int (*read_core_reg)(struct target *target, struct reg *reg,
  109. int num, enum arm_mode mode);
  110. int (*write_core_reg)(struct target *target, struct reg *reg,
  111. int num, enum arm_mode mode, uint32_t value);
  112. /** Read coprocessor register. */
  113. int (*mrc)(struct target *target, int cpnum,
  114. uint32_t op1, uint32_t op2,
  115. uint32_t CRn, uint32_t CRm,
  116. uint32_t *value);
  117. /** Write coprocessor register. */
  118. int (*mcr)(struct target *target, int cpnum,
  119. uint32_t op1, uint32_t op2,
  120. uint32_t CRn, uint32_t CRm,
  121. uint32_t value);
  122. void *arch_info;
  123. };
  124. /** Convert target handle to generic ARM target state handle. */
  125. static inline struct arm *target_to_arm(struct target *target)
  126. {
  127. return target->arch_info;
  128. }
  129. static inline bool is_arm(struct arm *arm)
  130. {
  131. return arm && arm->common_magic == ARM_COMMON_MAGIC;
  132. }
  133. struct arm_algorithm {
  134. int common_magic;
  135. enum arm_mode core_mode;
  136. enum arm_state core_state;
  137. };
  138. struct arm_reg {
  139. int num;
  140. enum arm_mode mode;
  141. struct target *target;
  142. struct arm *armv4_5_common;
  143. uint32_t value;
  144. };
  145. struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
  146. extern const struct command_registration arm_command_handlers[];
  147. int arm_arch_state(struct target *target);
  148. int arm_get_gdb_reg_list(struct target *target,
  149. struct reg **reg_list[], int *reg_list_size);
  150. int arm_init_arch_info(struct target *target, struct arm *arm);
  151. /* REVISIT rename this once it's usable by ARMv7-M */
  152. int armv4_5_run_algorithm(struct target *target,
  153. int num_mem_params, struct mem_param *mem_params,
  154. int num_reg_params, struct reg_param *reg_params,
  155. uint32_t entry_point, uint32_t exit_point,
  156. int timeout_ms, void *arch_info);
  157. int armv4_5_run_algorithm_inner(struct target *target,
  158. int num_mem_params, struct mem_param *mem_params,
  159. int num_reg_params, struct reg_param *reg_params,
  160. uint32_t entry_point, uint32_t exit_point,
  161. int timeout_ms, void *arch_info,
  162. int (*run_it)(struct target *target, uint32_t exit_point,
  163. int timeout_ms, void *arch_info));
  164. int arm_checksum_memory(struct target *target,
  165. uint32_t address, uint32_t count, uint32_t *checksum);
  166. int arm_blank_check_memory(struct target *target,
  167. uint32_t address, uint32_t count, uint32_t *blank);
  168. void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
  169. struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
  170. void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
  171. extern struct reg arm_gdb_dummy_fp_reg;
  172. extern struct reg arm_gdb_dummy_fps_reg;
  173. #endif /* ARM_H */