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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2009 by √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "arm720t.h"
  27. #include <helper/time_support.h>
  28. #include "target_type.h"
  29. #include "register.h"
  30. #include "arm_opcodes.h"
  31. /*
  32. * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
  33. * ARM DDI 0229C especially Chapter 9 about debug support.
  34. */
  35. #if 0
  36. #define _DEBUG_INSTRUCTION_EXECUTION_
  37. #endif
  38. static int arm720t_scan_cp15(struct target *target,
  39. uint32_t out, uint32_t *in, int instruction, int clock)
  40. {
  41. int retval;
  42. struct arm720t_common *arm720t = target_to_arm720(target);
  43. struct arm_jtag *jtag_info;
  44. struct scan_field fields[2];
  45. uint8_t out_buf[4];
  46. uint8_t instruction_buf = instruction;
  47. jtag_info = &arm720t->arm7_9_common.jtag_info;
  48. buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  49. jtag_set_end_state(TAP_DRPAUSE);
  50. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  51. {
  52. return retval;
  53. }
  54. if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
  55. {
  56. return retval;
  57. }
  58. fields[0].tap = jtag_info->tap;
  59. fields[0].num_bits = 1;
  60. fields[0].out_value = &instruction_buf;
  61. fields[0].in_value = NULL;
  62. fields[1].tap = jtag_info->tap;
  63. fields[1].num_bits = 32;
  64. fields[1].out_value = out_buf;
  65. fields[1].in_value = NULL;
  66. if (in)
  67. {
  68. fields[1].in_value = (uint8_t *)in;
  69. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  70. jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  71. } else
  72. {
  73. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  74. }
  75. if (clock)
  76. jtag_add_runtest(0, jtag_get_end_state());
  77. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  78. if ((retval = jtag_execute_queue()) != ERROR_OK)
  79. {
  80. return retval;
  81. }
  82. if (in)
  83. LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  84. else
  85. LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  86. #else
  87. LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
  88. #endif
  89. return ERROR_OK;
  90. }
  91. static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
  92. {
  93. /* fetch CP15 opcode */
  94. arm720t_scan_cp15(target, opcode, NULL, 1, 1);
  95. /* "DECODE" stage */
  96. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
  97. /* "EXECUTE" stage (1) */
  98. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
  99. arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
  100. /* "EXECUTE" stage (2) */
  101. arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
  102. /* "EXECUTE" stage (3), CDATA is read */
  103. arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
  104. return ERROR_OK;
  105. }
  106. static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
  107. {
  108. /* fetch CP15 opcode */
  109. arm720t_scan_cp15(target, opcode, NULL, 1, 1);
  110. /* "DECODE" stage */
  111. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
  112. /* "EXECUTE" stage (1) */
  113. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
  114. arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
  115. /* "EXECUTE" stage (2) */
  116. arm720t_scan_cp15(target, value, NULL, 0, 1);
  117. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
  118. return ERROR_OK;
  119. }
  120. static uint32_t arm720t_get_ttb(struct target *target)
  121. {
  122. uint32_t ttb = 0x0;
  123. arm720t_read_cp15(target, 0xee120f10, &ttb);
  124. jtag_execute_queue();
  125. ttb &= 0xffffc000;
  126. return ttb;
  127. }
  128. static void arm720t_disable_mmu_caches(struct target *target,
  129. int mmu, int d_u_cache, int i_cache)
  130. {
  131. uint32_t cp15_control;
  132. /* read cp15 control register */
  133. arm720t_read_cp15(target, 0xee110f10, &cp15_control);
  134. jtag_execute_queue();
  135. if (mmu)
  136. cp15_control &= ~0x1U;
  137. if (d_u_cache || i_cache)
  138. cp15_control &= ~0x4U;
  139. arm720t_write_cp15(target, 0xee010f10, cp15_control);
  140. }
  141. static void arm720t_enable_mmu_caches(struct target *target,
  142. int mmu, int d_u_cache, int i_cache)
  143. {
  144. uint32_t cp15_control;
  145. /* read cp15 control register */
  146. arm720t_read_cp15(target, 0xee110f10, &cp15_control);
  147. jtag_execute_queue();
  148. if (mmu)
  149. cp15_control |= 0x1U;
  150. if (d_u_cache || i_cache)
  151. cp15_control |= 0x4U;
  152. arm720t_write_cp15(target, 0xee010f10, cp15_control);
  153. }
  154. static void arm720t_post_debug_entry(struct target *target)
  155. {
  156. struct arm720t_common *arm720t = target_to_arm720(target);
  157. /* examine cp15 control reg */
  158. arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
  159. jtag_execute_queue();
  160. LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
  161. arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
  162. arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
  163. arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  164. /* save i/d fault status and address register */
  165. arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
  166. arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
  167. jtag_execute_queue();
  168. }
  169. static void arm720t_pre_restore_context(struct target *target)
  170. {
  171. struct arm720t_common *arm720t = target_to_arm720(target);
  172. /* restore i/d fault status and address register */
  173. arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
  174. arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
  175. }
  176. static int arm720t_verify_pointer(struct command_context *cmd_ctx,
  177. struct arm720t_common *arm720t)
  178. {
  179. if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
  180. command_print(cmd_ctx, "target is not an ARM720");
  181. return ERROR_TARGET_INVALID;
  182. }
  183. return ERROR_OK;
  184. }
  185. static int arm720t_arch_state(struct target *target)
  186. {
  187. struct arm720t_common *arm720t = target_to_arm720(target);
  188. struct arm *armv4_5;
  189. static const char *state[] =
  190. {
  191. "disabled", "enabled"
  192. };
  193. armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
  194. arm_arch_state(target);
  195. LOG_USER("MMU: %s, Cache: %s",
  196. state[arm720t->armv4_5_mmu.mmu_enabled],
  197. state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
  198. return ERROR_OK;
  199. }
  200. static int arm720_mmu(struct target *target, int *enabled)
  201. {
  202. if (target->state != TARGET_HALTED) {
  203. LOG_ERROR("%s: target not halted", __func__);
  204. return ERROR_TARGET_INVALID;
  205. }
  206. *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
  207. return ERROR_OK;
  208. }
  209. static int arm720_virt2phys(struct target *target,
  210. uint32_t virt, uint32_t *phys)
  211. {
  212. /** @todo Implement this! */
  213. LOG_ERROR("%s: not implemented", __func__);
  214. return ERROR_FAIL;
  215. }
  216. static int arm720t_read_memory(struct target *target,
  217. uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  218. {
  219. int retval;
  220. struct arm720t_common *arm720t = target_to_arm720(target);
  221. /* disable cache, but leave MMU enabled */
  222. if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
  223. arm720t_disable_mmu_caches(target, 0, 1, 0);
  224. retval = arm7_9_read_memory(target, address, size, count, buffer);
  225. if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
  226. arm720t_enable_mmu_caches(target, 0, 1, 0);
  227. return retval;
  228. }
  229. static int arm720t_read_phys_memory(struct target *target,
  230. uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  231. {
  232. struct arm720t_common *arm720t = target_to_arm720(target);
  233. return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
  234. }
  235. static int arm720t_write_phys_memory(struct target *target,
  236. uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  237. {
  238. struct arm720t_common *arm720t = target_to_arm720(target);
  239. return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
  240. }
  241. static int arm720t_soft_reset_halt(struct target *target)
  242. {
  243. int retval = ERROR_OK;
  244. struct arm720t_common *arm720t = target_to_arm720(target);
  245. struct reg *dbg_stat = &arm720t->arm7_9_common
  246. .eice_cache->reg_list[EICE_DBG_STAT];
  247. struct arm *armv4_5 = &arm720t->arm7_9_common
  248. .armv4_5_common;
  249. if ((retval = target_halt(target)) != ERROR_OK)
  250. {
  251. return retval;
  252. }
  253. long long then = timeval_ms();
  254. int timeout;
  255. while (!(timeout = ((timeval_ms()-then) > 1000)))
  256. {
  257. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
  258. {
  259. embeddedice_read_reg(dbg_stat);
  260. if ((retval = jtag_execute_queue()) != ERROR_OK)
  261. {
  262. return retval;
  263. }
  264. } else
  265. {
  266. break;
  267. }
  268. if (debug_level >= 3)
  269. {
  270. alive_sleep(100);
  271. } else
  272. {
  273. keep_alive();
  274. }
  275. }
  276. if (timeout)
  277. {
  278. LOG_ERROR("Failed to halt CPU after 1 sec");
  279. return ERROR_TARGET_TIMEOUT;
  280. }
  281. target->state = TARGET_HALTED;
  282. /* SVC, ARM state, IRQ and FIQ disabled */
  283. uint32_t cpsr;
  284. cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
  285. cpsr &= ~0xff;
  286. cpsr |= 0xd3;
  287. arm_set_cpsr(armv4_5, cpsr);
  288. armv4_5->cpsr->dirty = 1;
  289. /* start fetching from 0x0 */
  290. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  291. armv4_5->core_cache->reg_list[15].dirty = 1;
  292. armv4_5->core_cache->reg_list[15].valid = 1;
  293. arm720t_disable_mmu_caches(target, 1, 1, 1);
  294. arm720t->armv4_5_mmu.mmu_enabled = 0;
  295. arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
  296. arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  297. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
  298. {
  299. return retval;
  300. }
  301. return ERROR_OK;
  302. }
  303. static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
  304. {
  305. return arm7tdmi_init_target(cmd_ctx, target);
  306. }
  307. /* FIXME remove forward decls */
  308. static int arm720t_mrc(struct target *target, int cpnum,
  309. uint32_t op1, uint32_t op2,
  310. uint32_t CRn, uint32_t CRm,
  311. uint32_t *value);
  312. static int arm720t_mcr(struct target *target, int cpnum,
  313. uint32_t op1, uint32_t op2,
  314. uint32_t CRn, uint32_t CRm,
  315. uint32_t value);
  316. static int arm720t_init_arch_info(struct target *target,
  317. struct arm720t_common *arm720t, struct jtag_tap *tap)
  318. {
  319. struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
  320. arm7_9->armv4_5_common.mrc = arm720t_mrc;
  321. arm7_9->armv4_5_common.mcr = arm720t_mcr;
  322. arm7tdmi_init_arch_info(target, arm7_9, tap);
  323. arm720t->common_magic = ARM720T_COMMON_MAGIC;
  324. arm7_9->post_debug_entry = arm720t_post_debug_entry;
  325. arm7_9->pre_restore_context = arm720t_pre_restore_context;
  326. arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
  327. arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
  328. arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
  329. arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
  330. arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
  331. arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
  332. arm720t->armv4_5_mmu.has_tiny_pages = 0;
  333. arm720t->armv4_5_mmu.mmu_enabled = 0;
  334. return ERROR_OK;
  335. }
  336. static int arm720t_target_create(struct target *target, Jim_Interp *interp)
  337. {
  338. struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
  339. arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
  340. return arm720t_init_arch_info(target, arm720t, target->tap);
  341. }
  342. COMMAND_HANDLER(arm720t_handle_cp15_command)
  343. {
  344. int retval;
  345. struct target *target = get_current_target(CMD_CTX);
  346. struct arm720t_common *arm720t = target_to_arm720(target);
  347. struct arm_jtag *jtag_info;
  348. retval = arm720t_verify_pointer(CMD_CTX, arm720t);
  349. if (retval != ERROR_OK)
  350. return retval;
  351. jtag_info = &arm720t->arm7_9_common.jtag_info;
  352. if (target->state != TARGET_HALTED)
  353. {
  354. command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
  355. return ERROR_OK;
  356. }
  357. /* one or more argument, access a single register (write if second argument is given */
  358. if (CMD_ARGC >= 1)
  359. {
  360. uint32_t opcode;
  361. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
  362. if (CMD_ARGC == 1)
  363. {
  364. uint32_t value;
  365. if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
  366. {
  367. command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
  368. return ERROR_OK;
  369. }
  370. if ((retval = jtag_execute_queue()) != ERROR_OK)
  371. {
  372. return retval;
  373. }
  374. command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
  375. }
  376. else if (CMD_ARGC == 2)
  377. {
  378. uint32_t value;
  379. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
  380. if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
  381. {
  382. command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
  383. return ERROR_OK;
  384. }
  385. command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
  386. }
  387. }
  388. return ERROR_OK;
  389. }
  390. static int arm720t_mrc(struct target *target, int cpnum,
  391. uint32_t op1, uint32_t op2,
  392. uint32_t CRn, uint32_t CRm,
  393. uint32_t *value)
  394. {
  395. if (cpnum!=15)
  396. {
  397. LOG_ERROR("Only cp15 is supported");
  398. return ERROR_FAIL;
  399. }
  400. /* read "to" r0 */
  401. return arm720t_read_cp15(target,
  402. ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  403. value);
  404. }
  405. static int arm720t_mcr(struct target *target, int cpnum,
  406. uint32_t op1, uint32_t op2,
  407. uint32_t CRn, uint32_t CRm,
  408. uint32_t value)
  409. {
  410. if (cpnum!=15)
  411. {
  412. LOG_ERROR("Only cp15 is supported");
  413. return ERROR_FAIL;
  414. }
  415. /* write "from" r0 */
  416. return arm720t_write_cp15(target,
  417. ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  418. value);
  419. }
  420. static const struct command_registration arm720t_exec_command_handlers[] = {
  421. {
  422. .name = "cp15",
  423. .handler = arm720t_handle_cp15_command,
  424. .mode = COMMAND_EXEC,
  425. /* prefer using less error-prone "arm mcr" or "arm mrc" */
  426. .help = "display/modify cp15 register using ARM opcode"
  427. " (DEPRECATED)",
  428. .usage = "instruction [value]",
  429. },
  430. COMMAND_REGISTRATION_DONE
  431. };
  432. static const struct command_registration arm720t_command_handlers[] = {
  433. {
  434. .chain = arm7_9_command_handlers,
  435. },
  436. {
  437. .name = "arm720t",
  438. .mode = COMMAND_ANY,
  439. .help = "arm720t command group",
  440. .chain = arm720t_exec_command_handlers,
  441. },
  442. COMMAND_REGISTRATION_DONE
  443. };
  444. /** Holds methods for ARM720 targets. */
  445. struct target_type arm720t_target =
  446. {
  447. .name = "arm720t",
  448. .poll = arm7_9_poll,
  449. .arch_state = arm720t_arch_state,
  450. .halt = arm7_9_halt,
  451. .resume = arm7_9_resume,
  452. .step = arm7_9_step,
  453. .assert_reset = arm7_9_assert_reset,
  454. .deassert_reset = arm7_9_deassert_reset,
  455. .soft_reset_halt = arm720t_soft_reset_halt,
  456. .get_gdb_reg_list = arm_get_gdb_reg_list,
  457. .read_memory = arm720t_read_memory,
  458. .write_memory = arm7_9_write_memory,
  459. .read_phys_memory = arm720t_read_phys_memory,
  460. .write_phys_memory = arm720t_write_phys_memory,
  461. .mmu = arm720_mmu,
  462. .virt2phys = arm720_virt2phys,
  463. .bulk_write_memory = arm7_9_bulk_write_memory,
  464. .checksum_memory = arm_checksum_memory,
  465. .blank_check_memory = arm_blank_check_memory,
  466. .run_algorithm = armv4_5_run_algorithm,
  467. .add_breakpoint = arm7_9_add_breakpoint,
  468. .remove_breakpoint = arm7_9_remove_breakpoint,
  469. .add_watchpoint = arm7_9_add_watchpoint,
  470. .remove_watchpoint = arm7_9_remove_watchpoint,
  471. .commands = arm720t_command_handlers,
  472. .target_create = arm720t_target_create,
  473. .init_target = arm720t_init_target,
  474. .examine = arm7_9_examine,
  475. };