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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2007,2008 √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * Copyright (C) 2008 by Hongtao Zheng *
  12. * hontor@126.com *
  13. * *
  14. * This program is free software; you can redistribute it and/or modify *
  15. * it under the terms of the GNU General Public License as published by *
  16. * the Free Software Foundation; either version 2 of the License, or *
  17. * (at your option) any later version. *
  18. * *
  19. * This program is distributed in the hope that it will be useful, *
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  22. * GNU General Public License for more details. *
  23. * *
  24. * You should have received a copy of the GNU General Public License *
  25. * along with this program; if not, write to the *
  26. * Free Software Foundation, Inc., *
  27. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  28. ***************************************************************************/
  29. #ifndef ARM7_9_COMMON_H
  30. #define ARM7_9_COMMON_H
  31. #include "arm.h"
  32. #include "arm_jtag.h"
  33. #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
  34. /**
  35. * Structure for items that are common between both ARM7 and ARM9 targets.
  36. */
  37. struct arm7_9_common
  38. {
  39. struct arm armv4_5_common;
  40. uint32_t common_magic;
  41. struct arm_jtag jtag_info; /**< JTAG information for target */
  42. struct reg_cache *eice_cache; /**< Embedded ICE register cache */
  43. uint32_t arm_bkpt; /**< ARM breakpoint instruction */
  44. uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
  45. int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
  46. int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
  47. int breakpoint_count; /**< Current number of set breakpoints */
  48. int wp_available; /**< Current number of available watchpoint units */
  49. int wp_available_max; /**< Maximum number of available watchpoint units */
  50. int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
  51. int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
  52. int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
  53. int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
  54. bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
  55. bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
  56. bool has_single_step;
  57. bool has_monitor_mode;
  58. bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
  59. bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
  60. bool fast_memory_access;
  61. bool dcc_downloads;
  62. struct working_area *dcc_working_area;
  63. int (*examine_debug_reason)(struct target *target); /**< Function for determining why debug state was entered */
  64. void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
  65. void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
  66. void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size);
  67. void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
  68. void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
  69. void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
  70. void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
  71. void (*load_word_regs)(struct target *target, uint32_t mask);
  72. void (*load_hword_reg)(struct target *target, int num);
  73. void (*load_byte_reg)(struct target *target, int num);
  74. void (*store_word_regs)(struct target *target, uint32_t mask);
  75. void (*store_hword_reg)(struct target *target, int num);
  76. void (*store_byte_reg)(struct target *target, int num);
  77. void (*write_pc)(struct target *target, uint32_t pc); /**< Function for writing to the program counter */
  78. void (*branch_resume)(struct target *target);
  79. void (*branch_resume_thumb)(struct target *target);
  80. void (*enable_single_step)(struct target *target, uint32_t next_pc);
  81. void (*disable_single_step)(struct target *target);
  82. void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */
  83. void (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
  84. void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */
  85. void (*post_restore_context)(struct target *target); /**< Callback function called after restoring the processor context */
  86. };
  87. static inline struct arm7_9_common *
  88. target_to_arm7_9(struct target *target)
  89. {
  90. return container_of(target->arch_info, struct arm7_9_common,
  91. armv4_5_common);
  92. }
  93. static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
  94. {
  95. return arm7_9->common_magic == ARM7_9_COMMON_MAGIC;
  96. }
  97. extern const struct command_registration arm7_9_command_handlers[];
  98. int arm7_9_poll(struct target *target);
  99. int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
  100. int arm7_9_setup(struct target *target);
  101. int arm7_9_assert_reset(struct target *target);
  102. int arm7_9_deassert_reset(struct target *target);
  103. int arm7_9_reset_request_halt(struct target *target);
  104. int arm7_9_early_halt(struct target *target);
  105. int arm7_9_soft_reset_halt(struct target *target);
  106. int arm7_9_prepare_reset_halt(struct target *target);
  107. int arm7_9_halt(struct target *target);
  108. int arm7_9_full_context(struct target *target);
  109. int arm7_9_restore_context(struct target *target);
  110. int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
  111. int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
  112. int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  113. int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  114. int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
  115. int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
  116. int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
  117. int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
  118. int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
  119. int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
  120. void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
  121. void arm7_9_disable_eice_step(struct target *target);
  122. int arm7_9_execute_sys_speed(struct target *target);
  123. int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
  124. int arm7_9_examine(struct target *target);
  125. #endif /* ARM7_9_COMMON_H */