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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2008 by Hongtao Zheng *
  9. * hontor@126.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "arm9tdmi.h"
  30. #include "target_type.h"
  31. #include "register.h"
  32. #include "arm_opcodes.h"
  33. /*
  34. * NOTE: this holds code that's used with multiple ARM9 processors:
  35. * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
  36. * - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
  37. * - ARM9EJS (ARMv5TEJ) ... in ARM926 core
  38. *
  39. * In short, the file name is a misnomer ... it is NOT specific to
  40. * that first generation ARM9 processor, or cores using it.
  41. */
  42. #if 0
  43. #define _DEBUG_INSTRUCTION_EXECUTION_
  44. #endif
  45. enum arm9tdmi_vector_bit
  46. {
  47. ARM9TDMI_RESET_VECTOR = 0x01,
  48. ARM9TDMI_UNDEF_VECTOR = 0x02,
  49. ARM9TDMI_SWI_VECTOR = 0x04,
  50. ARM9TDMI_PABT_VECTOR = 0x08,
  51. ARM9TDMI_DABT_VECTOR = 0x10,
  52. /* BIT(5) reserved -- must be zero */
  53. ARM9TDMI_IRQ_VECTOR = 0x40,
  54. ARM9TDMI_FIQ_VECTOR = 0x80,
  55. };
  56. static const struct arm9tdmi_vector {
  57. char *name;
  58. uint32_t value;
  59. } arm9tdmi_vectors[] = {
  60. {"reset", ARM9TDMI_RESET_VECTOR},
  61. {"undef", ARM9TDMI_UNDEF_VECTOR},
  62. {"swi", ARM9TDMI_SWI_VECTOR},
  63. {"pabt", ARM9TDMI_PABT_VECTOR},
  64. {"dabt", ARM9TDMI_DABT_VECTOR},
  65. {"irq", ARM9TDMI_IRQ_VECTOR},
  66. {"fiq", ARM9TDMI_FIQ_VECTOR},
  67. {0, 0},
  68. };
  69. int arm9tdmi_examine_debug_reason(struct target *target)
  70. {
  71. int retval = ERROR_OK;
  72. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  73. /* only check the debug reason if we don't know it already */
  74. if ((target->debug_reason != DBG_REASON_DBGRQ)
  75. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  76. {
  77. struct scan_field fields[3];
  78. uint8_t databus[4];
  79. uint8_t instructionbus[4];
  80. uint8_t debug_reason;
  81. jtag_set_end_state(TAP_DRPAUSE);
  82. fields[0].tap = arm7_9->jtag_info.tap;
  83. fields[0].num_bits = 32;
  84. fields[0].out_value = NULL;
  85. fields[0].in_value = databus;
  86. fields[1].tap = arm7_9->jtag_info.tap;
  87. fields[1].num_bits = 3;
  88. fields[1].out_value = NULL;
  89. fields[1].in_value = &debug_reason;
  90. fields[2].tap = arm7_9->jtag_info.tap;
  91. fields[2].num_bits = 32;
  92. fields[2].out_value = NULL;
  93. fields[2].in_value = instructionbus;
  94. if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
  95. {
  96. return retval;
  97. }
  98. arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
  99. jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
  100. if ((retval = jtag_execute_queue()) != ERROR_OK)
  101. {
  102. return retval;
  103. }
  104. fields[0].in_value = NULL;
  105. fields[0].out_value = databus;
  106. fields[1].in_value = NULL;
  107. fields[1].out_value = &debug_reason;
  108. fields[2].in_value = NULL;
  109. fields[2].out_value = instructionbus;
  110. jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
  111. if (debug_reason & 0x4)
  112. if (debug_reason & 0x2)
  113. target->debug_reason = DBG_REASON_WPTANDBKPT;
  114. else
  115. target->debug_reason = DBG_REASON_WATCHPOINT;
  116. else
  117. target->debug_reason = DBG_REASON_BREAKPOINT;
  118. }
  119. return ERROR_OK;
  120. }
  121. /* put an instruction in the ARM9TDMI pipeline or write the data bus,
  122. * and optionally read data
  123. */
  124. int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
  125. uint32_t out, uint32_t *in, int sysspeed)
  126. {
  127. int retval = ERROR_OK;
  128. struct scan_field fields[3];
  129. uint8_t out_buf[4];
  130. uint8_t instr_buf[4];
  131. uint8_t sysspeed_buf = 0x0;
  132. /* prepare buffer */
  133. buf_set_u32(out_buf, 0, 32, out);
  134. buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
  135. if (sysspeed)
  136. buf_set_u32(&sysspeed_buf, 2, 1, 1);
  137. jtag_set_end_state(TAP_DRPAUSE);
  138. if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
  139. {
  140. return retval;
  141. }
  142. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  143. fields[0].tap = jtag_info->tap;
  144. fields[0].num_bits = 32;
  145. fields[0].out_value = out_buf;
  146. fields[0].in_value = NULL;
  147. fields[1].tap = jtag_info->tap;
  148. fields[1].num_bits = 3;
  149. fields[1].out_value = &sysspeed_buf;
  150. fields[1].in_value = NULL;
  151. fields[2].tap = jtag_info->tap;
  152. fields[2].num_bits = 32;
  153. fields[2].out_value = instr_buf;
  154. fields[2].in_value = NULL;
  155. if (in)
  156. {
  157. fields[0].in_value = (uint8_t *)in;
  158. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  159. jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
  160. }
  161. else
  162. {
  163. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  164. }
  165. jtag_add_runtest(0, jtag_get_end_state());
  166. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  167. {
  168. if ((retval = jtag_execute_queue()) != ERROR_OK)
  169. {
  170. return retval;
  171. }
  172. if (in)
  173. {
  174. LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
  175. }
  176. else
  177. LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
  178. }
  179. #endif
  180. return ERROR_OK;
  181. }
  182. /* just read data (instruction and data-out = don't care) */
  183. int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
  184. {
  185. int retval = ERROR_OK;;
  186. struct scan_field fields[3];
  187. jtag_set_end_state(TAP_DRPAUSE);
  188. if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
  189. {
  190. return retval;
  191. }
  192. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  193. fields[0].tap = jtag_info->tap;
  194. fields[0].num_bits = 32;
  195. fields[0].out_value = NULL;
  196. fields[0].in_value = (uint8_t *)in;
  197. fields[1].tap = jtag_info->tap;
  198. fields[1].num_bits = 3;
  199. fields[1].out_value = NULL;
  200. fields[1].in_value = NULL;
  201. fields[2].tap = jtag_info->tap;
  202. fields[2].num_bits = 32;
  203. fields[2].out_value = NULL;
  204. fields[2].in_value = NULL;
  205. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  206. jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
  207. jtag_add_runtest(0, jtag_get_end_state());
  208. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  209. {
  210. if ((retval = jtag_execute_queue()) != ERROR_OK)
  211. {
  212. return retval;
  213. }
  214. if (in)
  215. {
  216. LOG_DEBUG("in: 0x%8.8x", *in);
  217. }
  218. else
  219. {
  220. LOG_ERROR("BUG: called with in == NULL");
  221. }
  222. }
  223. #endif
  224. return ERROR_OK;
  225. }
  226. static int arm9endianness(jtag_callback_data_t arg,
  227. jtag_callback_data_t size, jtag_callback_data_t be,
  228. jtag_callback_data_t captured)
  229. {
  230. uint8_t *in = (uint8_t *)arg;
  231. arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0);
  232. return ERROR_OK;
  233. }
  234. /* clock the target, and read the databus
  235. * the *in pointer points to a buffer where elements of 'size' bytes
  236. * are stored in big (be == 1) or little (be == 0) endianness
  237. */
  238. int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
  239. void *in, int size, int be)
  240. {
  241. int retval = ERROR_OK;
  242. struct scan_field fields[3];
  243. jtag_set_end_state(TAP_DRPAUSE);
  244. if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
  245. {
  246. return retval;
  247. }
  248. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  249. fields[0].tap = jtag_info->tap;
  250. fields[0].num_bits = 32;
  251. fields[0].out_value = NULL;
  252. jtag_alloc_in_value32(&fields[0]);
  253. fields[1].tap = jtag_info->tap;
  254. fields[1].num_bits = 3;
  255. fields[1].out_value = NULL;
  256. fields[1].in_value = NULL;
  257. fields[2].tap = jtag_info->tap;
  258. fields[2].num_bits = 32;
  259. fields[2].out_value = NULL;
  260. fields[2].in_value = NULL;
  261. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  262. jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
  263. jtag_add_runtest(0, jtag_get_end_state());
  264. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  265. {
  266. if ((retval = jtag_execute_queue()) != ERROR_OK)
  267. {
  268. return retval;
  269. }
  270. if (in)
  271. {
  272. LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
  273. }
  274. else
  275. {
  276. LOG_ERROR("BUG: called with in == NULL");
  277. }
  278. }
  279. #endif
  280. return ERROR_OK;
  281. }
  282. static void arm9tdmi_change_to_arm(struct target *target,
  283. uint32_t *r0, uint32_t *pc)
  284. {
  285. int retval = ERROR_OK;
  286. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  287. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  288. /* save r0 before using it and put system in ARM state
  289. * to allow common handling of ARM and THUMB debugging */
  290. /* fetch STR r0, [r0] */
  291. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
  292. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  293. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  294. /* STR r0, [r0] in Memory */
  295. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
  296. /* MOV r0, r15 fetched, STR in Decode */
  297. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
  298. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  299. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
  300. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  301. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  302. /* nothing fetched, STR r0, [r0] in Memory */
  303. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
  304. /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
  305. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
  306. /* LDR in Decode */
  307. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  308. /* LDR in Execute */
  309. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  310. /* LDR in Memory (to account for interlock) */
  311. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  312. /* fetch BX */
  313. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
  314. /* NOP fetched, BX in Decode, MOV in Execute */
  315. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  316. /* NOP fetched, BX in Execute (1) */
  317. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  318. if ((retval = jtag_execute_queue()) != ERROR_OK)
  319. {
  320. return;
  321. }
  322. /* fix program counter:
  323. * MOV r0, r15 was the 5th instruction (+8)
  324. * reading PC in Thumb state gives address of instruction + 4
  325. */
  326. *pc -= 0xc;
  327. }
  328. void arm9tdmi_read_core_regs(struct target *target,
  329. uint32_t mask, uint32_t* core_regs[16])
  330. {
  331. int i;
  332. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  333. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  334. /* STMIA r0-15, [r0] at debug speed
  335. * register values will start to appear on 4th DCLK
  336. */
  337. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  338. /* fetch NOP, STM in DECODE stage */
  339. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  340. /* fetch NOP, STM in EXECUTE stage (1st cycle) */
  341. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  342. for (i = 0; i <= 15; i++)
  343. {
  344. if (mask & (1 << i))
  345. /* nothing fetched, STM in MEMORY (i'th cycle) */
  346. arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
  347. }
  348. }
  349. static void arm9tdmi_read_core_regs_target_buffer(struct target *target,
  350. uint32_t mask, void* buffer, int size)
  351. {
  352. int i;
  353. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  354. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  355. int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
  356. uint32_t *buf_u32 = buffer;
  357. uint16_t *buf_u16 = buffer;
  358. uint8_t *buf_u8 = buffer;
  359. /* STMIA r0-15, [r0] at debug speed
  360. * register values will start to appear on 4th DCLK
  361. */
  362. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  363. /* fetch NOP, STM in DECODE stage */
  364. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  365. /* fetch NOP, STM in EXECUTE stage (1st cycle) */
  366. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  367. for (i = 0; i <= 15; i++)
  368. {
  369. if (mask & (1 << i))
  370. /* nothing fetched, STM in MEMORY (i'th cycle) */
  371. switch (size)
  372. {
  373. case 4:
  374. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
  375. break;
  376. case 2:
  377. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
  378. break;
  379. case 1:
  380. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
  381. break;
  382. }
  383. }
  384. }
  385. static void arm9tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
  386. {
  387. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  388. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  389. /* MRS r0, cpsr */
  390. arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
  391. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  392. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  393. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  394. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  395. /* STR r0, [r15] */
  396. arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
  397. /* fetch NOP, STR in DECODE stage */
  398. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  399. /* fetch NOP, STR in EXECUTE stage (1st cycle) */
  400. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  401. /* nothing fetched, STR in MEMORY */
  402. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
  403. }
  404. static void arm9tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
  405. {
  406. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  407. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  408. LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
  409. /* MSR1 fetched */
  410. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
  411. /* MSR2 fetched, MSR1 in DECODE */
  412. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
  413. /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
  414. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
  415. /* nothing fetched, MSR1 in EXECUTE (2) */
  416. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  417. /* nothing fetched, MSR1 in EXECUTE (3) */
  418. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  419. /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
  420. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
  421. /* nothing fetched, MSR2 in EXECUTE (2) */
  422. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  423. /* nothing fetched, MSR2 in EXECUTE (3) */
  424. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  425. /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
  426. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  427. /* nothing fetched, MSR3 in EXECUTE (2) */
  428. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  429. /* nothing fetched, MSR3 in EXECUTE (3) */
  430. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  431. /* NOP fetched, MSR4 in EXECUTE (1) */
  432. /* last MSR writes flags, which takes only one cycle */
  433. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  434. }
  435. static void arm9tdmi_write_xpsr_im8(struct target *target,
  436. uint8_t xpsr_im, int rot, int spsr)
  437. {
  438. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  439. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  440. LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
  441. /* MSR fetched */
  442. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
  443. /* NOP fetched, MSR in DECODE */
  444. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  445. /* NOP fetched, MSR in EXECUTE (1) */
  446. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  447. /* rot == 4 writes flags, which takes only one cycle */
  448. if (rot != 4)
  449. {
  450. /* nothing fetched, MSR in EXECUTE (2) */
  451. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  452. /* nothing fetched, MSR in EXECUTE (3) */
  453. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  454. }
  455. }
  456. void arm9tdmi_write_core_regs(struct target *target,
  457. uint32_t mask, uint32_t core_regs[16])
  458. {
  459. int i;
  460. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  461. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  462. /* LDMIA r0-15, [r0] at debug speed
  463. * register values will start to appear on 4th DCLK
  464. */
  465. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  466. /* fetch NOP, LDM in DECODE stage */
  467. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  468. /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
  469. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  470. for (i = 0; i <= 15; i++)
  471. {
  472. if (mask & (1 << i))
  473. /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
  474. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
  475. }
  476. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  477. }
  478. void arm9tdmi_load_word_regs(struct target *target, uint32_t mask)
  479. {
  480. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  481. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  482. /* put system-speed load-multiple into the pipeline */
  483. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
  484. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  485. }
  486. void arm9tdmi_load_hword_reg(struct target *target, int num)
  487. {
  488. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  489. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  490. /* put system-speed load half-word into the pipeline */
  491. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
  492. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  493. }
  494. void arm9tdmi_load_byte_reg(struct target *target, int num)
  495. {
  496. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  497. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  498. /* put system-speed load byte into the pipeline */
  499. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
  500. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  501. }
  502. void arm9tdmi_store_word_regs(struct target *target, uint32_t mask)
  503. {
  504. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  505. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  506. /* put system-speed store-multiple into the pipeline */
  507. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
  508. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  509. }
  510. void arm9tdmi_store_hword_reg(struct target *target, int num)
  511. {
  512. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  513. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  514. /* put system-speed store half-word into the pipeline */
  515. arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
  516. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  517. }
  518. void arm9tdmi_store_byte_reg(struct target *target, int num)
  519. {
  520. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  521. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  522. /* put system-speed store byte into the pipeline */
  523. arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
  524. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  525. }
  526. static void arm9tdmi_write_pc(struct target *target, uint32_t pc)
  527. {
  528. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  529. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  530. /* LDMIA r0-15, [r0] at debug speed
  531. * register values will start to appear on 4th DCLK
  532. */
  533. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
  534. /* fetch NOP, LDM in DECODE stage */
  535. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  536. /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
  537. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  538. /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
  539. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
  540. /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
  541. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  542. /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
  543. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  544. /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
  545. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  546. }
  547. void arm9tdmi_branch_resume(struct target *target)
  548. {
  549. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  550. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  551. arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
  552. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  553. }
  554. static void arm9tdmi_branch_resume_thumb(struct target *target)
  555. {
  556. LOG_DEBUG("-");
  557. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  558. struct arm *armv4_5 = &arm7_9->armv4_5_common;
  559. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  560. struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  561. /* LDMIA r0-15, [r0] at debug speed
  562. * register values will start to appear on 4th DCLK
  563. */
  564. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
  565. /* fetch NOP, LDM in DECODE stage */
  566. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  567. /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
  568. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  569. /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
  570. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
  571. /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
  572. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  573. /* Branch and eXchange */
  574. arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
  575. embeddedice_read_reg(dbg_stat);
  576. /* fetch NOP, BX in DECODE stage */
  577. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  578. embeddedice_read_reg(dbg_stat);
  579. /* fetch NOP, BX in EXECUTE stage (1st cycle) */
  580. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  581. /* target is now in Thumb state */
  582. embeddedice_read_reg(dbg_stat);
  583. /* load r0 value, MOV_IM in Decode*/
  584. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
  585. /* fetch NOP, LDR in Decode, MOV_IM in Execute */
  586. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  587. /* fetch NOP, LDR in Execute */
  588. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  589. /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
  590. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
  591. /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
  592. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  593. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  594. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  595. embeddedice_read_reg(dbg_stat);
  596. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
  597. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  598. }
  599. void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc)
  600. {
  601. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  602. if (arm7_9->has_single_step)
  603. {
  604. buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
  605. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
  606. }
  607. else
  608. {
  609. arm7_9_enable_eice_step(target, next_pc);
  610. }
  611. }
  612. void arm9tdmi_disable_single_step(struct target *target)
  613. {
  614. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  615. if (arm7_9->has_single_step)
  616. {
  617. buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
  618. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
  619. }
  620. else
  621. {
  622. arm7_9_disable_eice_step(target);
  623. }
  624. }
  625. static void arm9tdmi_build_reg_cache(struct target *target)
  626. {
  627. struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
  628. struct arm *armv4_5 = target_to_arm(target);
  629. (*cache_p) = arm_build_reg_cache(target, armv4_5);
  630. }
  631. int arm9tdmi_init_target(struct command_context *cmd_ctx,
  632. struct target *target)
  633. {
  634. arm9tdmi_build_reg_cache(target);
  635. return ERROR_OK;
  636. }
  637. int arm9tdmi_init_arch_info(struct target *target,
  638. struct arm7_9_common *arm7_9, struct jtag_tap *tap)
  639. {
  640. /* prepare JTAG information for the new target */
  641. arm7_9->jtag_info.tap = tap;
  642. arm7_9->jtag_info.scann_size = 5;
  643. /* register arch-specific functions */
  644. arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
  645. arm7_9->change_to_arm = arm9tdmi_change_to_arm;
  646. arm7_9->read_core_regs = arm9tdmi_read_core_regs;
  647. arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
  648. arm7_9->read_xpsr = arm9tdmi_read_xpsr;
  649. arm7_9->write_xpsr = arm9tdmi_write_xpsr;
  650. arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
  651. arm7_9->write_core_regs = arm9tdmi_write_core_regs;
  652. arm7_9->load_word_regs = arm9tdmi_load_word_regs;
  653. arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
  654. arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
  655. arm7_9->store_word_regs = arm9tdmi_store_word_regs;
  656. arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
  657. arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
  658. arm7_9->write_pc = arm9tdmi_write_pc;
  659. arm7_9->branch_resume = arm9tdmi_branch_resume;
  660. arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
  661. arm7_9->enable_single_step = arm9tdmi_enable_single_step;
  662. arm7_9->disable_single_step = arm9tdmi_disable_single_step;
  663. arm7_9->post_debug_entry = NULL;
  664. arm7_9->pre_restore_context = NULL;
  665. arm7_9->post_restore_context = NULL;
  666. /* initialize arch-specific breakpoint handling */
  667. arm7_9->arm_bkpt = 0xdeeedeee;
  668. arm7_9->thumb_bkpt = 0xdeee;
  669. arm7_9->dbgreq_adjust_pc = 3;
  670. arm7_9_init_arch_info(target, arm7_9);
  671. /* override use of DBGRQ, this is safe on ARM9TDMI */
  672. arm7_9->use_dbgrq = 1;
  673. /* all ARM9s have the vector catch register */
  674. arm7_9->has_vector_catch = 1;
  675. return ERROR_OK;
  676. }
  677. static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
  678. {
  679. struct arm7_9_common *arm7_9 = calloc(1,sizeof(struct arm7_9_common));
  680. arm9tdmi_init_arch_info(target, arm7_9, target->tap);
  681. arm7_9->armv4_5_common.is_armv4 = true;
  682. return ERROR_OK;
  683. }
  684. COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
  685. {
  686. struct target *target = get_current_target(CMD_CTX);
  687. struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  688. struct reg *vector_catch;
  689. uint32_t vector_catch_value;
  690. if (!target_was_examined(target))
  691. {
  692. LOG_ERROR("Target not examined yet");
  693. return ERROR_FAIL;
  694. }
  695. /* it's uncommon, but some ARM7 chips can support this */
  696. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC
  697. || !arm7_9->has_vector_catch) {
  698. command_print(CMD_CTX, "target doesn't have EmbeddedICE "
  699. "with vector_catch");
  700. return ERROR_TARGET_INVALID;
  701. }
  702. vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
  703. /* read the vector catch register if necessary */
  704. if (!vector_catch->valid)
  705. embeddedice_read_reg(vector_catch);
  706. /* get the current setting */
  707. vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
  708. if (CMD_ARGC > 0)
  709. {
  710. vector_catch_value = 0x0;
  711. if (strcmp(CMD_ARGV[0], "all") == 0)
  712. {
  713. vector_catch_value = 0xdf;
  714. }
  715. else if (strcmp(CMD_ARGV[0], "none") == 0)
  716. {
  717. /* do nothing */
  718. }
  719. else
  720. {
  721. for (unsigned i = 0; i < CMD_ARGC; i++)
  722. {
  723. /* go through list of vectors */
  724. unsigned j;
  725. for (j = 0; arm9tdmi_vectors[j].name; j++)
  726. {
  727. if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0)
  728. {
  729. vector_catch_value |= arm9tdmi_vectors[j].value;
  730. break;
  731. }
  732. }
  733. /* complain if vector wasn't found */
  734. if (!arm9tdmi_vectors[j].name)
  735. {
  736. command_print(CMD_CTX, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV[i]);
  737. /* reread current setting */
  738. vector_catch_value = buf_get_u32(
  739. vector_catch->value,
  740. 0, 8);
  741. break;
  742. }
  743. }
  744. }
  745. /* store new settings */
  746. buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
  747. embeddedice_store_reg(vector_catch);
  748. }
  749. /* output current settings */
  750. for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) {
  751. command_print(CMD_CTX, "%s: %s", arm9tdmi_vectors[i].name,
  752. (vector_catch_value & arm9tdmi_vectors[i].value)
  753. ? "catch" : "don't catch");
  754. }
  755. return ERROR_OK;
  756. }
  757. static const struct command_registration arm9tdmi_exec_command_handlers[] = {
  758. {
  759. .name = "vector_catch",
  760. .handler = handle_arm9tdmi_catch_vectors_command,
  761. .mode = COMMAND_EXEC,
  762. .help = "Display, after optionally updating, configuration "
  763. "of vector catch unit.",
  764. .usage = "[all|none|(reset|undef|swi|pabt|dabt|irq|fiq)*]",
  765. },
  766. COMMAND_REGISTRATION_DONE
  767. };
  768. const struct command_registration arm9tdmi_command_handlers[] = {
  769. {
  770. .chain = arm7_9_command_handlers,
  771. },
  772. {
  773. .name = "arm9tdmi",
  774. .mode = COMMAND_ANY,
  775. .help = "arm9tdmi command group",
  776. .chain = arm9tdmi_exec_command_handlers,
  777. },
  778. COMMAND_REGISTRATION_DONE
  779. };
  780. /** Holds methods for ARM9TDMI targets. */
  781. struct target_type arm9tdmi_target =
  782. {
  783. .name = "arm9tdmi",
  784. .poll = arm7_9_poll,
  785. .arch_state = arm_arch_state,
  786. .target_request_data = arm7_9_target_request_data,
  787. .halt = arm7_9_halt,
  788. .resume = arm7_9_resume,
  789. .step = arm7_9_step,
  790. .assert_reset = arm7_9_assert_reset,
  791. .deassert_reset = arm7_9_deassert_reset,
  792. .soft_reset_halt = arm7_9_soft_reset_halt,
  793. .get_gdb_reg_list = arm_get_gdb_reg_list,
  794. .read_memory = arm7_9_read_memory,
  795. .write_memory = arm7_9_write_memory,
  796. .bulk_write_memory = arm7_9_bulk_write_memory,
  797. .checksum_memory = arm_checksum_memory,
  798. .blank_check_memory = arm_blank_check_memory,
  799. .run_algorithm = armv4_5_run_algorithm,
  800. .add_breakpoint = arm7_9_add_breakpoint,
  801. .remove_breakpoint = arm7_9_remove_breakpoint,
  802. .add_watchpoint = arm7_9_add_watchpoint,
  803. .remove_watchpoint = arm7_9_remove_watchpoint,
  804. .commands = arm9tdmi_command_handlers,
  805. .target_create = arm9tdmi_target_create,
  806. .init_target = arm9tdmi_init_target,
  807. .examine = arm7_9_examine,
  808. };