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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2009 by Oyvind Harboe *
  9. * oyvind.harboe@zylin.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. /**
  27. * @file
  28. * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  29. * debugging architecture. Compared with previous versions, this includes
  30. * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  31. * transport, and focusses on memory mapped resources as defined by the
  32. * CoreSight architecture.
  33. *
  34. * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
  35. * basic components: a Debug Port (DP) transporting messages to and from a
  36. * debugger, and an Access Port (AP) accessing resources. Three types of DP
  37. * are defined. One uses only JTAG for communication, and is called JTAG-DP.
  38. * One uses only SWD for communication, and is called SW-DP. The third can
  39. * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
  40. * is used to access memory mapped resources and is called a MEM-AP. Also a
  41. * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  42. */
  43. /*
  44. * Relevant specifications from ARM include:
  45. *
  46. * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
  47. * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
  48. *
  49. * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  50. * Cortex-M3(tm) TRM, ARM DDI 0337G
  51. */
  52. #ifdef HAVE_CONFIG_H
  53. #include "config.h"
  54. #endif
  55. #include "arm_adi_v5.h"
  56. #include <helper/time_support.h>
  57. /*
  58. * Transaction Mode:
  59. * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  60. * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  61. * result checking until swjdp_end_transaction()
  62. * This must be done before using or deallocating any return variables.
  63. * swjdp->trans_mode == TRANS_MODE_ATOMIC
  64. * All reads and writes to the AHB bus are checked for valid completion, and return values
  65. * are immediatley available.
  66. */
  67. /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
  68. /*
  69. uint32_t tar_block_size(uint32_t address)
  70. Return the largest block starting at address that does not cross a tar block size alignment boundary
  71. */
  72. static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  73. {
  74. return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  75. }
  76. /***************************************************************************
  77. * *
  78. * DPACC and APACC scanchain access through JTAG-DP *
  79. * *
  80. ***************************************************************************/
  81. /* Scan out and in from target ordered uint8_t buffers */
  82. static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
  83. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  84. uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
  85. {
  86. struct arm_jtag *jtag_info = swjdp->jtag_info;
  87. struct scan_field fields[2];
  88. uint8_t out_addr_buf;
  89. jtag_set_end_state(TAP_IDLE);
  90. arm_jtag_set_instr(jtag_info, instr, NULL);
  91. /* Add specified number of tck clocks before accessing memory bus */
  92. /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
  93. * they provide more time for the (MEM) AP to complete the read ...
  94. */
  95. if ((instr == JTAG_DP_APACC)
  96. && ((reg_addr == AP_REG_DRW)
  97. || ((reg_addr & 0xF0) == AP_REG_BD0))
  98. && (swjdp->memaccess_tck != 0))
  99. jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
  100. fields[0].tap = jtag_info->tap;
  101. fields[0].num_bits = 3;
  102. buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  103. fields[0].out_value = &out_addr_buf;
  104. fields[0].in_value = ack;
  105. fields[1].tap = jtag_info->tap;
  106. fields[1].num_bits = 32;
  107. fields[1].out_value = outvalue;
  108. fields[1].in_value = invalue;
  109. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  110. return ERROR_OK;
  111. }
  112. /* Scan out and in from host ordered uint32_t variables */
  113. static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
  114. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  115. uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
  116. {
  117. struct arm_jtag *jtag_info = swjdp->jtag_info;
  118. struct scan_field fields[2];
  119. uint8_t out_value_buf[4];
  120. uint8_t out_addr_buf;
  121. jtag_set_end_state(TAP_IDLE);
  122. arm_jtag_set_instr(jtag_info, instr, NULL);
  123. /* Add specified number of tck clocks before accessing memory bus */
  124. /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
  125. * they provide more time for the (MEM) AP to complete the read ...
  126. */
  127. if ((instr == JTAG_DP_APACC)
  128. && ((reg_addr == AP_REG_DRW)
  129. || ((reg_addr & 0xF0) == AP_REG_BD0))
  130. && (swjdp->memaccess_tck != 0))
  131. jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
  132. fields[0].tap = jtag_info->tap;
  133. fields[0].num_bits = 3;
  134. buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  135. fields[0].out_value = &out_addr_buf;
  136. fields[0].in_value = ack;
  137. fields[1].tap = jtag_info->tap;
  138. fields[1].num_bits = 32;
  139. buf_set_u32(out_value_buf, 0, 32, outvalue);
  140. fields[1].out_value = out_value_buf;
  141. fields[1].in_value = NULL;
  142. if (invalue)
  143. {
  144. fields[1].in_value = (uint8_t *)invalue;
  145. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  146. jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
  147. } else
  148. {
  149. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  150. }
  151. return ERROR_OK;
  152. }
  153. /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
  154. static int scan_inout_check(struct swjdp_common *swjdp,
  155. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  156. uint8_t *outvalue, uint8_t *invalue)
  157. {
  158. adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
  159. if ((RnW == DPAP_READ) && (invalue != NULL))
  160. adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
  161. DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
  162. /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
  163. * ack = OK/FAULT and the check CTRL_STAT
  164. */
  165. if ((instr == JTAG_DP_APACC)
  166. && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
  167. return swjdp_transaction_endcheck(swjdp);
  168. return ERROR_OK;
  169. }
  170. static int scan_inout_check_u32(struct swjdp_common *swjdp,
  171. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  172. uint32_t outvalue, uint32_t *invalue)
  173. {
  174. /* Issue the read or write */
  175. adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
  176. /* For reads, collect posted value; RDBUFF has no other effect.
  177. * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
  178. */
  179. if ((RnW == DPAP_READ) && (invalue != NULL))
  180. adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
  181. DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
  182. /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
  183. * ack = OK/FAULT and then check CTRL_STAT
  184. */
  185. if ((instr == JTAG_DP_APACC)
  186. && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
  187. return swjdp_transaction_endcheck(swjdp);
  188. return ERROR_OK;
  189. }
  190. int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
  191. {
  192. int retval;
  193. uint32_t ctrlstat;
  194. /* too expensive to call keep_alive() here */
  195. #if 0
  196. /* Danger!!!! BROKEN!!!! */
  197. scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  198. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  199. /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
  200. R956 introduced the check on return value here and now Michael Schwingen reports
  201. that this code no longer works....
  202. https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
  203. */
  204. if ((retval = jtag_execute_queue()) != ERROR_OK)
  205. {
  206. LOG_ERROR("BUG: Why does this fail the first time????");
  207. }
  208. /* Why??? second time it works??? */
  209. #endif
  210. /* Post CTRL/STAT read; discard any previous posted read value
  211. * but collect its ACK status.
  212. */
  213. scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  214. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  215. if ((retval = jtag_execute_queue()) != ERROR_OK)
  216. return retval;
  217. swjdp->ack = swjdp->ack & 0x7;
  218. /* common code path avoids calling timeval_ms() */
  219. if (swjdp->ack != JTAG_ACK_OK_FAULT)
  220. {
  221. long long then = timeval_ms();
  222. while (swjdp->ack != JTAG_ACK_OK_FAULT)
  223. {
  224. if (swjdp->ack == JTAG_ACK_WAIT)
  225. {
  226. if ((timeval_ms()-then) > 1000)
  227. {
  228. /* NOTE: this would be a good spot
  229. * to use JTAG_DP_ABORT.
  230. */
  231. LOG_WARNING("Timeout (1000ms) waiting "
  232. "for ACK=OK/FAULT "
  233. "in JTAG-DP transaction");
  234. return ERROR_JTAG_DEVICE_ERROR;
  235. }
  236. }
  237. else
  238. {
  239. LOG_WARNING("Invalid ACK "
  240. "in JTAG-DP transaction");
  241. return ERROR_JTAG_DEVICE_ERROR;
  242. }
  243. scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  244. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  245. if ((retval = jtag_execute_queue()) != ERROR_OK)
  246. return retval;
  247. swjdp->ack = swjdp->ack & 0x7;
  248. }
  249. }
  250. /* Check for STICKYERR and STICKYORUN */
  251. if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
  252. {
  253. LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
  254. /* Check power to debug regions */
  255. if ((ctrlstat & 0xf0000000) != 0xf0000000)
  256. {
  257. ahbap_debugport_init(swjdp);
  258. }
  259. else
  260. {
  261. uint32_t mem_ap_csw, mem_ap_tar;
  262. /* Print information about last AHBAP access */
  263. LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
  264. if (ctrlstat & SSTICKYORUN)
  265. LOG_ERROR("JTAG-DP OVERRUN - "
  266. "check clock or reduce jtag speed");
  267. if (ctrlstat & SSTICKYERR)
  268. LOG_ERROR("JTAG-DP STICKY ERROR");
  269. /* Clear Sticky Error Bits */
  270. scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  271. DP_CTRL_STAT, DPAP_WRITE,
  272. swjdp->dp_ctrl_stat | SSTICKYORUN
  273. | SSTICKYERR, NULL);
  274. scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  275. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  276. if ((retval = jtag_execute_queue()) != ERROR_OK)
  277. return retval;
  278. LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
  279. dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
  280. dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
  281. if ((retval = jtag_execute_queue()) != ERROR_OK)
  282. return retval;
  283. LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
  284. }
  285. if ((retval = jtag_execute_queue()) != ERROR_OK)
  286. return retval;
  287. return ERROR_JTAG_DEVICE_ERROR;
  288. }
  289. return ERROR_OK;
  290. }
  291. /***************************************************************************
  292. * *
  293. * DP and MEM-AP register access through APACC and DPACC *
  294. * *
  295. ***************************************************************************/
  296. static int dap_dp_write_reg(struct swjdp_common *swjdp,
  297. uint32_t value, uint8_t reg_addr)
  298. {
  299. return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  300. reg_addr, DPAP_WRITE, value, NULL);
  301. }
  302. static int dap_dp_read_reg(struct swjdp_common *swjdp,
  303. uint32_t *value, uint8_t reg_addr)
  304. {
  305. return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
  306. reg_addr, DPAP_READ, 0, value);
  307. }
  308. int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
  309. {
  310. uint32_t select;
  311. select = (apsel << 24) & 0xFF000000;
  312. if (select != swjdp->apsel)
  313. {
  314. swjdp->apsel = select;
  315. /* Switching AP invalidates cached values */
  316. swjdp->dp_select_value = -1;
  317. swjdp->ap_csw_value = -1;
  318. swjdp->ap_tar_value = -1;
  319. }
  320. return ERROR_OK;
  321. }
  322. static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
  323. {
  324. uint32_t select;
  325. select = (ap_reg & 0x000000F0);
  326. if (select != swjdp->dp_select_value)
  327. {
  328. dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
  329. swjdp->dp_select_value = select;
  330. }
  331. return ERROR_OK;
  332. }
  333. static int dap_ap_write_reg(struct swjdp_common *swjdp,
  334. uint32_t reg_addr, uint8_t *out_value_buf)
  335. {
  336. dap_dp_bankselect(swjdp, reg_addr);
  337. scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
  338. DPAP_WRITE, out_value_buf, NULL);
  339. return ERROR_OK;
  340. }
  341. int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
  342. {
  343. uint8_t out_value_buf[4];
  344. buf_set_u32(out_value_buf, 0, 32, value);
  345. dap_dp_bankselect(swjdp, reg_addr);
  346. scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
  347. DPAP_WRITE, out_value_buf, NULL);
  348. return ERROR_OK;
  349. }
  350. int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
  351. {
  352. dap_dp_bankselect(swjdp, reg_addr);
  353. scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
  354. DPAP_READ, 0, value);
  355. return ERROR_OK;
  356. }
  357. /***************************************************************************
  358. * *
  359. * AHB-AP access to memory and system registers on AHB bus *
  360. * *
  361. ***************************************************************************/
  362. int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
  363. {
  364. csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
  365. if (csw != swjdp->ap_csw_value)
  366. {
  367. /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
  368. dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
  369. swjdp->ap_csw_value = csw;
  370. }
  371. if (tar != swjdp->ap_tar_value)
  372. {
  373. /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
  374. dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
  375. swjdp->ap_tar_value = tar;
  376. }
  377. if (csw & CSW_ADDRINC_MASK)
  378. {
  379. /* Do not cache TAR value when autoincrementing */
  380. swjdp->ap_tar_value = -1;
  381. }
  382. return ERROR_OK;
  383. }
  384. /*****************************************************************************
  385. * *
  386. * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
  387. * *
  388. * Read a uint32_t value from memory or system register *
  389. * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
  390. * but with less overhead *
  391. *****************************************************************************/
  392. int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
  393. {
  394. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  395. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
  396. dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
  397. return ERROR_OK;
  398. }
  399. int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
  400. {
  401. mem_ap_read_u32(swjdp, address, value);
  402. return swjdp_transaction_endcheck(swjdp);
  403. }
  404. /*****************************************************************************
  405. * *
  406. * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
  407. * *
  408. * Write a uint32_t value to memory or memory mapped register *
  409. * *
  410. *****************************************************************************/
  411. int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
  412. {
  413. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  414. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
  415. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
  416. return ERROR_OK;
  417. }
  418. int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
  419. {
  420. mem_ap_write_u32(swjdp, address, value);
  421. return swjdp_transaction_endcheck(swjdp);
  422. }
  423. /*****************************************************************************
  424. * *
  425. * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
  426. * *
  427. * Write a buffer in target order (little endian) *
  428. * *
  429. *****************************************************************************/
  430. int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
  431. {
  432. int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
  433. uint32_t adr = address;
  434. uint8_t* pBuffer = buffer;
  435. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  436. count >>= 2;
  437. wcount = count;
  438. /* if we have an unaligned access - reorder data */
  439. if (adr & 0x3u)
  440. {
  441. for (writecount = 0; writecount < count; writecount++)
  442. {
  443. int i;
  444. uint32_t outvalue;
  445. memcpy(&outvalue, pBuffer, sizeof(uint32_t));
  446. for (i = 0; i < 4; i++)
  447. {
  448. *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
  449. outvalue >>= 8;
  450. adr++;
  451. }
  452. pBuffer += sizeof(uint32_t);
  453. }
  454. }
  455. while (wcount > 0)
  456. {
  457. /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
  458. blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
  459. if (wcount < blocksize)
  460. blocksize = wcount;
  461. /* handle unaligned data at 4k boundary */
  462. if (blocksize == 0)
  463. blocksize = 1;
  464. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
  465. for (writecount = 0; writecount < blocksize; writecount++)
  466. {
  467. dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
  468. }
  469. if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
  470. {
  471. wcount = wcount - blocksize;
  472. address = address + 4 * blocksize;
  473. buffer = buffer + 4 * blocksize;
  474. }
  475. else
  476. {
  477. errorcount++;
  478. }
  479. if (errorcount > 1)
  480. {
  481. LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
  482. return ERROR_JTAG_DEVICE_ERROR;
  483. }
  484. }
  485. return retval;
  486. }
  487. static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
  488. uint8_t *buffer, int count, uint32_t address)
  489. {
  490. int retval = ERROR_OK;
  491. int wcount, blocksize, writecount, i;
  492. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  493. wcount = count >> 1;
  494. while (wcount > 0)
  495. {
  496. int nbytes;
  497. /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
  498. blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
  499. if (wcount < blocksize)
  500. blocksize = wcount;
  501. /* handle unaligned data at 4k boundary */
  502. if (blocksize == 0)
  503. blocksize = 1;
  504. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
  505. writecount = blocksize;
  506. do
  507. {
  508. nbytes = MIN((writecount << 1), 4);
  509. if (nbytes < 4)
  510. {
  511. if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
  512. {
  513. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  514. return ERROR_JTAG_DEVICE_ERROR;
  515. }
  516. address += nbytes >> 1;
  517. }
  518. else
  519. {
  520. uint32_t outvalue;
  521. memcpy(&outvalue, buffer, sizeof(uint32_t));
  522. for (i = 0; i < nbytes; i++)
  523. {
  524. *((uint8_t*)buffer + (address & 0x3)) = outvalue;
  525. outvalue >>= 8;
  526. address++;
  527. }
  528. memcpy(&outvalue, buffer, sizeof(uint32_t));
  529. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
  530. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  531. {
  532. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  533. return ERROR_JTAG_DEVICE_ERROR;
  534. }
  535. }
  536. buffer += nbytes >> 1;
  537. writecount -= nbytes >> 1;
  538. } while (writecount);
  539. wcount -= blocksize;
  540. }
  541. return retval;
  542. }
  543. int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
  544. {
  545. int retval = ERROR_OK;
  546. if (count >= 4)
  547. return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
  548. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  549. while (count > 0)
  550. {
  551. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
  552. uint16_t svalue;
  553. memcpy(&svalue, buffer, sizeof(uint16_t));
  554. uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
  555. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
  556. retval = swjdp_transaction_endcheck(swjdp);
  557. count -= 2;
  558. address += 2;
  559. buffer += 2;
  560. }
  561. return retval;
  562. }
  563. static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
  564. uint8_t *buffer, int count, uint32_t address)
  565. {
  566. int retval = ERROR_OK;
  567. int wcount, blocksize, writecount, i;
  568. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  569. wcount = count;
  570. while (wcount > 0)
  571. {
  572. int nbytes;
  573. /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
  574. blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
  575. if (wcount < blocksize)
  576. blocksize = wcount;
  577. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
  578. writecount = blocksize;
  579. do
  580. {
  581. nbytes = MIN(writecount, 4);
  582. if (nbytes < 4)
  583. {
  584. if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
  585. {
  586. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  587. return ERROR_JTAG_DEVICE_ERROR;
  588. }
  589. address += nbytes;
  590. }
  591. else
  592. {
  593. uint32_t outvalue;
  594. memcpy(&outvalue, buffer, sizeof(uint32_t));
  595. for (i = 0; i < nbytes; i++)
  596. {
  597. *((uint8_t*)buffer + (address & 0x3)) = outvalue;
  598. outvalue >>= 8;
  599. address++;
  600. }
  601. memcpy(&outvalue, buffer, sizeof(uint32_t));
  602. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
  603. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  604. {
  605. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  606. return ERROR_JTAG_DEVICE_ERROR;
  607. }
  608. }
  609. buffer += nbytes;
  610. writecount -= nbytes;
  611. } while (writecount);
  612. wcount -= blocksize;
  613. }
  614. return retval;
  615. }
  616. int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
  617. {
  618. int retval = ERROR_OK;
  619. if (count >= 4)
  620. return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
  621. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  622. while (count > 0)
  623. {
  624. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
  625. uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
  626. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
  627. retval = swjdp_transaction_endcheck(swjdp);
  628. count--;
  629. address++;
  630. buffer++;
  631. }
  632. return retval;
  633. }
  634. /*********************************************************************************
  635. * *
  636. * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
  637. * *
  638. * Read block fast in target order (little endian) into a buffer *
  639. * *
  640. **********************************************************************************/
  641. int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
  642. {
  643. int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
  644. uint32_t adr = address;
  645. uint8_t* pBuffer = buffer;
  646. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  647. count >>= 2;
  648. wcount = count;
  649. while (wcount > 0)
  650. {
  651. /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
  652. blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
  653. if (wcount < blocksize)
  654. blocksize = wcount;
  655. /* handle unaligned data at 4k boundary */
  656. if (blocksize == 0)
  657. blocksize = 1;
  658. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
  659. /* Scan out first read */
  660. adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
  661. DPAP_READ, 0, NULL, NULL);
  662. for (readcount = 0; readcount < blocksize - 1; readcount++)
  663. {
  664. /* Scan out next read; scan in posted value for the
  665. * previous one. Assumes read is acked "OK/FAULT",
  666. * and CTRL_STAT says that meant "OK".
  667. */
  668. adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
  669. DPAP_READ, 0, buffer + 4 * readcount,
  670. &swjdp->ack);
  671. }
  672. /* Scan in last posted value; RDBUFF has no other effect,
  673. * assuming ack is OK/FAULT and CTRL_STAT says "OK".
  674. */
  675. adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
  676. DPAP_READ, 0, buffer + 4 * readcount,
  677. &swjdp->ack);
  678. if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
  679. {
  680. wcount = wcount - blocksize;
  681. address += 4 * blocksize;
  682. buffer += 4 * blocksize;
  683. }
  684. else
  685. {
  686. errorcount++;
  687. }
  688. if (errorcount > 1)
  689. {
  690. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  691. return ERROR_JTAG_DEVICE_ERROR;
  692. }
  693. }
  694. /* if we have an unaligned access - reorder data */
  695. if (adr & 0x3u)
  696. {
  697. for (readcount = 0; readcount < count; readcount++)
  698. {
  699. int i;
  700. uint32_t data;
  701. memcpy(&data, pBuffer, sizeof(uint32_t));
  702. for (i = 0; i < 4; i++)
  703. {
  704. *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
  705. pBuffer++;
  706. adr++;
  707. }
  708. }
  709. }
  710. return retval;
  711. }
  712. static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
  713. uint8_t *buffer, int count, uint32_t address)
  714. {
  715. uint32_t invalue;
  716. int retval = ERROR_OK;
  717. int wcount, blocksize, readcount, i;
  718. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  719. wcount = count >> 1;
  720. while (wcount > 0)
  721. {
  722. int nbytes;
  723. /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
  724. blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
  725. if (wcount < blocksize)
  726. blocksize = wcount;
  727. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
  728. /* handle unaligned data at 4k boundary */
  729. if (blocksize == 0)
  730. blocksize = 1;
  731. readcount = blocksize;
  732. do
  733. {
  734. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
  735. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  736. {
  737. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  738. return ERROR_JTAG_DEVICE_ERROR;
  739. }
  740. nbytes = MIN((readcount << 1), 4);
  741. for (i = 0; i < nbytes; i++)
  742. {
  743. *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
  744. buffer++;
  745. address++;
  746. }
  747. readcount -= (nbytes >> 1);
  748. } while (readcount);
  749. wcount -= blocksize;
  750. }
  751. return retval;
  752. }
  753. int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
  754. {
  755. uint32_t invalue, i;
  756. int retval = ERROR_OK;
  757. if (count >= 4)
  758. return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
  759. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  760. while (count > 0)
  761. {
  762. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
  763. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
  764. retval = swjdp_transaction_endcheck(swjdp);
  765. if (address & 0x1)
  766. {
  767. for (i = 0; i < 2; i++)
  768. {
  769. *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
  770. buffer++;
  771. address++;
  772. }
  773. }
  774. else
  775. {
  776. uint16_t svalue = (invalue >> 8 * (address & 0x3));
  777. memcpy(buffer, &svalue, sizeof(uint16_t));
  778. address += 2;
  779. buffer += 2;
  780. }
  781. count -= 2;
  782. }
  783. return retval;
  784. }
  785. /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
  786. * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
  787. *
  788. * The solution is to arrange for a large out/in scan in this loop and
  789. * and convert data afterwards.
  790. */
  791. static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
  792. uint8_t *buffer, int count, uint32_t address)
  793. {
  794. uint32_t invalue;
  795. int retval = ERROR_OK;
  796. int wcount, blocksize, readcount, i;
  797. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  798. wcount = count;
  799. while (wcount > 0)
  800. {
  801. int nbytes;
  802. /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
  803. blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
  804. if (wcount < blocksize)
  805. blocksize = wcount;
  806. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
  807. readcount = blocksize;
  808. do
  809. {
  810. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
  811. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  812. {
  813. LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
  814. return ERROR_JTAG_DEVICE_ERROR;
  815. }
  816. nbytes = MIN(readcount, 4);
  817. for (i = 0; i < nbytes; i++)
  818. {
  819. *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
  820. buffer++;
  821. address++;
  822. }
  823. readcount -= nbytes;
  824. } while (readcount);
  825. wcount -= blocksize;
  826. }
  827. return retval;
  828. }
  829. int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
  830. {
  831. uint32_t invalue;
  832. int retval = ERROR_OK;
  833. if (count >= 4)
  834. return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
  835. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  836. while (count > 0)
  837. {
  838. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
  839. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
  840. retval = swjdp_transaction_endcheck(swjdp);
  841. *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
  842. count--;
  843. address++;
  844. buffer++;
  845. }
  846. return retval;
  847. }
  848. /**
  849. * Initialize a DAP.
  850. *
  851. * @todo Rename this. We also need an initialization scheme which account
  852. * for SWD transports not just JTAG; that will need to address differences
  853. * in layering. (JTAG is useful without any debug target; but not SWD.)
  854. */
  855. int ahbap_debugport_init(struct swjdp_common *swjdp)
  856. {
  857. uint32_t idreg, romaddr, dummy;
  858. uint32_t ctrlstat;
  859. int cnt = 0;
  860. int retval;
  861. LOG_DEBUG(" ");
  862. /* Default MEM-AP setup.
  863. *
  864. * REVISIT AP #0 may be an inappropriate default for this.
  865. * Should we probe, or receve a hint from the caller?
  866. * Presumably we can ignore the possibility of multiple APs.
  867. */
  868. swjdp->apsel = 0;
  869. swjdp->ap_csw_value = -1;
  870. swjdp->ap_tar_value = -1;
  871. /* DP initialization */
  872. swjdp->trans_mode = TRANS_MODE_ATOMIC;
  873. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  874. dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
  875. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  876. swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
  877. dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
  878. dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
  879. if ((retval = jtag_execute_queue()) != ERROR_OK)
  880. return retval;
  881. /* Check that we have debug power domains activated */
  882. while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
  883. {
  884. LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
  885. dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
  886. if ((retval = jtag_execute_queue()) != ERROR_OK)
  887. return retval;
  888. alive_sleep(10);
  889. }
  890. while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
  891. {
  892. LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
  893. dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
  894. if ((retval = jtag_execute_queue()) != ERROR_OK)
  895. return retval;
  896. alive_sleep(10);
  897. }
  898. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  899. /* With debug power on we can activate OVERRUN checking */
  900. swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
  901. dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
  902. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  903. /*
  904. * REVISIT this isn't actually *initializing* anything in an AP,
  905. * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
  906. * Should it? If the ROM address is valid, is this the right
  907. * place to scan the table and do any topology detection?
  908. */
  909. dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
  910. dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
  911. LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
  912. return ERROR_OK;
  913. }
  914. /* CID interpretation -- see ARM IHI 0029B section 3
  915. * and ARM IHI 0031A table 13-3.
  916. */
  917. static const char *class_description[16] ={
  918. "Reserved", "ROM table", "Reserved", "Reserved",
  919. "Reserved", "Reserved", "Reserved", "Reserved",
  920. "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
  921. "Reserved", "OptimoDE DESS",
  922. "Generic IP component", "PrimeCell or System component"
  923. };
  924. static bool
  925. is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
  926. {
  927. return cid3 == 0xb1 && cid2 == 0x05
  928. && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
  929. }
  930. int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
  931. {
  932. uint32_t dbgbase, apid;
  933. int romtable_present = 0;
  934. uint8_t mem_ap;
  935. uint32_t apselold;
  936. apselold = swjdp->apsel;
  937. dap_ap_select(swjdp, apsel);
  938. dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
  939. dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
  940. swjdp_transaction_endcheck(swjdp);
  941. /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
  942. mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
  943. command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
  944. if (apid)
  945. {
  946. switch (apid&0x0F)
  947. {
  948. case 0:
  949. command_print(cmd_ctx, "\tType is JTAG-AP");
  950. break;
  951. case 1:
  952. command_print(cmd_ctx, "\tType is MEM-AP AHB");
  953. break;
  954. case 2:
  955. command_print(cmd_ctx, "\tType is MEM-AP APB");
  956. break;
  957. default:
  958. command_print(cmd_ctx, "\tUnknown AP type");
  959. break;
  960. }
  961. /* NOTE: a MEM-AP may have a single CoreSight component that's
  962. * not a ROM table ... or have no such components at all.
  963. */
  964. if (mem_ap)
  965. command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
  966. dbgbase);
  967. }
  968. else
  969. {
  970. command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
  971. }
  972. romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
  973. if (romtable_present)
  974. {
  975. uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
  976. uint16_t entry_offset;
  977. /* bit 16 of apid indicates a memory access port */
  978. if (dbgbase & 0x02)
  979. command_print(cmd_ctx, "\tValid ROM table present");
  980. else
  981. command_print(cmd_ctx, "\tROM table in legacy format");
  982. /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
  983. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
  984. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
  985. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
  986. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
  987. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
  988. swjdp_transaction_endcheck(swjdp);
  989. if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
  990. command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
  991. ", CID2 0x%2.2" PRIx32
  992. ", CID1 0x%2.2" PRIx32
  993. ", CID0 0x%2.2" PRIx32,
  994. cid3, cid2, cid1, cid0);
  995. if (memtype & 0x01)
  996. command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
  997. else
  998. command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
  999. "Dedicated debug bus.");
  1000. /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
  1001. entry_offset = 0;
  1002. do
  1003. {
  1004. mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
  1005. command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
  1006. if (romentry&0x01)
  1007. {
  1008. uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
  1009. uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
  1010. uint32_t component_start, component_base;
  1011. unsigned part_num;
  1012. char *type, *full;
  1013. component_base = (uint32_t)((dbgbase & 0xFFFFF000)
  1014. + (int)(romentry & 0xFFFFF000));
  1015. mem_ap_read_atomic_u32(swjdp,
  1016. (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
  1017. mem_ap_read_atomic_u32(swjdp,
  1018. (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
  1019. mem_ap_read_atomic_u32(swjdp,
  1020. (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
  1021. mem_ap_read_atomic_u32(swjdp,
  1022. (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
  1023. mem_ap_read_atomic_u32(swjdp,
  1024. (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
  1025. mem_ap_read_atomic_u32(swjdp,
  1026. (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
  1027. mem_ap_read_atomic_u32(swjdp,
  1028. (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
  1029. mem_ap_read_atomic_u32(swjdp,
  1030. (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
  1031. mem_ap_read_atomic_u32(swjdp,
  1032. (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
  1033. component_start = component_base - 0x1000*(c_pid4 >> 4);
  1034. command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
  1035. ", start address 0x%" PRIx32,
  1036. component_base, component_start);
  1037. command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
  1038. (int) (c_cid1 >> 4) & 0xf,
  1039. /* See ARM IHI 0029B Table 3-3 */
  1040. class_description[(c_cid1 >> 4) & 0xf]);
  1041. /* CoreSight component? */
  1042. if (((c_cid1 >> 4) & 0x0f) == 9) {
  1043. uint32_t devtype;
  1044. unsigned minor;
  1045. char *major = "Reserved", *subtype = "Reserved";
  1046. mem_ap_read_atomic_u32(swjdp,
  1047. (component_base & 0xfffff000) | 0xfcc,
  1048. &devtype);
  1049. minor = (devtype >> 4) & 0x0f;
  1050. switch (devtype & 0x0f) {
  1051. case 0:
  1052. major = "Miscellaneous";
  1053. switch (minor) {
  1054. case 0:
  1055. subtype = "other";
  1056. break;
  1057. case 4:
  1058. subtype = "Validation component";
  1059. break;
  1060. }
  1061. break;
  1062. case 1:
  1063. major = "Trace Sink";
  1064. switch (minor) {
  1065. case 0:
  1066. subtype = "other";
  1067. break;
  1068. case 1:
  1069. subtype = "Port";
  1070. break;
  1071. case 2:
  1072. subtype = "Buffer";
  1073. break;
  1074. }
  1075. break;
  1076. case 2:
  1077. major = "Trace Link";
  1078. switch (minor) {
  1079. case 0:
  1080. subtype = "other";
  1081. break;
  1082. case 1:
  1083. subtype = "Funnel, router";
  1084. break;
  1085. case 2:
  1086. subtype = "Filter";
  1087. break;
  1088. case 3:
  1089. subtype = "FIFO, buffer";
  1090. break;
  1091. }
  1092. break;
  1093. case 3:
  1094. major = "Trace Source";
  1095. switch (minor) {
  1096. case 0:
  1097. subtype = "other";
  1098. break;
  1099. case 1:
  1100. subtype = "Processor";
  1101. break;
  1102. case 2:
  1103. subtype = "DSP";
  1104. break;
  1105. case 3:
  1106. subtype = "Engine/Coprocessor";
  1107. break;
  1108. case 4:
  1109. subtype = "Bus";
  1110. break;
  1111. }
  1112. break;
  1113. case 4:
  1114. major = "Debug Control";
  1115. switch (minor) {
  1116. case 0:
  1117. subtype = "other";
  1118. break;
  1119. case 1:
  1120. subtype = "Trigger Matrix";
  1121. break;
  1122. case 2:
  1123. subtype = "Debug Auth";
  1124. break;
  1125. }
  1126. break;
  1127. case 5:
  1128. major = "Debug Logic";
  1129. switch (minor) {
  1130. case 0:
  1131. subtype = "other";
  1132. break;
  1133. case 1:
  1134. subtype = "Processor";
  1135. break;
  1136. case 2:
  1137. subtype = "DSP";
  1138. break;
  1139. case 3:
  1140. subtype = "Engine/Coprocessor";
  1141. break;
  1142. }
  1143. break;
  1144. }
  1145. command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
  1146. (unsigned) (devtype & 0xff),
  1147. major, subtype);
  1148. /* REVISIT also show 0xfc8 DevId */
  1149. }
  1150. if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
  1151. command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
  1152. ", CID2 0x%2.2" PRIx32
  1153. ", CID1 0x%2.2" PRIx32
  1154. ", CID0 0x%2.2" PRIx32,
  1155. c_cid3, c_cid2, c_cid1, c_cid0);
  1156. command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
  1157. "%2.2x %2.2x %2.2x %2.2x %2.2x",
  1158. (int) c_pid4,
  1159. (int) c_pid3, (int) c_pid2,
  1160. (int) c_pid1, (int) c_pid0);
  1161. /* Part number interpretations are from Cortex
  1162. * core specs, the CoreSight components TRM
  1163. * (ARM DDI 0314H), and ETM specs; also from
  1164. * chip observation (e.g. TI SDTI).
  1165. */
  1166. part_num = c_pid0 & 0xff;
  1167. part_num |= (c_pid1 & 0x0f) << 8;
  1168. switch (part_num) {
  1169. case 0x000:
  1170. type = "Cortex-M3 NVIC";
  1171. full = "(Interrupt Controller)";
  1172. break;
  1173. case 0x001:
  1174. type = "Cortex-M3 ITM";
  1175. full = "(Instrumentation Trace Module)";
  1176. break;
  1177. case 0x002:
  1178. type = "Cortex-M3 DWT";
  1179. full = "(Data Watchpoint and Trace)";
  1180. break;
  1181. case 0x003:
  1182. type = "Cortex-M3 FBP";
  1183. full = "(Flash Patch and Breakpoint)";
  1184. break;
  1185. case 0x00d:
  1186. type = "CoreSight ETM11";
  1187. full = "(Embedded Trace)";
  1188. break;
  1189. // case 0x113: what?
  1190. case 0x120: /* from OMAP3 memmap */
  1191. type = "TI SDTI";
  1192. full = "(System Debug Trace Interface)";
  1193. break;
  1194. case 0x343: /* from OMAP3 memmap */
  1195. type = "TI DAPCTL";
  1196. full = "";
  1197. break;
  1198. case 0x4e0:
  1199. type = "Cortex-M3 ETM";
  1200. full = "(Embedded Trace)";
  1201. break;
  1202. case 0x906:
  1203. type = "Coresight CTI";
  1204. full = "(Cross Trigger)";
  1205. break;
  1206. case 0x907:
  1207. type = "Coresight ETB";
  1208. full = "(Trace Buffer)";
  1209. break;
  1210. case 0x908:
  1211. type = "Coresight CSTF";
  1212. full = "(Trace Funnel)";
  1213. break;
  1214. case 0x910:
  1215. type = "CoreSight ETM9";
  1216. full = "(Embedded Trace)";
  1217. break;
  1218. case 0x912:
  1219. type = "Coresight TPIU";
  1220. full = "(Trace Port Interface Unit)";
  1221. break;
  1222. case 0x921:
  1223. type = "Cortex-A8 ETM";
  1224. full = "(Embedded Trace)";
  1225. break;
  1226. case 0x922:
  1227. type = "Cortex-A8 CTI";
  1228. full = "(Cross Trigger)";
  1229. break;
  1230. case 0x923:
  1231. type = "Cortex-M3 TPIU";
  1232. full = "(Trace Port Interface Unit)";
  1233. break;
  1234. case 0xc08:
  1235. type = "Cortex-A8 Debug";
  1236. full = "(Debug Unit)";
  1237. break;
  1238. default:
  1239. type = "-*- unrecognized -*-";
  1240. full = "";
  1241. break;
  1242. }
  1243. command_print(cmd_ctx, "\t\tPart is %s %s",
  1244. type, full);
  1245. }
  1246. else
  1247. {
  1248. if (romentry)
  1249. command_print(cmd_ctx, "\t\tComponent not present");
  1250. else
  1251. command_print(cmd_ctx, "\t\tEnd of ROM table");
  1252. }
  1253. entry_offset += 4;
  1254. } while (romentry > 0);
  1255. }
  1256. else
  1257. {
  1258. command_print(cmd_ctx, "\tNo ROM table present");
  1259. }
  1260. dap_ap_select(swjdp, apselold);
  1261. return ERROR_OK;
  1262. }
  1263. DAP_COMMAND_HANDLER(dap_baseaddr_command)
  1264. {
  1265. uint32_t apsel, apselsave, baseaddr;
  1266. int retval;
  1267. apselsave = swjdp->apsel;
  1268. switch (CMD_ARGC) {
  1269. case 0:
  1270. apsel = swjdp->apsel;
  1271. break;
  1272. case 1:
  1273. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
  1274. break;
  1275. default:
  1276. return ERROR_COMMAND_SYNTAX_ERROR;
  1277. }
  1278. if (apselsave != apsel)
  1279. dap_ap_select(swjdp, apsel);
  1280. dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
  1281. retval = swjdp_transaction_endcheck(swjdp);
  1282. command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
  1283. if (apselsave != apsel)
  1284. dap_ap_select(swjdp, apselsave);
  1285. return retval;
  1286. }
  1287. DAP_COMMAND_HANDLER(dap_memaccess_command)
  1288. {
  1289. uint32_t memaccess_tck;
  1290. switch (CMD_ARGC) {
  1291. case 0:
  1292. memaccess_tck = swjdp->memaccess_tck;
  1293. break;
  1294. case 1:
  1295. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
  1296. break;
  1297. default:
  1298. return ERROR_COMMAND_SYNTAX_ERROR;
  1299. }
  1300. swjdp->memaccess_tck = memaccess_tck;
  1301. command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
  1302. swjdp->memaccess_tck);
  1303. return ERROR_OK;
  1304. }
  1305. DAP_COMMAND_HANDLER(dap_apsel_command)
  1306. {
  1307. uint32_t apsel, apid;
  1308. int retval;
  1309. switch (CMD_ARGC) {
  1310. case 0:
  1311. apsel = 0;
  1312. break;
  1313. case 1:
  1314. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
  1315. break;
  1316. default:
  1317. return ERROR_COMMAND_SYNTAX_ERROR;
  1318. }
  1319. dap_ap_select(swjdp, apsel);
  1320. dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
  1321. retval = swjdp_transaction_endcheck(swjdp);
  1322. command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
  1323. apsel, apid);
  1324. return retval;
  1325. }
  1326. DAP_COMMAND_HANDLER(dap_apid_command)
  1327. {
  1328. uint32_t apsel, apselsave, apid;
  1329. int retval;
  1330. apselsave = swjdp->apsel;
  1331. switch (CMD_ARGC) {
  1332. case 0:
  1333. apsel = swjdp->apsel;
  1334. break;
  1335. case 1:
  1336. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
  1337. break;
  1338. default:
  1339. return ERROR_COMMAND_SYNTAX_ERROR;
  1340. }
  1341. if (apselsave != apsel)
  1342. dap_ap_select(swjdp, apsel);
  1343. dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
  1344. retval = swjdp_transaction_endcheck(swjdp);
  1345. command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
  1346. if (apselsave != apsel)
  1347. dap_ap_select(swjdp, apselsave);
  1348. return retval;
  1349. }