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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifndef ARM_ADI_V5_H
  24. #define ARM_ADI_V5_H
  25. /**
  26. * @file
  27. * This defines formats and data structures used to talk to ADIv5 entities.
  28. * Those include a DAP, different types of Debug Port (DP), and memory mapped
  29. * resources accessed through a MEM-AP.
  30. */
  31. #include "arm_jtag.h"
  32. /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
  33. #define JTAG_DP_ABORT 0x8
  34. #define JTAG_DP_DPACC 0xA
  35. #define JTAG_DP_APACC 0xB
  36. #define JTAG_DP_IDCODE 0xE
  37. /* three-bit ACK values for DPACC and APACC reads */
  38. #define JTAG_ACK_OK_FAULT 0x2
  39. #define JTAG_ACK_WAIT 0x1
  40. #define DPAP_WRITE 0
  41. #define DPAP_READ 1
  42. /* A[3:0] for DP registers (for JTAG, stored in DPACC) */
  43. #define DP_ZERO 0
  44. #define DP_CTRL_STAT 0x4
  45. #define DP_SELECT 0x8
  46. #define DP_RDBUFF 0xC
  47. /* Fields of the DP's CTRL/STAT register */
  48. #define CORUNDETECT (1 << 0)
  49. #define SSTICKYORUN (1 << 1)
  50. /* 3:2 - transaction mode (e.g. pushed compare) */
  51. #define SSTICKYERR (1 << 5)
  52. #define READOK (1 << 6)
  53. #define WDATAERR (1 << 7)
  54. /* 11:8 - mask lanes for pushed compare or verify ops */
  55. /* 21:12 - transaction counter */
  56. #define CDBGRSTREQ (1 << 26)
  57. #define CDBGRSTACK (1 << 27)
  58. #define CDBGPWRUPREQ (1 << 28)
  59. #define CDBGPWRUPACK (1 << 29)
  60. #define CSYSPWRUPREQ (1 << 30)
  61. #define CSYSPWRUPACK (1 << 31)
  62. /* MEM-AP register addresses */
  63. /* TODO: rename as MEM_AP_REG_* */
  64. #define AP_REG_CSW 0x00
  65. #define AP_REG_TAR 0x04
  66. #define AP_REG_DRW 0x0C
  67. #define AP_REG_BD0 0x10
  68. #define AP_REG_BD1 0x14
  69. #define AP_REG_BD2 0x18
  70. #define AP_REG_BD3 0x1C
  71. #define AP_REG_CFG 0xF4 /* big endian? */
  72. #define AP_REG_BASE 0xF8
  73. /* Generic AP register address */
  74. #define AP_REG_IDR 0xFC
  75. /* Fields of the MEM-AP's CSW register */
  76. #define CSW_8BIT 0
  77. #define CSW_16BIT 1
  78. #define CSW_32BIT 2
  79. #define CSW_ADDRINC_MASK (3 << 4)
  80. #define CSW_ADDRINC_OFF 0
  81. #define CSW_ADDRINC_SINGLE (1 << 4)
  82. #define CSW_ADDRINC_PACKED (2 << 4)
  83. #define CSW_DEVICE_EN (1 << 6)
  84. #define CSW_TRIN_PROG (1 << 7)
  85. #define CSW_SPIDEN (1 << 23)
  86. /* 30:24 - implementation-defined! */
  87. #define CSW_HPROT (1 << 25) /* ? */
  88. #define CSW_MASTER_DEBUG (1 << 29) /* ? */
  89. #define CSW_DBGSWENABLE (1 << 31)
  90. /* transaction mode */
  91. #define TRANS_MODE_NONE 0
  92. /* Transaction waits for previous to complete */
  93. #define TRANS_MODE_ATOMIC 1
  94. /* Freerunning transactions with delays and overrun checking */
  95. #define TRANS_MODE_COMPOSITE 2
  96. /**
  97. * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
  98. * A DAP has two types of component: one Debug Port (DP), which is a
  99. * transport agent; and at least one Access Port (AP), controlling
  100. * resource access. Most common is a MEM-AP, for memory access.
  101. *
  102. * @todo Rename "swjdp_common" as "dap". Use of SWJ-DP is optional!
  103. */
  104. struct swjdp_common
  105. {
  106. struct arm_jtag *jtag_info;
  107. /* Control config */
  108. uint32_t dp_ctrl_stat;
  109. /* Support for several AP's in one DAP */
  110. uint32_t apsel;
  111. /* Register select cache */
  112. uint32_t dp_select_value;
  113. uint32_t ap_csw_value;
  114. uint32_t ap_tar_value;
  115. /* information about current pending SWjDP-AHBAP transaction */
  116. uint8_t trans_mode;
  117. uint8_t trans_rw;
  118. uint8_t ack;
  119. /* extra tck clocks for memory bus access */
  120. uint32_t memaccess_tck;
  121. /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
  122. uint32_t tar_autoincr_block;
  123. };
  124. /* Accessor function for currently selected DAP-AP number */
  125. static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
  126. {
  127. return (uint8_t)(swjdp ->apsel >> 24);
  128. }
  129. /* Queued transactions -- use with care */
  130. int dap_setup_accessport(struct swjdp_common *swjdp,
  131. uint32_t csw, uint32_t tar);
  132. int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel);
  133. int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
  134. uint32_t addr, uint32_t value);
  135. int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
  136. uint32_t addr, uint32_t *value);
  137. /* Queued transactions must be completed with swjdp_transaction_endcheck() */
  138. int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
  139. /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
  140. int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
  141. int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
  142. /* MEM-AP memory mapped bus transfers, single registers, complete transactions */
  143. int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
  144. uint32_t address, uint32_t *value);
  145. int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
  146. uint32_t address, uint32_t value);
  147. /* MEM-AP memory mapped bus block transfers */
  148. int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
  149. uint8_t *buffer, int count, uint32_t address);
  150. int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
  151. uint8_t *buffer, int count, uint32_t address);
  152. int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
  153. uint8_t *buffer, int count, uint32_t address);
  154. int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
  155. uint8_t *buffer, int count, uint32_t address);
  156. int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
  157. uint8_t *buffer, int count, uint32_t address);
  158. int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
  159. uint8_t *buffer, int count, uint32_t address);
  160. /* Initialisation of the debug system, power domains and registers */
  161. int ahbap_debugport_init(struct swjdp_common *swjdp);
  162. /* Commands for user dap access */
  163. int dap_info_command(struct command_context *cmd_ctx,
  164. struct swjdp_common *swjdp, int apsel);
  165. #define DAP_COMMAND_HANDLER(name) \
  166. COMMAND_HELPER(name, struct swjdp_common *swjdp)
  167. DAP_COMMAND_HANDLER(dap_baseaddr_command);
  168. DAP_COMMAND_HANDLER(dap_memaccess_command);
  169. DAP_COMMAND_HANDLER(dap_apsel_command);
  170. DAP_COMMAND_HANDLER(dap_apid_command);
  171. #endif