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  1. /*
  2. * Copyright (C) 2009 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the
  16. * Free Software Foundation, Inc.,
  17. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. */
  19. #ifdef HAVE_CONFIG_H
  20. #include "config.h"
  21. #endif
  22. #include "arm.h"
  23. #include "arm_dpm.h"
  24. #include <jtag/jtag.h>
  25. #include "register.h"
  26. #include "breakpoints.h"
  27. #include "target_type.h"
  28. #include "arm_opcodes.h"
  29. /**
  30. * @file
  31. * Implements various ARM DPM operations using architectural debug registers.
  32. * These routines layer over core-specific communication methods to cope with
  33. * implementation differences between cores like ARM1136 and Cortex-A8.
  34. */
  35. /*----------------------------------------------------------------------*/
  36. /*
  37. * Coprocessor support
  38. */
  39. /* Read coprocessor */
  40. static int dpm_mrc(struct target *target, int cpnum,
  41. uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  42. uint32_t *value)
  43. {
  44. struct arm *arm = target_to_arm(target);
  45. struct arm_dpm *dpm = arm->dpm;
  46. int retval;
  47. retval = dpm->prepare(dpm);
  48. if (retval != ERROR_OK)
  49. return retval;
  50. LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
  51. (int) op1, (int) CRn,
  52. (int) CRm, (int) op2);
  53. /* read coprocessor register into R0; return via DCC */
  54. retval = dpm->instr_read_data_r0(dpm,
  55. ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  56. value);
  57. /* (void) */ dpm->finish(dpm);
  58. return retval;
  59. }
  60. static int dpm_mcr(struct target *target, int cpnum,
  61. uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  62. uint32_t value)
  63. {
  64. struct arm *arm = target_to_arm(target);
  65. struct arm_dpm *dpm = arm->dpm;
  66. int retval;
  67. retval = dpm->prepare(dpm);
  68. if (retval != ERROR_OK)
  69. return retval;
  70. LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
  71. (int) op1, (int) CRn,
  72. (int) CRm, (int) op2);
  73. /* read DCC into r0; then write coprocessor register from R0 */
  74. retval = dpm->instr_write_data_r0(dpm,
  75. ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  76. value);
  77. /* (void) */ dpm->finish(dpm);
  78. return retval;
  79. }
  80. /*----------------------------------------------------------------------*/
  81. /*
  82. * Register access utilities
  83. */
  84. /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  85. * Routines *must* restore the original mode before returning!!
  86. */
  87. static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
  88. {
  89. int retval;
  90. uint32_t cpsr;
  91. /* restore previous mode */
  92. if (mode == ARM_MODE_ANY)
  93. cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
  94. /* else force to the specified mode */
  95. else
  96. cpsr = mode;
  97. retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
  98. if (dpm->instr_cpsr_sync)
  99. retval = dpm->instr_cpsr_sync(dpm);
  100. return retval;
  101. }
  102. /* just read the register -- rely on the core mode being right */
  103. static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
  104. {
  105. uint32_t value;
  106. int retval;
  107. switch (regnum) {
  108. case 0 ... 14:
  109. /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
  110. retval = dpm->instr_read_data_dcc(dpm,
  111. ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
  112. &value);
  113. break;
  114. case 15: /* PC */
  115. /* "MOV r0, pc"; then return via DCC */
  116. retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
  117. /* NOTE: this seems like a slightly awkward place to update
  118. * this value ... but if the PC gets written (the only way
  119. * to change what we compute), the arch spec says subsequent
  120. * reads return values which are "unpredictable". So this
  121. * is always right except in those broken-by-intent cases.
  122. */
  123. switch (dpm->arm->core_state) {
  124. case ARM_STATE_ARM:
  125. value -= 8;
  126. break;
  127. case ARM_STATE_THUMB:
  128. case ARM_STATE_THUMB_EE:
  129. value -= 4;
  130. break;
  131. case ARM_STATE_JAZELLE:
  132. /* core-specific ... ? */
  133. LOG_WARNING("Jazelle PC adjustment unknown");
  134. break;
  135. }
  136. break;
  137. default:
  138. /* 16: "MRS r0, CPSR"; then return via DCC
  139. * 17: "MRS r0, SPSR"; then return via DCC
  140. */
  141. retval = dpm->instr_read_data_r0(dpm,
  142. ARMV4_5_MRS(0, regnum & 1),
  143. &value);
  144. break;
  145. }
  146. if (retval == ERROR_OK) {
  147. buf_set_u32(r->value, 0, 32, value);
  148. r->valid = true;
  149. r->dirty = false;
  150. LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
  151. }
  152. return retval;
  153. }
  154. /* just write the register -- rely on the core mode being right */
  155. static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
  156. {
  157. int retval;
  158. uint32_t value = buf_get_u32(r->value, 0, 32);
  159. switch (regnum) {
  160. case 0 ... 14:
  161. /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
  162. retval = dpm->instr_write_data_dcc(dpm,
  163. ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
  164. value);
  165. break;
  166. case 15: /* PC */
  167. /* read r0 from DCC; then "MOV pc, r0" */
  168. retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
  169. break;
  170. default:
  171. /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
  172. * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
  173. */
  174. retval = dpm->instr_write_data_r0(dpm,
  175. ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
  176. value);
  177. if (regnum == 16 && dpm->instr_cpsr_sync)
  178. retval = dpm->instr_cpsr_sync(dpm);
  179. break;
  180. }
  181. if (retval == ERROR_OK) {
  182. r->dirty = false;
  183. LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
  184. }
  185. return retval;
  186. }
  187. /**
  188. * Read basic registers of the the current context: R0 to R15, and CPSR;
  189. * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  190. * In normal operation this is called on entry to halting debug state,
  191. * possibly after some other operations supporting restore of debug state
  192. * or making sure the CPU is fully idle (drain write buffer, etc).
  193. */
  194. int arm_dpm_read_current_registers(struct arm_dpm *dpm)
  195. {
  196. struct arm *arm = dpm->arm;
  197. uint32_t cpsr;
  198. int retval;
  199. struct reg *r;
  200. retval = dpm->prepare(dpm);
  201. if (retval != ERROR_OK)
  202. return retval;
  203. /* read R0 first (it's used for scratch), then CPSR */
  204. r = arm->core_cache->reg_list + 0;
  205. if (!r->valid) {
  206. retval = dpm_read_reg(dpm, r, 0);
  207. if (retval != ERROR_OK)
  208. goto fail;
  209. }
  210. r->dirty = true;
  211. retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
  212. if (retval != ERROR_OK)
  213. goto fail;
  214. /* update core mode and state, plus shadow mapping for R8..R14 */
  215. arm_set_cpsr(arm, cpsr);
  216. /* REVISIT we can probably avoid reading R1..R14, saving time... */
  217. for (unsigned i = 1; i < 16; i++) {
  218. r = arm_reg_current(arm, i);
  219. if (r->valid)
  220. continue;
  221. retval = dpm_read_reg(dpm, r, i);
  222. if (retval != ERROR_OK)
  223. goto fail;
  224. }
  225. /* NOTE: SPSR ignored (if it's even relevant). */
  226. /* REVISIT the debugger can trigger various exceptions. See the
  227. * ARMv7A architecture spec, section C5.7, for more info about
  228. * what defenses are needed; v6 debug has the most issues.
  229. */
  230. fail:
  231. /* (void) */ dpm->finish(dpm);
  232. return retval;
  233. }
  234. /* Avoid needless I/O ... leave breakpoints and watchpoints alone
  235. * unless they're removed, or need updating because of single-stepping
  236. * or running debugger code.
  237. */
  238. static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
  239. struct dpm_bpwp *xp, int *set_p)
  240. {
  241. int retval = ERROR_OK;
  242. bool disable;
  243. if (!set_p) {
  244. if (!xp->dirty)
  245. goto done;
  246. xp->dirty = false;
  247. /* removed or startup; we must disable it */
  248. disable = true;
  249. } else if (bpwp) {
  250. if (!xp->dirty)
  251. goto done;
  252. /* disabled, but we must set it */
  253. xp->dirty = disable = false;
  254. *set_p = true;
  255. } else {
  256. if (!*set_p)
  257. goto done;
  258. /* set, but we must temporarily disable it */
  259. xp->dirty = disable = true;
  260. *set_p = false;
  261. }
  262. if (disable)
  263. retval = dpm->bpwp_disable(dpm, xp->number);
  264. else
  265. retval = dpm->bpwp_enable(dpm, xp->number,
  266. xp->address, xp->control);
  267. if (retval != ERROR_OK)
  268. LOG_ERROR("%s: can't %s HW bp/wp %d",
  269. disable ? "disable" : "enable",
  270. target_name(dpm->arm->target),
  271. xp->number);
  272. done:
  273. return retval;
  274. }
  275. /**
  276. * Writes all modified core registers for all processor modes. In normal
  277. * operation this is called on exit from halting debug state.
  278. *
  279. * @param dpm: represents the processor
  280. * @param bpwp: true ensures breakpoints and watchpoints are set,
  281. * false ensures they are cleared
  282. */
  283. int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
  284. {
  285. struct arm *arm = dpm->arm;
  286. struct reg_cache *cache = arm->core_cache;
  287. int retval;
  288. bool did_write;
  289. retval = dpm->prepare(dpm);
  290. if (retval != ERROR_OK)
  291. goto done;
  292. /* enable/disable hardware breakpoints */
  293. for (unsigned i = 0; i < dpm->nbp; i++) {
  294. struct dpm_bp *dbp = dpm->dbp + i;
  295. struct breakpoint *bp = dbp->bp;
  296. retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
  297. bp ? &bp->set : NULL);
  298. }
  299. /* enable/disable watchpoints */
  300. for (unsigned i = 0; i < dpm->nwp; i++) {
  301. struct dpm_wp *dwp = dpm->dwp + i;
  302. struct watchpoint *wp = dwp->wp;
  303. retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
  304. wp ? &wp->set : NULL);
  305. }
  306. /* NOTE: writes to breakpoint and watchpoint registers might
  307. * be queued, and need (efficient/batched) flushing later.
  308. */
  309. /* Scan the registers until we find one that's both dirty and
  310. * eligible for flushing. Flush that and everything else that
  311. * shares the same core mode setting. Typically this won't
  312. * actually find anything to do...
  313. */
  314. do {
  315. enum arm_mode mode = ARM_MODE_ANY;
  316. did_write = false;
  317. /* check everything except our scratch register R0 */
  318. for (unsigned i = 1; i < cache->num_regs; i++) {
  319. struct arm_reg *r;
  320. unsigned regnum;
  321. /* also skip PC, CPSR, and non-dirty */
  322. if (i == 15)
  323. continue;
  324. if (arm->cpsr == cache->reg_list + i)
  325. continue;
  326. if (!cache->reg_list[i].dirty)
  327. continue;
  328. r = cache->reg_list[i].arch_info;
  329. regnum = r->num;
  330. /* may need to pick and set a mode */
  331. if (!did_write) {
  332. enum arm_mode tmode;
  333. did_write = true;
  334. mode = tmode = r->mode;
  335. /* cope with special cases */
  336. switch (regnum) {
  337. case 8 ... 12:
  338. /* r8..r12 "anything but FIQ" case;
  339. * we "know" core mode is accurate
  340. * since we haven't changed it yet
  341. */
  342. if (arm->core_mode == ARM_MODE_FIQ
  343. && ARM_MODE_ANY
  344. != mode)
  345. tmode = ARM_MODE_USR;
  346. break;
  347. case 16:
  348. /* SPSR */
  349. regnum++;
  350. break;
  351. }
  352. /* REVISIT error checks */
  353. if (tmode != ARM_MODE_ANY)
  354. retval = dpm_modeswitch(dpm, tmode);
  355. }
  356. if (r->mode != mode)
  357. continue;
  358. retval = dpm_write_reg(dpm,
  359. &cache->reg_list[i],
  360. regnum);
  361. }
  362. } while (did_write);
  363. /* Restore original CPSR ... assuming either that we changed it,
  364. * or it's dirty. Must write PC to ensure the return address is
  365. * defined, and must not write it before CPSR.
  366. */
  367. retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
  368. arm->cpsr->dirty = false;
  369. retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
  370. cache->reg_list[15].dirty = false;
  371. /* flush R0 -- it's *very* dirty by now */
  372. retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
  373. cache->reg_list[0].dirty = false;
  374. /* (void) */ dpm->finish(dpm);
  375. done:
  376. return retval;
  377. }
  378. /* Returns ARM_MODE_ANY or temporary mode to use while reading the
  379. * specified register ... works around flakiness from ARM core calls.
  380. * Caller already filtered out SPSR access; mode is never MODE_SYS
  381. * or MODE_ANY.
  382. */
  383. static enum arm_mode dpm_mapmode(struct arm *arm,
  384. unsigned num, enum arm_mode mode)
  385. {
  386. enum arm_mode amode = arm->core_mode;
  387. /* don't switch if the mode is already correct */
  388. if (amode == ARM_MODE_SYS)
  389. amode = ARM_MODE_USR;
  390. if (mode == amode)
  391. return ARM_MODE_ANY;
  392. switch (num) {
  393. /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
  394. case 0 ... 7:
  395. case 15:
  396. case 16:
  397. break;
  398. /* r8..r12 aren't shadowed for anything except FIQ */
  399. case 8 ... 12:
  400. if (mode == ARM_MODE_FIQ)
  401. return mode;
  402. break;
  403. /* r13/sp, and r14/lr are always shadowed */
  404. case 13:
  405. case 14:
  406. return mode;
  407. default:
  408. LOG_WARNING("invalid register #%u", num);
  409. break;
  410. }
  411. return ARM_MODE_ANY;
  412. }
  413. /*
  414. * Standard ARM register accessors ... there are three methods
  415. * in "struct arm", to support individual read/write and bulk read
  416. * of registers.
  417. */
  418. static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
  419. int regnum, enum arm_mode mode)
  420. {
  421. struct arm_dpm *dpm = target_to_arm(target)->dpm;
  422. int retval;
  423. if (regnum < 0 || regnum > 16)
  424. return ERROR_INVALID_ARGUMENTS;
  425. if (regnum == 16) {
  426. if (mode != ARM_MODE_ANY)
  427. regnum = 17;
  428. } else
  429. mode = dpm_mapmode(dpm->arm, regnum, mode);
  430. /* REVISIT what happens if we try to read SPSR in a core mode
  431. * which has no such register?
  432. */
  433. retval = dpm->prepare(dpm);
  434. if (retval != ERROR_OK)
  435. return retval;
  436. if (mode != ARM_MODE_ANY) {
  437. retval = dpm_modeswitch(dpm, mode);
  438. if (retval != ERROR_OK)
  439. goto fail;
  440. }
  441. retval = dpm_read_reg(dpm, r, regnum);
  442. /* always clean up, regardless of error */
  443. if (mode != ARM_MODE_ANY)
  444. /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
  445. fail:
  446. /* (void) */ dpm->finish(dpm);
  447. return retval;
  448. }
  449. static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
  450. int regnum, enum arm_mode mode, uint32_t value)
  451. {
  452. struct arm_dpm *dpm = target_to_arm(target)->dpm;
  453. int retval;
  454. if (regnum < 0 || regnum > 16)
  455. return ERROR_INVALID_ARGUMENTS;
  456. if (regnum == 16) {
  457. if (mode != ARM_MODE_ANY)
  458. regnum = 17;
  459. } else
  460. mode = dpm_mapmode(dpm->arm, regnum, mode);
  461. /* REVISIT what happens if we try to write SPSR in a core mode
  462. * which has no such register?
  463. */
  464. retval = dpm->prepare(dpm);
  465. if (retval != ERROR_OK)
  466. return retval;
  467. if (mode != ARM_MODE_ANY) {
  468. retval = dpm_modeswitch(dpm, mode);
  469. if (retval != ERROR_OK)
  470. goto fail;
  471. }
  472. retval = dpm_write_reg(dpm, r, regnum);
  473. /* always clean up, regardless of error */
  474. if (mode != ARM_MODE_ANY)
  475. /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
  476. fail:
  477. /* (void) */ dpm->finish(dpm);
  478. return retval;
  479. }
  480. static int arm_dpm_full_context(struct target *target)
  481. {
  482. struct arm *arm = target_to_arm(target);
  483. struct arm_dpm *dpm = arm->dpm;
  484. struct reg_cache *cache = arm->core_cache;
  485. int retval;
  486. bool did_read;
  487. retval = dpm->prepare(dpm);
  488. if (retval != ERROR_OK)
  489. goto done;
  490. do {
  491. enum arm_mode mode = ARM_MODE_ANY;
  492. did_read = false;
  493. /* We "know" arm_dpm_read_current_registers() was called so
  494. * the unmapped registers (R0..R7, PC, AND CPSR) and some
  495. * view of R8..R14 are current. We also "know" oddities of
  496. * register mapping: special cases for R8..R12 and SPSR.
  497. *
  498. * Pick some mode with unread registers and read them all.
  499. * Repeat until done.
  500. */
  501. for (unsigned i = 0; i < cache->num_regs; i++) {
  502. struct arm_reg *r;
  503. if (cache->reg_list[i].valid)
  504. continue;
  505. r = cache->reg_list[i].arch_info;
  506. /* may need to pick a mode and set CPSR */
  507. if (!did_read) {
  508. did_read = true;
  509. mode = r->mode;
  510. /* For R8..R12 when we've entered debug
  511. * state in FIQ mode... patch mode.
  512. */
  513. if (mode == ARM_MODE_ANY)
  514. mode = ARM_MODE_USR;
  515. /* REVISIT error checks */
  516. retval = dpm_modeswitch(dpm, mode);
  517. }
  518. if (r->mode != mode)
  519. continue;
  520. /* CPSR was read, so "R16" must mean SPSR */
  521. retval = dpm_read_reg(dpm,
  522. &cache->reg_list[i],
  523. (r->num == 16) ? 17 : r->num);
  524. }
  525. } while (did_read);
  526. retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
  527. /* (void) */ dpm->finish(dpm);
  528. done:
  529. return retval;
  530. }
  531. /*----------------------------------------------------------------------*/
  532. /*
  533. * Breakpoint and Watchpoint support.
  534. *
  535. * Hardware {break,watch}points are usually left active, to minimize
  536. * debug entry/exit costs. When they are set or cleared, it's done in
  537. * batches. Also, DPM-conformant hardware can update debug registers
  538. * regardless of whether the CPU is running or halted ... though that
  539. * fact isn't currently leveraged.
  540. */
  541. static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
  542. struct watchpoint *wp)
  543. {
  544. uint32_t addr = wp->address;
  545. uint32_t control;
  546. /* this hardware doesn't support data value matching or masking */
  547. if (wp->value || wp->mask != ~(uint32_t)0) {
  548. LOG_DEBUG("watchpoint values and masking not supported");
  549. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  550. }
  551. control = (1 << 0) /* enable */
  552. | (3 << 1); /* both user and privileged access */
  553. switch (wp->rw) {
  554. case WPT_READ:
  555. control |= 1 << 3;
  556. break;
  557. case WPT_WRITE:
  558. control |= 2 << 3;
  559. break;
  560. case WPT_ACCESS:
  561. control |= 3 << 3;
  562. break;
  563. }
  564. /* Match 1, 2, or all 4 byte addresses in this word.
  565. *
  566. * FIXME: v7 hardware allows lengths up to 2 GB, and has eight
  567. * byte address select bits. Support larger wp->length, if addr
  568. * is suitably aligned.
  569. */
  570. switch (wp->length) {
  571. case 1:
  572. control |= (1 << (addr & 3)) << 5;
  573. addr &= ~3;
  574. break;
  575. case 2:
  576. /* require 2-byte alignment */
  577. if (!(addr & 1)) {
  578. control |= (3 << (addr & 2)) << 5;
  579. break;
  580. }
  581. /* FALL THROUGH */
  582. case 4:
  583. /* require 4-byte alignment */
  584. if (!(addr & 3)) {
  585. control |= 0xf << 5;
  586. break;
  587. }
  588. /* FALL THROUGH */
  589. default:
  590. LOG_DEBUG("bad watchpoint length or alignment");
  591. return ERROR_INVALID_ARGUMENTS;
  592. }
  593. /* other control bits:
  594. * bits 9:12 == 0 ... only checking up to four byte addresses (v7 only)
  595. * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
  596. * bit 20 == 0 ... not linked to a context ID
  597. * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
  598. */
  599. dpm->dwp[index].wp = wp;
  600. dpm->dwp[index].bpwp.address = addr & ~3;
  601. dpm->dwp[index].bpwp.control = control;
  602. dpm->dwp[index].bpwp.dirty = true;
  603. /* hardware is updated in write_dirty_registers() */
  604. return ERROR_OK;
  605. }
  606. static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
  607. {
  608. struct arm *arm = target_to_arm(target);
  609. struct arm_dpm *dpm = arm->dpm;
  610. int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  611. if (dpm->bpwp_enable) {
  612. for (unsigned i = 0; i < dpm->nwp; i++) {
  613. if (!dpm->dwp[i].wp) {
  614. retval = dpm_watchpoint_setup(dpm, i, wp);
  615. break;
  616. }
  617. }
  618. }
  619. return retval;
  620. }
  621. static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
  622. {
  623. struct arm *arm = target_to_arm(target);
  624. struct arm_dpm *dpm = arm->dpm;
  625. int retval = ERROR_INVALID_ARGUMENTS;
  626. for (unsigned i = 0; i < dpm->nwp; i++) {
  627. if (dpm->dwp[i].wp == wp) {
  628. dpm->dwp[i].wp = NULL;
  629. dpm->dwp[i].bpwp.dirty = true;
  630. /* hardware is updated in write_dirty_registers() */
  631. retval = ERROR_OK;
  632. break;
  633. }
  634. }
  635. return retval;
  636. }
  637. void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
  638. {
  639. switch (dpm->arm->core_state) {
  640. case ARM_STATE_ARM:
  641. addr -= 8;
  642. break;
  643. case ARM_STATE_THUMB:
  644. case ARM_STATE_THUMB_EE:
  645. addr -= 4;
  646. break;
  647. case ARM_STATE_JAZELLE:
  648. /* ?? */
  649. break;
  650. }
  651. dpm->wp_pc = addr;
  652. }
  653. /*----------------------------------------------------------------------*/
  654. /*
  655. * Other debug and support utilities
  656. */
  657. void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
  658. {
  659. struct target *target = dpm->arm->target;
  660. dpm->dscr = dscr;
  661. /* Examine debug reason */
  662. switch (DSCR_ENTRY(dscr)) {
  663. case 6: /* Data abort (v6 only) */
  664. case 7: /* Prefetch abort (v6 only) */
  665. /* FALL THROUGH -- assume a v6 core in abort mode */
  666. case 0: /* HALT request from debugger */
  667. case 4: /* EDBGRQ */
  668. target->debug_reason = DBG_REASON_DBGRQ;
  669. break;
  670. case 1: /* HW breakpoint */
  671. case 3: /* SW BKPT */
  672. case 5: /* vector catch */
  673. target->debug_reason = DBG_REASON_BREAKPOINT;
  674. break;
  675. case 2: /* asynch watchpoint */
  676. case 10: /* precise watchpoint */
  677. target->debug_reason = DBG_REASON_WATCHPOINT;
  678. break;
  679. default:
  680. target->debug_reason = DBG_REASON_UNDEFINED;
  681. break;
  682. }
  683. }
  684. /*----------------------------------------------------------------------*/
  685. /*
  686. * Setup and management support.
  687. */
  688. /**
  689. * Hooks up this DPM to its associated target; call only once.
  690. * Initially this only covers the register cache.
  691. *
  692. * Oh, and watchpoints. Yeah.
  693. */
  694. int arm_dpm_setup(struct arm_dpm *dpm)
  695. {
  696. struct arm *arm = dpm->arm;
  697. struct target *target = arm->target;
  698. struct reg_cache *cache;
  699. arm->dpm = dpm;
  700. /* register access setup */
  701. arm->full_context = arm_dpm_full_context;
  702. arm->read_core_reg = arm_dpm_read_core_reg;
  703. arm->write_core_reg = arm_dpm_write_core_reg;
  704. cache = arm_build_reg_cache(target, arm);
  705. if (!cache)
  706. return ERROR_FAIL;
  707. *register_get_last_cache_p(&target->reg_cache) = cache;
  708. /* coprocessor access setup */
  709. arm->mrc = dpm_mrc;
  710. arm->mcr = dpm_mcr;
  711. /* breakpoint and watchpoint setup */
  712. target->type->add_watchpoint = dpm_add_watchpoint;
  713. target->type->remove_watchpoint = dpm_remove_watchpoint;
  714. /* FIXME add breakpoint support */
  715. /* FIXME add vector catch support */
  716. dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
  717. dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
  718. dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
  719. dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
  720. if (!dpm->dbp || !dpm->dwp) {
  721. free(dpm->dbp);
  722. free(dpm->dwp);
  723. return ERROR_FAIL;
  724. }
  725. LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
  726. target_name(target), dpm->nbp, dpm->nwp);
  727. /* REVISIT ... and some of those breakpoints could match
  728. * execution context IDs...
  729. */
  730. return ERROR_OK;
  731. }
  732. /**
  733. * Reinitializes DPM state at the beginning of a new debug session
  734. * or after a reset which may have affected the debug module.
  735. */
  736. int arm_dpm_initialize(struct arm_dpm *dpm)
  737. {
  738. /* Disable all breakpoints and watchpoints at startup. */
  739. if (dpm->bpwp_disable) {
  740. unsigned i;
  741. for (i = 0; i < dpm->nbp; i++) {
  742. dpm->dbp[i].bpwp.number = i;
  743. (void) dpm->bpwp_disable(dpm, i);
  744. }
  745. for (i = 0; i < dpm->nwp; i++) {
  746. dpm->dwp[i].bpwp.number = 16 + i;
  747. (void) dpm->bpwp_disable(dpm, 16 + i);
  748. }
  749. } else
  750. LOG_WARNING("%s: can't disable breakpoints and watchpoints",
  751. target_name(dpm->arm->target));
  752. return ERROR_OK;
  753. }