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  1. /*
  2. * Copyright (C) 2009 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the
  16. * Free Software Foundation, Inc.,
  17. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. */
  19. #ifndef __ARM_DPM_H
  20. #define __ARM_DPM_H
  21. /**
  22. * @file
  23. * This is the interface to the Debug Programmers Model for ARMv6 and
  24. * ARMv7 processors. ARMv6 processors (such as ARM11xx implementations)
  25. * introduced a model which became part of the ARMv7-AR architecture
  26. * which is most familiar through the Cortex-A series parts. While
  27. * specific details differ (like how to write the instruction register),
  28. * the high level models easily support shared code because those
  29. * registers are compatible.
  30. */
  31. struct dpm_bpwp {
  32. unsigned number;
  33. uint32_t address;
  34. uint32_t control;
  35. /* true if hardware state needs flushing */
  36. bool dirty;
  37. };
  38. struct dpm_bp {
  39. struct breakpoint *bp;
  40. struct dpm_bpwp bpwp;
  41. };
  42. struct dpm_wp {
  43. struct watchpoint *wp;
  44. struct dpm_bpwp bpwp;
  45. };
  46. /**
  47. * This wraps an implementation of DPM primitives. Each interface
  48. * provider supplies a structure like this, which is the glue between
  49. * upper level code and the lower level hardware access.
  50. *
  51. * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
  52. * support for CPU register access.
  53. */
  54. struct arm_dpm {
  55. struct arm *arm;
  56. /** Cache of DIDR */
  57. uint32_t didr;
  58. /** Invoke before a series of instruction operations */
  59. int (*prepare)(struct arm_dpm *);
  60. /** Invoke after a series of instruction operations */
  61. int (*finish)(struct arm_dpm *);
  62. /* WRITE TO CPU */
  63. /** Runs one instruction, writing data to DCC before execution. */
  64. int (*instr_write_data_dcc)(struct arm_dpm *,
  65. uint32_t opcode, uint32_t data);
  66. /** Runs one instruction, writing data to R0 before execution. */
  67. int (*instr_write_data_r0)(struct arm_dpm *,
  68. uint32_t opcode, uint32_t data);
  69. /** Optional core-specific operation invoked after CPSR writes. */
  70. int (*instr_cpsr_sync)(struct arm_dpm *dpm);
  71. /* READ FROM CPU */
  72. /** Runs one instruction, reading data from dcc after execution. */
  73. int (*instr_read_data_dcc)(struct arm_dpm *,
  74. uint32_t opcode, uint32_t *data);
  75. /** Runs one instruction, reading data from r0 after execution. */
  76. int (*instr_read_data_r0)(struct arm_dpm *,
  77. uint32_t opcode, uint32_t *data);
  78. /* BREAKPOINT/WATCHPOINT SUPPORT */
  79. /**
  80. * Enables one breakpoint or watchpoint by writing to the
  81. * hardware registers. The specified breakpoint/watchpoint
  82. * must currently be disabled. Indices 0..15 are used for
  83. * breakpoints; indices 16..31 are for watchpoints.
  84. */
  85. int (*bpwp_enable)(struct arm_dpm *, unsigned index,
  86. uint32_t addr, uint32_t control);
  87. /**
  88. * Disables one breakpoint or watchpoint by clearing its
  89. * hardware control registers. Indices are the same ones
  90. * accepted by bpwp_enable().
  91. */
  92. int (*bpwp_disable)(struct arm_dpm *, unsigned index);
  93. /* The breakpoint and watchpoint arrays are private to the
  94. * DPM infrastructure. There are nbp indices in the dbp
  95. * array. There are nwp indices in the dwp array.
  96. */
  97. unsigned nbp;
  98. unsigned nwp;
  99. struct dpm_bp *dbp;
  100. struct dpm_wp *dwp;
  101. /** Address of the instruction which triggered a watchpoint. */
  102. uint32_t wp_pc;
  103. /** Recent value of DSCR. */
  104. uint32_t dscr;
  105. // FIXME -- read/write DCSR methods and symbols
  106. };
  107. int arm_dpm_setup(struct arm_dpm *dpm);
  108. int arm_dpm_initialize(struct arm_dpm *dpm);
  109. int arm_dpm_read_current_registers(struct arm_dpm *);
  110. int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
  111. void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
  112. /* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1.
  113. * Not all v7 bits are valid in v6.
  114. */
  115. #define DSCR_CORE_HALTED (1 << 0)
  116. #define DSCR_CORE_RESTARTED (1 << 1)
  117. #define DSCR_INT_DIS (1 << 11)
  118. #define DSCR_ITR_EN (1 << 13)
  119. #define DSCR_HALT_DBG_MODE (1 << 14)
  120. #define DSCR_MON_DBG_MODE (1 << 15)
  121. #define DSCR_INSTR_COMP (1 << 24)
  122. #define DSCR_DTR_TX_FULL (1 << 29)
  123. #define DSCR_DTR_RX_FULL (1 << 30)
  124. #define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
  125. void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
  126. #endif /* __ARM_DPM_H */