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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Hongtao Zheng *
  6. * hontor@126.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "arm.h"
  27. #include "armv4_5.h"
  28. #include "arm_disassembler.h"
  29. #include "arm_simulator.h"
  30. #include <helper/binarybuffer.h>
  31. #include "register.h"
  32. #include <helper/log.h>
  33. static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
  34. uint32_t shift_amount, uint8_t *carry)
  35. {
  36. uint32_t return_value = 0;
  37. shift_amount &= 0xff;
  38. if (shift == 0x0) /* LSL */
  39. {
  40. if ((shift_amount > 0) && (shift_amount <= 32))
  41. {
  42. return_value = Rm << shift_amount;
  43. *carry = Rm >> (32 - shift_amount);
  44. }
  45. else if (shift_amount > 32)
  46. {
  47. return_value = 0x0;
  48. *carry = 0x0;
  49. }
  50. else /* (shift_amount == 0) */
  51. {
  52. return_value = Rm;
  53. }
  54. }
  55. else if (shift == 0x1) /* LSR */
  56. {
  57. if ((shift_amount > 0) && (shift_amount <= 32))
  58. {
  59. return_value = Rm >> shift_amount;
  60. *carry = (Rm >> (shift_amount - 1)) & 1;
  61. }
  62. else if (shift_amount > 32)
  63. {
  64. return_value = 0x0;
  65. *carry = 0x0;
  66. }
  67. else /* (shift_amount == 0) */
  68. {
  69. return_value = Rm;
  70. }
  71. }
  72. else if (shift == 0x2) /* ASR */
  73. {
  74. if ((shift_amount > 0) && (shift_amount <= 32))
  75. {
  76. /* C right shifts of unsigned values are guaranteed to
  77. * be logical (shift in zeroes); simulate an arithmetic
  78. * shift (shift in signed-bit) by adding the sign bit
  79. * manually
  80. */
  81. return_value = Rm >> shift_amount;
  82. if (Rm & 0x80000000)
  83. return_value |= 0xffffffff << (32 - shift_amount);
  84. }
  85. else if (shift_amount > 32)
  86. {
  87. if (Rm & 0x80000000)
  88. {
  89. return_value = 0xffffffff;
  90. *carry = 0x1;
  91. }
  92. else
  93. {
  94. return_value = 0x0;
  95. *carry = 0x0;
  96. }
  97. }
  98. else /* (shift_amount == 0) */
  99. {
  100. return_value = Rm;
  101. }
  102. }
  103. else if (shift == 0x3) /* ROR */
  104. {
  105. if (shift_amount == 0)
  106. {
  107. return_value = Rm;
  108. }
  109. else
  110. {
  111. shift_amount = shift_amount % 32;
  112. return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount));
  113. *carry = (return_value >> 31) & 0x1;
  114. }
  115. }
  116. else if (shift == 0x4) /* RRX */
  117. {
  118. return_value = Rm >> 1;
  119. if (*carry)
  120. Rm |= 0x80000000;
  121. *carry = Rm & 0x1;
  122. }
  123. return return_value;
  124. }
  125. static uint32_t arm_shifter_operand(struct arm_sim_interface *sim,
  126. int variant, union arm_shifter_operand shifter_operand,
  127. uint8_t *shifter_carry_out)
  128. {
  129. uint32_t return_value;
  130. int instruction_size;
  131. if (sim->get_state(sim) == ARM_STATE_ARM)
  132. instruction_size = 4;
  133. else
  134. instruction_size = 2;
  135. *shifter_carry_out = sim->get_cpsr(sim, 29, 1);
  136. if (variant == 0) /* 32-bit immediate */
  137. {
  138. return_value = shifter_operand.immediate.immediate;
  139. }
  140. else if (variant == 1) /* immediate shift */
  141. {
  142. uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm);
  143. /* adjust RM in case the PC is being read */
  144. if (shifter_operand.immediate_shift.Rm == 15)
  145. Rm += 2 * instruction_size;
  146. return_value = arm_shift(shifter_operand.immediate_shift.shift,
  147. Rm, shifter_operand.immediate_shift.shift_imm,
  148. shifter_carry_out);
  149. }
  150. else if (variant == 2) /* register shift */
  151. {
  152. uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm);
  153. uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs);
  154. /* adjust RM in case the PC is being read */
  155. if (shifter_operand.register_shift.Rm == 15)
  156. Rm += 2 * instruction_size;
  157. return_value = arm_shift(shifter_operand.immediate_shift.shift,
  158. Rm, Rs, shifter_carry_out);
  159. }
  160. else
  161. {
  162. LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
  163. return_value = 0xffffffff;
  164. }
  165. return return_value;
  166. }
  167. static int pass_condition(uint32_t cpsr, uint32_t opcode)
  168. {
  169. switch ((opcode & 0xf0000000) >> 28)
  170. {
  171. case 0x0: /* EQ */
  172. if (cpsr & 0x40000000)
  173. return 1;
  174. else
  175. return 0;
  176. case 0x1: /* NE */
  177. if (!(cpsr & 0x40000000))
  178. return 1;
  179. else
  180. return 0;
  181. case 0x2: /* CS */
  182. if (cpsr & 0x20000000)
  183. return 1;
  184. else
  185. return 0;
  186. case 0x3: /* CC */
  187. if (!(cpsr & 0x20000000))
  188. return 1;
  189. else
  190. return 0;
  191. case 0x4: /* MI */
  192. if (cpsr & 0x80000000)
  193. return 1;
  194. else
  195. return 0;
  196. case 0x5: /* PL */
  197. if (!(cpsr & 0x80000000))
  198. return 1;
  199. else
  200. return 0;
  201. case 0x6: /* VS */
  202. if (cpsr & 0x10000000)
  203. return 1;
  204. else
  205. return 0;
  206. case 0x7: /* VC */
  207. if (!(cpsr & 0x10000000))
  208. return 1;
  209. else
  210. return 0;
  211. case 0x8: /* HI */
  212. if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
  213. return 1;
  214. else
  215. return 0;
  216. case 0x9: /* LS */
  217. if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
  218. return 1;
  219. else
  220. return 0;
  221. case 0xa: /* GE */
  222. if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
  223. || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
  224. return 1;
  225. else
  226. return 0;
  227. case 0xb: /* LT */
  228. if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
  229. || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
  230. return 1;
  231. else
  232. return 0;
  233. case 0xc: /* GT */
  234. if (!(cpsr & 0x40000000) &&
  235. (((cpsr & 0x80000000) && (cpsr & 0x10000000))
  236. || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
  237. return 1;
  238. else
  239. return 0;
  240. case 0xd: /* LE */
  241. if ((cpsr & 0x40000000) ||
  242. ((cpsr & 0x80000000) && !(cpsr & 0x10000000))
  243. || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
  244. return 1;
  245. else
  246. return 0;
  247. case 0xe:
  248. case 0xf:
  249. return 1;
  250. }
  251. LOG_ERROR("BUG: should never get here");
  252. return 0;
  253. }
  254. static int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
  255. {
  256. return pass_condition(cpsr, (opcode & 0x0f00) << 20);
  257. }
  258. /* simulate a single step (if possible)
  259. * if the dry_run_pc argument is provided, no state is changed,
  260. * but the new pc is stored in the variable pointed at by the argument
  261. */
  262. int arm_simulate_step_core(struct target *target,
  263. uint32_t *dry_run_pc, struct arm_sim_interface *sim)
  264. {
  265. uint32_t current_pc = sim->get_reg(sim, 15);
  266. struct arm_instruction instruction;
  267. int instruction_size;
  268. int retval = ERROR_OK;
  269. if (sim->get_state(sim) == ARM_STATE_ARM)
  270. {
  271. uint32_t opcode;
  272. /* get current instruction, and identify it */
  273. if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
  274. {
  275. return retval;
  276. }
  277. if ((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
  278. {
  279. return retval;
  280. }
  281. instruction_size = 4;
  282. /* check condition code (for all instructions) */
  283. if (!pass_condition(sim->get_cpsr(sim, 0, 32), opcode))
  284. {
  285. if (dry_run_pc)
  286. {
  287. *dry_run_pc = current_pc + instruction_size;
  288. }
  289. else
  290. {
  291. sim->set_reg(sim, 15, current_pc + instruction_size);
  292. }
  293. return ERROR_OK;
  294. }
  295. }
  296. else
  297. {
  298. uint16_t opcode;
  299. retval = target_read_u16(target, current_pc, &opcode);
  300. if (retval != ERROR_OK)
  301. return retval;
  302. retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
  303. if (retval != ERROR_OK)
  304. return retval;
  305. instruction_size = 2;
  306. /* check condition code (only for branch (1) instructions) */
  307. if ((opcode & 0xf000) == 0xd000
  308. && !thumb_pass_branch_condition(
  309. sim->get_cpsr(sim, 0, 32), opcode))
  310. {
  311. if (dry_run_pc)
  312. {
  313. *dry_run_pc = current_pc + instruction_size;
  314. }
  315. else
  316. {
  317. sim->set_reg(sim, 15, current_pc + instruction_size);
  318. }
  319. return ERROR_OK;
  320. }
  321. /* Deal with 32-bit BL/BLX */
  322. if ((opcode & 0xf800) == 0xf000) {
  323. uint32_t high = instruction.info.b_bl_bx_blx.target_address;
  324. retval = target_read_u16(target, current_pc+2, &opcode);
  325. if (retval != ERROR_OK)
  326. return retval;
  327. retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
  328. if (retval != ERROR_OK)
  329. return retval;
  330. instruction.info.b_bl_bx_blx.target_address += high;
  331. }
  332. }
  333. /* examine instruction type */
  334. /* branch instructions */
  335. if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
  336. {
  337. uint32_t target;
  338. if (instruction.info.b_bl_bx_blx.reg_operand == -1)
  339. {
  340. target = instruction.info.b_bl_bx_blx.target_address;
  341. }
  342. else
  343. {
  344. target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
  345. if (instruction.info.b_bl_bx_blx.reg_operand == 15)
  346. {
  347. target += 2 * instruction_size;
  348. }
  349. }
  350. if (dry_run_pc)
  351. {
  352. *dry_run_pc = target & ~1;
  353. return ERROR_OK;
  354. }
  355. else
  356. {
  357. if (instruction.type == ARM_B)
  358. {
  359. sim->set_reg(sim, 15, target);
  360. }
  361. else if (instruction.type == ARM_BL)
  362. {
  363. uint32_t old_pc = sim->get_reg(sim, 15);
  364. int T = (sim->get_state(sim) == ARM_STATE_THUMB);
  365. sim->set_reg_mode(sim, 14, old_pc + 4 + T);
  366. sim->set_reg(sim, 15, target);
  367. }
  368. else if (instruction.type == ARM_BX)
  369. {
  370. if (target & 0x1)
  371. {
  372. sim->set_state(sim, ARM_STATE_THUMB);
  373. }
  374. else
  375. {
  376. sim->set_state(sim, ARM_STATE_ARM);
  377. }
  378. sim->set_reg(sim, 15, target & 0xfffffffe);
  379. }
  380. else if (instruction.type == ARM_BLX)
  381. {
  382. uint32_t old_pc = sim->get_reg(sim, 15);
  383. int T = (sim->get_state(sim) == ARM_STATE_THUMB);
  384. sim->set_reg_mode(sim, 14, old_pc + 4 + T);
  385. if (target & 0x1)
  386. {
  387. sim->set_state(sim, ARM_STATE_THUMB);
  388. }
  389. else
  390. {
  391. sim->set_state(sim, ARM_STATE_ARM);
  392. }
  393. sim->set_reg(sim, 15, target & 0xfffffffe);
  394. }
  395. return ERROR_OK;
  396. }
  397. }
  398. /* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
  399. else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
  400. || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
  401. {
  402. uint32_t Rd, Rn, shifter_operand;
  403. uint8_t C = sim->get_cpsr(sim, 29, 1);
  404. uint8_t carry_out;
  405. Rd = 0x0;
  406. /* ARM_MOV and ARM_MVN does not use Rn */
  407. if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
  408. Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn);
  409. else
  410. Rn = 0;
  411. shifter_operand = arm_shifter_operand(sim,
  412. instruction.info.data_proc.variant,
  413. instruction.info.data_proc.shifter_operand,
  414. &carry_out);
  415. /* adjust Rn in case the PC is being read */
  416. if (instruction.info.data_proc.Rn == 15)
  417. Rn += 2 * instruction_size;
  418. if (instruction.type == ARM_AND)
  419. Rd = Rn & shifter_operand;
  420. else if (instruction.type == ARM_EOR)
  421. Rd = Rn ^ shifter_operand;
  422. else if (instruction.type == ARM_SUB)
  423. Rd = Rn - shifter_operand;
  424. else if (instruction.type == ARM_RSB)
  425. Rd = shifter_operand - Rn;
  426. else if (instruction.type == ARM_ADD)
  427. Rd = Rn + shifter_operand;
  428. else if (instruction.type == ARM_ADC)
  429. Rd = Rn + shifter_operand + (C & 1);
  430. else if (instruction.type == ARM_SBC)
  431. Rd = Rn - shifter_operand - (C & 1) ? 0 : 1;
  432. else if (instruction.type == ARM_RSC)
  433. Rd = shifter_operand - Rn - (C & 1) ? 0 : 1;
  434. else if (instruction.type == ARM_ORR)
  435. Rd = Rn | shifter_operand;
  436. else if (instruction.type == ARM_BIC)
  437. Rd = Rn & ~(shifter_operand);
  438. else if (instruction.type == ARM_MOV)
  439. Rd = shifter_operand;
  440. else if (instruction.type == ARM_MVN)
  441. Rd = ~shifter_operand;
  442. else
  443. LOG_WARNING("unhandled instruction type");
  444. if (dry_run_pc)
  445. {
  446. if (instruction.info.data_proc.Rd == 15)
  447. *dry_run_pc = Rd & ~1;
  448. else
  449. *dry_run_pc = current_pc + instruction_size;
  450. return ERROR_OK;
  451. }
  452. else
  453. {
  454. if (instruction.info.data_proc.Rd == 15) {
  455. sim->set_reg_mode(sim, 15, Rd & ~1);
  456. if (Rd & 1)
  457. sim->set_state(sim, ARM_STATE_THUMB);
  458. else
  459. sim->set_state(sim, ARM_STATE_ARM);
  460. return ERROR_OK;
  461. }
  462. sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
  463. LOG_WARNING("no updating of flags yet");
  464. }
  465. }
  466. /* compare instructions (CMP, CMN, TST, TEQ) */
  467. else if ((instruction.type >= ARM_TST) && (instruction.type <= ARM_CMN))
  468. {
  469. if (dry_run_pc)
  470. {
  471. *dry_run_pc = current_pc + instruction_size;
  472. return ERROR_OK;
  473. }
  474. else
  475. {
  476. LOG_WARNING("no updating of flags yet");
  477. }
  478. }
  479. /* load register instructions */
  480. else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
  481. {
  482. uint32_t load_address = 0, modified_address = 0, load_value;
  483. uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
  484. /* adjust Rn in case the PC is being read */
  485. if (instruction.info.load_store.Rn == 15)
  486. Rn += 2 * instruction_size;
  487. if (instruction.info.load_store.offset_mode == 0)
  488. {
  489. if (instruction.info.load_store.U)
  490. modified_address = Rn + instruction.info.load_store.offset.offset;
  491. else
  492. modified_address = Rn - instruction.info.load_store.offset.offset;
  493. }
  494. else if (instruction.info.load_store.offset_mode == 1)
  495. {
  496. uint32_t offset;
  497. uint32_t Rm = sim->get_reg_mode(sim,
  498. instruction.info.load_store.offset.reg.Rm);
  499. uint8_t shift = instruction.info.load_store.offset.reg.shift;
  500. uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
  501. uint8_t carry = sim->get_cpsr(sim, 29, 1);
  502. offset = arm_shift(shift, Rm, shift_imm, &carry);
  503. if (instruction.info.load_store.U)
  504. modified_address = Rn + offset;
  505. else
  506. modified_address = Rn - offset;
  507. }
  508. else
  509. {
  510. LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
  511. }
  512. if (instruction.info.load_store.index_mode == 0)
  513. {
  514. /* offset mode
  515. * we load from the modified address, but don't change
  516. * the base address register
  517. */
  518. load_address = modified_address;
  519. modified_address = Rn;
  520. }
  521. else if (instruction.info.load_store.index_mode == 1)
  522. {
  523. /* pre-indexed mode
  524. * we load from the modified address, and write it
  525. * back to the base address register
  526. */
  527. load_address = modified_address;
  528. }
  529. else if (instruction.info.load_store.index_mode == 2)
  530. {
  531. /* post-indexed mode
  532. * we load from the unmodified address, and write the
  533. * modified address back
  534. */
  535. load_address = Rn;
  536. }
  537. if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
  538. {
  539. retval = target_read_u32(target, load_address, &load_value);
  540. if (retval != ERROR_OK)
  541. return retval;
  542. }
  543. if (dry_run_pc)
  544. {
  545. if (instruction.info.load_store.Rd == 15)
  546. *dry_run_pc = load_value & ~1;
  547. else
  548. *dry_run_pc = current_pc + instruction_size;
  549. return ERROR_OK;
  550. }
  551. else
  552. {
  553. if ((instruction.info.load_store.index_mode == 1) ||
  554. (instruction.info.load_store.index_mode == 2))
  555. {
  556. sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
  557. }
  558. if (instruction.info.load_store.Rd == 15) {
  559. sim->set_reg_mode(sim, 15, load_value & ~1);
  560. if (load_value & 1)
  561. sim->set_state(sim, ARM_STATE_THUMB);
  562. else
  563. sim->set_state(sim, ARM_STATE_ARM);
  564. return ERROR_OK;
  565. }
  566. sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
  567. }
  568. }
  569. /* load multiple instruction */
  570. else if (instruction.type == ARM_LDM)
  571. {
  572. int i;
  573. uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
  574. uint32_t load_values[16];
  575. int bits_set = 0;
  576. for (i = 0; i < 16; i++)
  577. {
  578. if (instruction.info.load_store_multiple.register_list & (1 << i))
  579. bits_set++;
  580. }
  581. switch (instruction.info.load_store_multiple.addressing_mode)
  582. {
  583. case 0: /* Increment after */
  584. Rn = Rn;
  585. break;
  586. case 1: /* Increment before */
  587. Rn = Rn + 4;
  588. break;
  589. case 2: /* Decrement after */
  590. Rn = Rn - (bits_set * 4) + 4;
  591. break;
  592. case 3: /* Decrement before */
  593. Rn = Rn - (bits_set * 4);
  594. break;
  595. }
  596. for (i = 0; i < 16; i++)
  597. {
  598. if (instruction.info.load_store_multiple.register_list & (1 << i))
  599. {
  600. if ((!dry_run_pc) || (i == 15))
  601. {
  602. target_read_u32(target, Rn, &load_values[i]);
  603. }
  604. Rn += 4;
  605. }
  606. }
  607. if (dry_run_pc)
  608. {
  609. if (instruction.info.load_store_multiple.register_list & 0x8000)
  610. {
  611. *dry_run_pc = load_values[15] & ~1;
  612. return ERROR_OK;
  613. }
  614. }
  615. else
  616. {
  617. enum arm_mode mode = sim->get_mode(sim);
  618. int update_cpsr = 0;
  619. if (instruction.info.load_store_multiple.S)
  620. {
  621. if (instruction.info.load_store_multiple.register_list & 0x8000)
  622. update_cpsr = 1;
  623. else
  624. mode = ARM_MODE_USR;
  625. }
  626. for (i = 0; i < 16; i++)
  627. {
  628. if (instruction.info.load_store_multiple.register_list & (1 << i))
  629. {
  630. if (i == 15) {
  631. uint32_t val = load_values[i];
  632. sim->set_reg_mode(sim, i, val & ~1);
  633. if (val & 1)
  634. sim->set_state(sim, ARM_STATE_THUMB);
  635. else
  636. sim->set_state(sim, ARM_STATE_ARM);
  637. } else {
  638. sim->set_reg_mode(sim, i, load_values[i]);
  639. }
  640. }
  641. }
  642. if (update_cpsr)
  643. {
  644. uint32_t spsr = sim->get_reg_mode(sim, 16);
  645. sim->set_reg(sim, ARMV4_5_CPSR, spsr);
  646. }
  647. /* base register writeback */
  648. if (instruction.info.load_store_multiple.W)
  649. sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
  650. if (instruction.info.load_store_multiple.register_list & 0x8000)
  651. return ERROR_OK;
  652. }
  653. }
  654. /* store multiple instruction */
  655. else if (instruction.type == ARM_STM)
  656. {
  657. int i;
  658. if (dry_run_pc)
  659. {
  660. /* STM wont affect PC (advance by instruction size */
  661. }
  662. else
  663. {
  664. uint32_t Rn = sim->get_reg_mode(sim,
  665. instruction.info.load_store_multiple.Rn);
  666. int bits_set = 0;
  667. enum arm_mode mode = sim->get_mode(sim);
  668. for (i = 0; i < 16; i++)
  669. {
  670. if (instruction.info.load_store_multiple.register_list & (1 << i))
  671. bits_set++;
  672. }
  673. if (instruction.info.load_store_multiple.S)
  674. {
  675. mode = ARM_MODE_USR;
  676. }
  677. switch (instruction.info.load_store_multiple.addressing_mode)
  678. {
  679. case 0: /* Increment after */
  680. Rn = Rn;
  681. break;
  682. case 1: /* Increment before */
  683. Rn = Rn + 4;
  684. break;
  685. case 2: /* Decrement after */
  686. Rn = Rn - (bits_set * 4) + 4;
  687. break;
  688. case 3: /* Decrement before */
  689. Rn = Rn - (bits_set * 4);
  690. break;
  691. }
  692. for (i = 0; i < 16; i++)
  693. {
  694. if (instruction.info.load_store_multiple.register_list & (1 << i))
  695. {
  696. target_write_u32(target, Rn, sim->get_reg_mode(sim, i));
  697. Rn += 4;
  698. }
  699. }
  700. /* base register writeback */
  701. if (instruction.info.load_store_multiple.W)
  702. sim->set_reg_mode(sim,
  703. instruction.info.load_store_multiple.Rn, Rn);
  704. }
  705. }
  706. else if (!dry_run_pc)
  707. {
  708. /* the instruction wasn't handled, but we're supposed to simulate it
  709. */
  710. LOG_ERROR("Unimplemented instruction, could not simulate it.");
  711. return ERROR_FAIL;
  712. }
  713. if (dry_run_pc)
  714. {
  715. *dry_run_pc = current_pc + instruction_size;
  716. return ERROR_OK;
  717. }
  718. else
  719. {
  720. sim->set_reg(sim, 15, current_pc + instruction_size);
  721. return ERROR_OK;
  722. }
  723. }
  724. static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
  725. {
  726. struct arm *armv4_5 = (struct arm *)sim->user_data;
  727. return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
  728. }
  729. static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
  730. {
  731. struct arm *armv4_5 = (struct arm *)sim->user_data;
  732. buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
  733. }
  734. static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
  735. {
  736. struct arm *armv4_5 = (struct arm *)sim->user_data;
  737. return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
  738. armv4_5->core_mode, reg).value, 0, 32);
  739. }
  740. static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
  741. {
  742. struct arm *armv4_5 = (struct arm *)sim->user_data;
  743. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
  744. armv4_5->core_mode, reg).value, 0, 32, value);
  745. }
  746. static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
  747. {
  748. struct arm *armv4_5 = (struct arm *)sim->user_data;
  749. return buf_get_u32(armv4_5->cpsr->value, pos, bits);
  750. }
  751. static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
  752. {
  753. struct arm *armv4_5 = (struct arm *)sim->user_data;
  754. return armv4_5->core_state;
  755. }
  756. static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
  757. {
  758. struct arm *armv4_5 = (struct arm *)sim->user_data;
  759. armv4_5->core_state = mode;
  760. }
  761. static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
  762. {
  763. struct arm *armv4_5 = (struct arm *)sim->user_data;
  764. return armv4_5->core_mode;
  765. }
  766. int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
  767. {
  768. struct arm *armv4_5 = target_to_arm(target);
  769. struct arm_sim_interface sim;
  770. sim.user_data = armv4_5;
  771. sim.get_reg = &armv4_5_get_reg;
  772. sim.set_reg = &armv4_5_set_reg;
  773. sim.get_reg_mode = &armv4_5_get_reg_mode;
  774. sim.set_reg_mode = &armv4_5_set_reg_mode;
  775. sim.get_cpsr = &armv4_5_get_cpsr;
  776. sim.get_mode = &armv4_5_get_mode;
  777. sim.get_state = &armv4_5_get_state;
  778. sim.set_state = &armv4_5_set_state;
  779. return arm_simulate_step_core(target, dry_run_pc, &sim);
  780. }