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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifndef ARMV4_5_CACHE_H
  21. #define ARMV4_5_CACHE_H
  22. #include <helper/types.h>
  23. struct command_context;
  24. struct armv4_5_cachesize
  25. {
  26. int linelen;
  27. int associativity;
  28. int nsets;
  29. int cachesize;
  30. };
  31. struct armv4_5_cache_common
  32. {
  33. int ctype; /* specify supported cache operations */
  34. int separate; /* separate caches or unified cache */
  35. struct armv4_5_cachesize d_u_size; /* data cache */
  36. struct armv4_5_cachesize i_size; /* instruction cache */
  37. int i_cache_enabled;
  38. int d_u_cache_enabled;
  39. };
  40. int armv4_5_identify_cache(uint32_t cache_type_reg,
  41. struct armv4_5_cache_common *cache);
  42. int armv4_5_cache_state(uint32_t cp15_control_reg,
  43. struct armv4_5_cache_common *cache);
  44. int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
  45. struct armv4_5_cache_common *armv4_5_cache);
  46. enum
  47. {
  48. ARMV4_5_D_U_CACHE_ENABLED = 0x4,
  49. ARMV4_5_I_CACHE_ENABLED = 0x1000,
  50. ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
  51. ARMV4_5_CACHE_RR_BIT = 0x5000,
  52. };
  53. #endif /* ARMV4_5_CACHE_H */