You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

173 lines
5.9 KiB

  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include <helper/log.h>
  24. #include "target.h"
  25. #include "armv4_5_mmu.h"
  26. uint32_t armv4mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap);
  27. char* armv4_5_mmu_page_type_names[] =
  28. {
  29. "section", "large page", "small page", "tiny page"
  30. };
  31. uint32_t armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
  32. {
  33. uint32_t first_lvl_descriptor = 0x0;
  34. uint32_t second_lvl_descriptor = 0x0;
  35. uint32_t ttb = armv4_5_mmu->get_ttb(target);
  36. armv4_5_mmu_read_physical(target, armv4_5_mmu,
  37. (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  38. 4, 1, (uint8_t*)&first_lvl_descriptor);
  39. first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  40. LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  41. if ((first_lvl_descriptor & 0x3) == 0)
  42. {
  43. *type = -1;
  44. LOG_ERROR("Address translation failure");
  45. return ERROR_TARGET_TRANSLATION_FAULT;
  46. }
  47. if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  48. {
  49. *type = -1;
  50. LOG_ERROR("Address translation failure");
  51. return ERROR_TARGET_TRANSLATION_FAULT;
  52. }
  53. /* domain is always specified in bits 8-5 */
  54. *domain = (first_lvl_descriptor & 0x1e0) >> 5;
  55. if ((first_lvl_descriptor & 0x3) == 2)
  56. {
  57. /* section descriptor */
  58. *type = ARMV4_5_SECTION;
  59. *cb = (first_lvl_descriptor & 0xc) >> 2;
  60. *ap = (first_lvl_descriptor & 0xc00) >> 10;
  61. return (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  62. }
  63. if ((first_lvl_descriptor & 0x3) == 1)
  64. {
  65. /* coarse page table */
  66. armv4_5_mmu_read_physical(target, armv4_5_mmu,
  67. (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  68. 4, 1, (uint8_t*)&second_lvl_descriptor);
  69. }
  70. else if ((first_lvl_descriptor & 0x3) == 3)
  71. {
  72. /* fine page table */
  73. armv4_5_mmu_read_physical(target, armv4_5_mmu,
  74. (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  75. 4, 1, (uint8_t*)&second_lvl_descriptor);
  76. }
  77. second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  78. LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  79. if ((second_lvl_descriptor & 0x3) == 0)
  80. {
  81. *type = -1;
  82. LOG_ERROR("Address translation failure");
  83. return ERROR_TARGET_TRANSLATION_FAULT;
  84. }
  85. /* cacheable/bufferable is always specified in bits 3-2 */
  86. *cb = (second_lvl_descriptor & 0xc) >> 2;
  87. if ((second_lvl_descriptor & 0x3) == 1)
  88. {
  89. /* large page descriptor */
  90. *type = ARMV4_5_LARGE_PAGE;
  91. *ap = (second_lvl_descriptor & 0xff0) >> 4;
  92. return (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
  93. }
  94. if ((second_lvl_descriptor & 0x3) == 2)
  95. {
  96. /* small page descriptor */
  97. *type = ARMV4_5_SMALL_PAGE;
  98. *ap = (second_lvl_descriptor & 0xff0) >> 4;
  99. return (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
  100. }
  101. if ((second_lvl_descriptor & 0x3) == 3)
  102. {
  103. /* tiny page descriptor */
  104. *type = ARMV4_5_TINY_PAGE;
  105. *ap = (second_lvl_descriptor & 0x30) >> 4;
  106. return (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
  107. }
  108. /* should not happen */
  109. *type = -1;
  110. LOG_ERROR("Address translation failure");
  111. return ERROR_TARGET_TRANSLATION_FAULT;
  112. }
  113. int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  114. {
  115. int retval;
  116. if (target->state != TARGET_HALTED)
  117. return ERROR_TARGET_NOT_HALTED;
  118. /* disable MMU and data (or unified) cache */
  119. armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
  120. retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
  121. /* reenable MMU / cache */
  122. armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
  123. armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
  124. armv4_5_mmu->armv4_5_cache.i_cache_enabled);
  125. return retval;
  126. }
  127. int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  128. {
  129. int retval;
  130. if (target->state != TARGET_HALTED)
  131. return ERROR_TARGET_NOT_HALTED;
  132. /* disable MMU and data (or unified) cache */
  133. armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
  134. retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
  135. /* reenable MMU / cache */
  136. armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
  137. armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
  138. armv4_5_mmu->armv4_5_cache.i_cache_enabled);
  139. return retval;
  140. }