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  1. /***************************************************************************
  2. * Copyright (C) 2009 by David Brownell *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc., *
  17. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  18. ***************************************************************************/
  19. #ifndef ARMV7A_H
  20. #define ARMV7A_H
  21. #include "arm_adi_v5.h"
  22. #include "arm.h"
  23. #include "armv4_5_mmu.h"
  24. #include "armv4_5_cache.h"
  25. #include "arm_dpm.h"
  26. enum
  27. {
  28. ARM_PC = 15,
  29. ARM_CPSR = 16
  30. }
  31. ;
  32. #define ARMV7_COMMON_MAGIC 0x0A450999
  33. /* VA to PA translation operations opc2 values*/
  34. #define V2PCWPR 0
  35. #define V2PCWPW 1
  36. #define V2PCWUR 2
  37. #define V2PCWUW 3
  38. #define V2POWPR 4
  39. #define V2POWPW 5
  40. #define V2POWUR 6
  41. #define V2POWUW 7
  42. struct armv7a_common
  43. {
  44. struct arm armv4_5_common;
  45. int common_magic;
  46. struct reg_cache *core_cache;
  47. /* arm adp debug port */
  48. struct swjdp_common swjdp_info;
  49. /* Core Debug Unit */
  50. struct arm_dpm dpm;
  51. uint32_t debug_base;
  52. uint8_t debug_ap;
  53. uint8_t memory_ap;
  54. /* Cache and Memory Management Unit */
  55. struct armv4_5_mmu_common armv4_5_mmu;
  56. int (*examine_debug_reason)(struct target *target);
  57. void (*post_debug_entry)(struct target *target);
  58. void (*pre_restore_context)(struct target *target);
  59. void (*post_restore_context)(struct target *target);
  60. };
  61. static inline struct armv7a_common *
  62. target_to_armv7a(struct target *target)
  63. {
  64. return container_of(target->arch_info, struct armv7a_common,
  65. armv4_5_common);
  66. }
  67. /* register offsets from armv7a.debug_base */
  68. /* See ARMv7a arch spec section C10.2 */
  69. #define CPUDBG_DIDR 0x000
  70. /* See ARMv7a arch spec section C10.3 */
  71. #define CPUDBG_WFAR 0x018
  72. /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
  73. #define CPUDBG_DSCR 0x088
  74. #define CPUDBG_DRCR 0x090
  75. #define CPUDBG_PRCR 0x310
  76. #define CPUDBG_PRSR 0x314
  77. /* See ARMv7a arch spec section C10.4 */
  78. #define CPUDBG_DTRRX 0x080
  79. #define CPUDBG_ITR 0x084
  80. #define CPUDBG_DTRTX 0x08c
  81. /* See ARMv7a arch spec section C10.5 */
  82. #define CPUDBG_BVR_BASE 0x100
  83. #define CPUDBG_BCR_BASE 0x140
  84. #define CPUDBG_WVR_BASE 0x180
  85. #define CPUDBG_WCR_BASE 0x1C0
  86. #define CPUDBG_VCR 0x01C
  87. /* See ARMv7a arch spec section C10.6 */
  88. #define CPUDBG_OSLAR 0x300
  89. #define CPUDBG_OSLSR 0x304
  90. #define CPUDBG_OSSRR 0x308
  91. #define CPUDBG_ECR 0x024
  92. /* See ARMv7a arch spec section C10.7 */
  93. #define CPUDBG_DSCCR 0x028
  94. /* See ARMv7a arch spec section C10.8 */
  95. #define CPUDBG_AUTHSTATUS 0xFB8
  96. int armv7a_arch_state(struct target *target);
  97. struct reg_cache *armv7a_build_reg_cache(struct target *target,
  98. struct armv7a_common *armv7a_common);
  99. int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
  100. extern const struct command_registration armv7a_command_handlers[];
  101. #endif /* ARMV4_5_H */