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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * Copyright (C) 2009 by Dirk Behme *
  12. * dirk.behme@gmail.com - copy from cortex_m3 *
  13. * *
  14. * This program is free software; you can redistribute it and/or modify *
  15. * it under the terms of the GNU General Public License as published by *
  16. * the Free Software Foundation; either version 2 of the License, or *
  17. * (at your option) any later version. *
  18. * *
  19. * This program is distributed in the hope that it will be useful, *
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  22. * GNU General Public License for more details. *
  23. * *
  24. * You should have received a copy of the GNU General Public License *
  25. * along with this program; if not, write to the *
  26. * Free Software Foundation, Inc., *
  27. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  28. ***************************************************************************/
  29. #ifndef CORTEX_A8_H
  30. #define CORTEX_A8_H
  31. #include "armv7a.h"
  32. #define CORTEX_A8_COMMON_MAGIC 0x411fc082
  33. /* See Cortex-A8 TRM section 12.5 */
  34. #define CPUDBG_CPUID 0xD00
  35. #define CPUDBG_CTYPR 0xD04
  36. #define CPUDBG_TTYPR 0xD0C
  37. #define CPUDBG_LOCKACCESS 0xFB0
  38. #define CPUDBG_LOCKSTATUS 0xFB4
  39. #define BRP_NORMAL 0
  40. #define BRP_CONTEXT 1
  41. struct cortex_a8_brp
  42. {
  43. int used;
  44. int type;
  45. uint32_t value;
  46. uint32_t control;
  47. uint8_t BRPn;
  48. };
  49. struct cortex_a8_common
  50. {
  51. int common_magic;
  52. struct arm_jtag jtag_info;
  53. /* Context information */
  54. uint32_t cpudbg_dscr;
  55. /* Saved cp15 registers */
  56. uint32_t cp15_control_reg;
  57. /* Breakpoint register pairs */
  58. int brp_num_context;
  59. int brp_num;
  60. int brp_num_available;
  61. struct cortex_a8_brp *brp_list;
  62. /* Use cortex_a8_read_regs_through_mem for fast register reads */
  63. int fast_reg_read;
  64. struct armv7a_common armv7a_common;
  65. };
  66. static inline struct cortex_a8_common *
  67. target_to_cortex_a8(struct target *target)
  68. {
  69. return container_of(target->arch_info, struct cortex_a8_common,
  70. armv7a_common.armv4_5_common);
  71. }
  72. #endif /* CORTEX_A8_H */