You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

2063 lines
56 KiB

  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. * *
  26. * *
  27. * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
  28. * *
  29. ***************************************************************************/
  30. #ifdef HAVE_CONFIG_H
  31. #include "config.h"
  32. #endif
  33. #include "breakpoints.h"
  34. #include "cortex_m3.h"
  35. #include "target_request.h"
  36. #include "target_type.h"
  37. #include "arm_disassembler.h"
  38. #include "register.h"
  39. #include "arm_opcodes.h"
  40. /* NOTE: most of this should work fine for the Cortex-M1 and
  41. * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  42. * Some differences: M0/M1 doesn't have FBP remapping or the
  43. * DWT tracing/profiling support. (So the cycle counter will
  44. * not be usable; the other stuff isn't currently used here.)
  45. *
  46. * Although there are some workarounds for errata seen only in r0p0
  47. * silicon, such old parts are hard to find and thus not much tested
  48. * any longer.
  49. */
  50. /* forward declarations */
  51. static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  52. static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  53. static void cortex_m3_enable_watchpoints(struct target *target);
  54. static int cortex_m3_store_core_reg_u32(struct target *target,
  55. enum armv7m_regtype type, uint32_t num, uint32_t value);
  56. static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
  57. uint32_t *value, int regnum)
  58. {
  59. int retval;
  60. uint32_t dcrdr;
  61. /* because the DCB_DCRDR is used for the emulated dcc channel
  62. * we have to save/restore the DCB_DCRDR when used */
  63. mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  64. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65. /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  66. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  67. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  68. /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  69. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  70. dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  71. retval = swjdp_transaction_endcheck(swjdp);
  72. /* restore DCB_DCRDR - this needs to be in a seperate
  73. * transaction otherwise the emulated DCC channel breaks */
  74. if (retval == ERROR_OK)
  75. retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  76. return retval;
  77. }
  78. static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
  79. uint32_t value, int regnum)
  80. {
  81. int retval;
  82. uint32_t dcrdr;
  83. /* because the DCB_DCRDR is used for the emulated dcc channel
  84. * we have to save/restore the DCB_DCRDR when used */
  85. mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  86. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  87. /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
  88. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  89. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  90. /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
  91. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  92. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
  93. retval = swjdp_transaction_endcheck(swjdp);
  94. /* restore DCB_DCRDR - this needs to be in a seperate
  95. * transaction otherwise the emulated DCC channel breaks */
  96. if (retval == ERROR_OK)
  97. retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  98. return retval;
  99. }
  100. static int cortex_m3_write_debug_halt_mask(struct target *target,
  101. uint32_t mask_on, uint32_t mask_off)
  102. {
  103. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  104. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  105. /* mask off status bits */
  106. cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
  107. /* create new register mask */
  108. cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
  109. return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
  110. }
  111. static int cortex_m3_clear_halt(struct target *target)
  112. {
  113. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  114. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  115. /* clear step if any */
  116. cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
  117. /* Read Debug Fault Status Register */
  118. mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
  119. /* Clear Debug Fault Status */
  120. mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
  121. LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
  122. return ERROR_OK;
  123. }
  124. static int cortex_m3_single_step_core(struct target *target)
  125. {
  126. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  127. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  128. uint32_t dhcsr_save;
  129. /* backup dhcsr reg */
  130. dhcsr_save = cortex_m3->dcb_dhcsr;
  131. /* Mask interrupts before clearing halt, if done already. This avoids
  132. * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
  133. * HALT can put the core into an unknown state.
  134. */
  135. if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
  136. mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
  137. DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
  138. mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
  139. DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
  140. LOG_DEBUG(" ");
  141. /* restore dhcsr reg */
  142. cortex_m3->dcb_dhcsr = dhcsr_save;
  143. cortex_m3_clear_halt(target);
  144. return ERROR_OK;
  145. }
  146. static int cortex_m3_endreset_event(struct target *target)
  147. {
  148. int i;
  149. uint32_t dcb_demcr;
  150. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  151. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  152. struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
  153. struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
  154. /* FIXME handling of DEMCR clobbers vector_catch config ... */
  155. mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
  156. LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
  157. /* this register is used for emulated dcc channel */
  158. mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
  159. /* Enable debug requests */
  160. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  161. if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
  162. mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
  163. /* clear any interrupt masking */
  164. cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
  165. /* Enable trace and DWT; trap hard and bus faults.
  166. *
  167. * REVISIT why trap those two? And why trash the vector_catch
  168. * config, instead of preserving it? Catching HARDERR and BUSERR
  169. * will interfere with code that handles those itself...
  170. */
  171. mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
  172. /* Monitor bus faults as such (instead of as generic HARDERR), but
  173. * leave memory management and usage faults disabled.
  174. *
  175. * REVISIT setting BUSFAULTENA interferes with code which relies
  176. * on the default setting. Why do it?
  177. */
  178. mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
  179. /* Paranoia: evidently some (early?) chips don't preserve all the
  180. * debug state (including FBP, DWT, etc) across reset...
  181. */
  182. /* Enable FPB */
  183. target_write_u32(target, FP_CTRL, 3);
  184. cortex_m3->fpb_enabled = 1;
  185. /* Restore FPB registers */
  186. for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
  187. {
  188. target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
  189. }
  190. /* Restore DWT registers */
  191. for (i = 0; i < cortex_m3->dwt_num_comp; i++)
  192. {
  193. target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
  194. dwt_list[i].comp);
  195. target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
  196. dwt_list[i].mask);
  197. target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
  198. dwt_list[i].function);
  199. }
  200. swjdp_transaction_endcheck(swjdp);
  201. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  202. /* make sure we have latest dhcsr flags */
  203. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  204. return ERROR_OK;
  205. }
  206. static int cortex_m3_examine_debug_reason(struct target *target)
  207. {
  208. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  209. /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
  210. /* only check the debug reason if we don't know it already */
  211. if ((target->debug_reason != DBG_REASON_DBGRQ)
  212. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  213. {
  214. if (cortex_m3->nvic_dfsr & DFSR_BKPT)
  215. {
  216. target->debug_reason = DBG_REASON_BREAKPOINT;
  217. if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
  218. target->debug_reason = DBG_REASON_WPTANDBKPT;
  219. }
  220. else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
  221. target->debug_reason = DBG_REASON_WATCHPOINT;
  222. else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
  223. target->debug_reason = DBG_REASON_BREAKPOINT;
  224. else /* EXTERNAL, HALTED */
  225. target->debug_reason = DBG_REASON_UNDEFINED;
  226. }
  227. return ERROR_OK;
  228. }
  229. static int cortex_m3_examine_exception_reason(struct target *target)
  230. {
  231. uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
  232. struct armv7m_common *armv7m = target_to_armv7m(target);
  233. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  234. mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
  235. switch (armv7m->exception_number)
  236. {
  237. case 2: /* NMI */
  238. break;
  239. case 3: /* Hard Fault */
  240. mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
  241. if (except_sr & 0x40000000)
  242. {
  243. mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
  244. }
  245. break;
  246. case 4: /* Memory Management */
  247. mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  248. mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
  249. break;
  250. case 5: /* Bus Fault */
  251. mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  252. mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
  253. break;
  254. case 6: /* Usage Fault */
  255. mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  256. break;
  257. case 11: /* SVCall */
  258. break;
  259. case 12: /* Debug Monitor */
  260. mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
  261. break;
  262. case 14: /* PendSV */
  263. break;
  264. case 15: /* SysTick */
  265. break;
  266. default:
  267. except_sr = 0;
  268. break;
  269. }
  270. swjdp_transaction_endcheck(swjdp);
  271. LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
  272. shcsr, except_sr, cfsr, except_ar);
  273. return ERROR_OK;
  274. }
  275. static int cortex_m3_debug_entry(struct target *target)
  276. {
  277. int i;
  278. uint32_t xPSR;
  279. int retval;
  280. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  281. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  282. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  283. struct reg *r;
  284. LOG_DEBUG(" ");
  285. cortex_m3_clear_halt(target);
  286. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  287. if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
  288. return retval;
  289. /* Examine target state and mode */
  290. /* First load register acessible through core debug port*/
  291. int num_regs = armv7m->core_cache->num_regs;
  292. for (i = 0; i < num_regs; i++)
  293. {
  294. if (!armv7m->core_cache->reg_list[i].valid)
  295. armv7m->read_core_reg(target, i);
  296. }
  297. r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
  298. xPSR = buf_get_u32(r->value, 0, 32);
  299. #ifdef ARMV7_GDB_HACKS
  300. /* FIXME this breaks on scan chains with more than one Cortex-M3.
  301. * Instead, each CM3 should have its own dummy value...
  302. */
  303. /* copy real xpsr reg for gdb, setting thumb bit */
  304. buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
  305. buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
  306. armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
  307. armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
  308. #endif
  309. /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
  310. if (xPSR & 0xf00)
  311. {
  312. r->dirty = r->valid;
  313. cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
  314. }
  315. /* Are we in an exception handler */
  316. if (xPSR & 0x1FF)
  317. {
  318. armv7m->core_mode = ARMV7M_MODE_HANDLER;
  319. armv7m->exception_number = (xPSR & 0x1FF);
  320. }
  321. else
  322. {
  323. armv7m->core_mode = buf_get_u32(armv7m->core_cache
  324. ->reg_list[ARMV7M_CONTROL].value, 0, 1);
  325. armv7m->exception_number = 0;
  326. }
  327. if (armv7m->exception_number)
  328. {
  329. cortex_m3_examine_exception_reason(target);
  330. }
  331. LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
  332. armv7m_mode_strings[armv7m->core_mode],
  333. *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
  334. target_state_name(target));
  335. if (armv7m->post_debug_entry)
  336. armv7m->post_debug_entry(target);
  337. return ERROR_OK;
  338. }
  339. static int cortex_m3_poll(struct target *target)
  340. {
  341. int retval;
  342. enum target_state prev_target_state = target->state;
  343. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  344. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  345. /* Read from Debug Halting Control and Status Register */
  346. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  347. if (retval != ERROR_OK)
  348. {
  349. target->state = TARGET_UNKNOWN;
  350. return retval;
  351. }
  352. if (cortex_m3->dcb_dhcsr & S_RESET_ST)
  353. {
  354. /* check if still in reset */
  355. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  356. if (cortex_m3->dcb_dhcsr & S_RESET_ST)
  357. {
  358. target->state = TARGET_RESET;
  359. return ERROR_OK;
  360. }
  361. }
  362. if (target->state == TARGET_RESET)
  363. {
  364. /* Cannot switch context while running so endreset is
  365. * called with target->state == TARGET_RESET
  366. */
  367. LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
  368. cortex_m3->dcb_dhcsr);
  369. cortex_m3_endreset_event(target);
  370. target->state = TARGET_RUNNING;
  371. prev_target_state = TARGET_RUNNING;
  372. }
  373. if (cortex_m3->dcb_dhcsr & S_HALT)
  374. {
  375. target->state = TARGET_HALTED;
  376. if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
  377. {
  378. if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
  379. return retval;
  380. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  381. }
  382. if (prev_target_state == TARGET_DEBUG_RUNNING)
  383. {
  384. LOG_DEBUG(" ");
  385. if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
  386. return retval;
  387. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  388. }
  389. }
  390. /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
  391. * How best to model low power modes?
  392. */
  393. if (target->state == TARGET_UNKNOWN)
  394. {
  395. /* check if processor is retiring instructions */
  396. if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
  397. {
  398. target->state = TARGET_RUNNING;
  399. return ERROR_OK;
  400. }
  401. }
  402. return ERROR_OK;
  403. }
  404. static int cortex_m3_halt(struct target *target)
  405. {
  406. LOG_DEBUG("target->state: %s",
  407. target_state_name(target));
  408. if (target->state == TARGET_HALTED)
  409. {
  410. LOG_DEBUG("target was already halted");
  411. return ERROR_OK;
  412. }
  413. if (target->state == TARGET_UNKNOWN)
  414. {
  415. LOG_WARNING("target was in unknown state when halt was requested");
  416. }
  417. if (target->state == TARGET_RESET)
  418. {
  419. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  420. {
  421. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  422. return ERROR_TARGET_FAILURE;
  423. }
  424. else
  425. {
  426. /* we came here in a reset_halt or reset_init sequence
  427. * debug entry was already prepared in cortex_m3_prepare_reset_halt()
  428. */
  429. target->debug_reason = DBG_REASON_DBGRQ;
  430. return ERROR_OK;
  431. }
  432. }
  433. /* Write to Debug Halting Control and Status Register */
  434. cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
  435. target->debug_reason = DBG_REASON_DBGRQ;
  436. return ERROR_OK;
  437. }
  438. static int cortex_m3_soft_reset_halt(struct target *target)
  439. {
  440. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  441. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  442. uint32_t dcb_dhcsr = 0;
  443. int retval, timeout = 0;
  444. /* Enter debug state on reset; see end_reset_event() */
  445. mem_ap_write_u32(swjdp, DCB_DEMCR,
  446. TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  447. /* Request a core-only reset */
  448. mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
  449. AIRCR_VECTKEY | AIRCR_VECTRESET);
  450. target->state = TARGET_RESET;
  451. /* registers are now invalid */
  452. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  453. while (timeout < 100)
  454. {
  455. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
  456. if (retval == ERROR_OK)
  457. {
  458. mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
  459. &cortex_m3->nvic_dfsr);
  460. if ((dcb_dhcsr & S_HALT)
  461. && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
  462. {
  463. LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
  464. "DFSR 0x%08x",
  465. (unsigned) dcb_dhcsr,
  466. (unsigned) cortex_m3->nvic_dfsr);
  467. cortex_m3_poll(target);
  468. /* FIXME restore user's vector catch config */
  469. return ERROR_OK;
  470. }
  471. else
  472. LOG_DEBUG("waiting for system reset-halt, "
  473. "DHCSR 0x%08x, %d ms",
  474. (unsigned) dcb_dhcsr, timeout);
  475. }
  476. timeout++;
  477. alive_sleep(1);
  478. }
  479. return ERROR_OK;
  480. }
  481. static void cortex_m3_enable_breakpoints(struct target *target)
  482. {
  483. struct breakpoint *breakpoint = target->breakpoints;
  484. /* set any pending breakpoints */
  485. while (breakpoint)
  486. {
  487. if (!breakpoint->set)
  488. cortex_m3_set_breakpoint(target, breakpoint);
  489. breakpoint = breakpoint->next;
  490. }
  491. }
  492. static int cortex_m3_resume(struct target *target, int current,
  493. uint32_t address, int handle_breakpoints, int debug_execution)
  494. {
  495. struct armv7m_common *armv7m = target_to_armv7m(target);
  496. struct breakpoint *breakpoint = NULL;
  497. uint32_t resume_pc;
  498. struct reg *r;
  499. if (target->state != TARGET_HALTED)
  500. {
  501. LOG_WARNING("target not halted");
  502. return ERROR_TARGET_NOT_HALTED;
  503. }
  504. if (!debug_execution)
  505. {
  506. target_free_all_working_areas(target);
  507. cortex_m3_enable_breakpoints(target);
  508. cortex_m3_enable_watchpoints(target);
  509. }
  510. if (debug_execution)
  511. {
  512. r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
  513. /* Disable interrupts */
  514. /* We disable interrupts in the PRIMASK register instead of
  515. * masking with C_MASKINTS. This is probably the same issue
  516. * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
  517. * in parallel with disabled interrupts can cause local faults
  518. * to not be taken.
  519. *
  520. * REVISIT this clearly breaks non-debug execution, since the
  521. * PRIMASK register state isn't saved/restored... workaround
  522. * by never resuming app code after debug execution.
  523. */
  524. buf_set_u32(r->value, 0, 1, 1);
  525. r->dirty = true;
  526. r->valid = true;
  527. /* Make sure we are in Thumb mode */
  528. r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
  529. buf_set_u32(r->value, 24, 1, 1);
  530. r->dirty = true;
  531. r->valid = true;
  532. }
  533. /* current = 1: continue on current pc, otherwise continue at <address> */
  534. r = armv7m->core_cache->reg_list + 15;
  535. if (!current)
  536. {
  537. buf_set_u32(r->value, 0, 32, address);
  538. r->dirty = true;
  539. r->valid = true;
  540. }
  541. resume_pc = buf_get_u32(r->value, 0, 32);
  542. armv7m_restore_context(target);
  543. /* the front-end may request us not to handle breakpoints */
  544. if (handle_breakpoints)
  545. {
  546. /* Single step past breakpoint at current address */
  547. if ((breakpoint = breakpoint_find(target, resume_pc)))
  548. {
  549. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
  550. breakpoint->address,
  551. breakpoint->unique_id);
  552. cortex_m3_unset_breakpoint(target, breakpoint);
  553. cortex_m3_single_step_core(target);
  554. cortex_m3_set_breakpoint(target, breakpoint);
  555. }
  556. }
  557. /* Restart core */
  558. cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
  559. target->debug_reason = DBG_REASON_NOTHALTED;
  560. /* registers are now invalid */
  561. register_cache_invalidate(armv7m->core_cache);
  562. if (!debug_execution)
  563. {
  564. target->state = TARGET_RUNNING;
  565. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  566. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  567. }
  568. else
  569. {
  570. target->state = TARGET_DEBUG_RUNNING;
  571. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  572. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  573. }
  574. return ERROR_OK;
  575. }
  576. /* int irqstepcount = 0; */
  577. static int cortex_m3_step(struct target *target, int current,
  578. uint32_t address, int handle_breakpoints)
  579. {
  580. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  581. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  582. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  583. struct breakpoint *breakpoint = NULL;
  584. struct reg *pc = armv7m->core_cache->reg_list + 15;
  585. if (target->state != TARGET_HALTED)
  586. {
  587. LOG_WARNING("target not halted");
  588. return ERROR_TARGET_NOT_HALTED;
  589. }
  590. /* current = 1: continue on current pc, otherwise continue at <address> */
  591. if (!current)
  592. buf_set_u32(pc->value, 0, 32, address);
  593. /* the front-end may request us not to handle breakpoints */
  594. if (handle_breakpoints) {
  595. breakpoint = breakpoint_find(target,
  596. buf_get_u32(pc->value, 0, 32));
  597. if (breakpoint)
  598. cortex_m3_unset_breakpoint(target, breakpoint);
  599. }
  600. target->debug_reason = DBG_REASON_SINGLESTEP;
  601. armv7m_restore_context(target);
  602. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  603. /* set step and clear halt */
  604. cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
  605. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  606. /* registers are now invalid */
  607. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  608. if (breakpoint)
  609. cortex_m3_set_breakpoint(target, breakpoint);
  610. LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
  611. " nvic_icsr = 0x%" PRIx32,
  612. cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
  613. cortex_m3_debug_entry(target);
  614. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  615. LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
  616. " nvic_icsr = 0x%" PRIx32,
  617. cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
  618. return ERROR_OK;
  619. }
  620. static int cortex_m3_assert_reset(struct target *target)
  621. {
  622. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  623. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  624. int assert_srst = 1;
  625. LOG_DEBUG("target->state: %s",
  626. target_state_name(target));
  627. enum reset_types jtag_reset_config = jtag_get_reset_config();
  628. /*
  629. * We can reset Cortex-M3 targets using just the NVIC without
  630. * requiring SRST, getting a SoC reset (or a core-only reset)
  631. * instead of a system reset.
  632. */
  633. if (!(jtag_reset_config & RESET_HAS_SRST))
  634. assert_srst = 0;
  635. /* Enable debug requests */
  636. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  637. if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
  638. mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
  639. mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
  640. if (!target->reset_halt)
  641. {
  642. /* Set/Clear C_MASKINTS in a separate operation */
  643. if (cortex_m3->dcb_dhcsr & C_MASKINTS)
  644. mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
  645. DBGKEY | C_DEBUGEN | C_HALT);
  646. /* clear any debug flags before resuming */
  647. cortex_m3_clear_halt(target);
  648. /* clear C_HALT in dhcsr reg */
  649. cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
  650. /* Enter debug state on reset, cf. end_reset_event() */
  651. mem_ap_write_u32(swjdp, DCB_DEMCR,
  652. TRCENA | VC_HARDERR | VC_BUSERR);
  653. }
  654. else
  655. {
  656. /* Enter debug state on reset, cf. end_reset_event() */
  657. mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
  658. TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  659. }
  660. /*
  661. * When nRST is asserted on most Stellaris devices, it clears some of
  662. * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
  663. * and OpenOCD depends on those TRMs. So we won't use SRST on those
  664. * chips. (Only power-on reset should affect debug state, beyond a
  665. * few specified bits; not the chip's nRST input, wired to SRST.)
  666. *
  667. * REVISIT current errata specs don't seem to cover this issue.
  668. * Do we have more details than this email?
  669. * https://lists.berlios.de/pipermail
  670. * /openocd-development/2008-August/003065.html
  671. */
  672. if (strcmp(target->variant, "lm3s") == 0)
  673. {
  674. /* Check for silicon revisions with the issue. */
  675. uint32_t did0;
  676. if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
  677. {
  678. switch ((did0 >> 16) & 0xff)
  679. {
  680. case 0:
  681. /* all Sandstorm suffer issue */
  682. assert_srst = 0;
  683. break;
  684. case 1:
  685. case 3:
  686. /* Fury and DustDevil rev A have
  687. * this nRST problem. It should
  688. * be fixed in rev B silicon.
  689. */
  690. if (((did0 >> 8) & 0xff) == 0)
  691. assert_srst = 0;
  692. break;
  693. case 4:
  694. /* Tempest should be fine. */
  695. break;
  696. }
  697. }
  698. }
  699. if (assert_srst)
  700. {
  701. /* default to asserting srst */
  702. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  703. {
  704. jtag_add_reset(1, 1);
  705. }
  706. else
  707. {
  708. jtag_add_reset(0, 1);
  709. }
  710. }
  711. else
  712. {
  713. /* Use a standard Cortex-M3 software reset mechanism.
  714. * SYSRESETREQ will reset SoC peripherals outside the
  715. * core, like watchdog timers, if the SoC wires it up
  716. * correctly. Else VECRESET can reset just the core.
  717. */
  718. mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
  719. AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
  720. LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
  721. {
  722. /* I do not know why this is necessary, but it
  723. * fixes strange effects (step/resume cause NMI
  724. * after reset) on LM3S6918 -- Michael Schwingen
  725. */
  726. uint32_t tmp;
  727. mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
  728. }
  729. }
  730. target->state = TARGET_RESET;
  731. jtag_add_sleep(50000);
  732. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  733. if (target->reset_halt)
  734. {
  735. int retval;
  736. if ((retval = target_halt(target)) != ERROR_OK)
  737. return retval;
  738. }
  739. return ERROR_OK;
  740. }
  741. static int cortex_m3_deassert_reset(struct target *target)
  742. {
  743. LOG_DEBUG("target->state: %s",
  744. target_state_name(target));
  745. /* deassert reset lines */
  746. jtag_add_reset(0, 0);
  747. return ERROR_OK;
  748. }
  749. static int
  750. cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
  751. {
  752. int retval;
  753. int fp_num = 0;
  754. uint32_t hilo;
  755. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  756. struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
  757. if (breakpoint->set)
  758. {
  759. LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
  760. return ERROR_OK;
  761. }
  762. if (cortex_m3->auto_bp_type)
  763. {
  764. breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
  765. }
  766. if (breakpoint->type == BKPT_HARD)
  767. {
  768. while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
  769. fp_num++;
  770. if (fp_num >= cortex_m3->fp_num_code)
  771. {
  772. LOG_ERROR("Can not find free FPB Comparator!");
  773. return ERROR_FAIL;
  774. }
  775. breakpoint->set = fp_num + 1;
  776. hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
  777. comparator_list[fp_num].used = 1;
  778. comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
  779. target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
  780. LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
  781. if (!cortex_m3->fpb_enabled)
  782. {
  783. LOG_DEBUG("FPB wasn't enabled, do it now");
  784. target_write_u32(target, FP_CTRL, 3);
  785. }
  786. }
  787. else if (breakpoint->type == BKPT_SOFT)
  788. {
  789. uint8_t code[4];
  790. /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
  791. * semihosting; don't use that. Otherwise the BKPT
  792. * parameter is arbitrary.
  793. */
  794. buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
  795. retval = target_read_memory(target,
  796. breakpoint->address & 0xFFFFFFFE,
  797. breakpoint->length, 1,
  798. breakpoint->orig_instr);
  799. if (retval != ERROR_OK)
  800. return retval;
  801. retval = target_write_memory(target,
  802. breakpoint->address & 0xFFFFFFFE,
  803. breakpoint->length, 1,
  804. code);
  805. if (retval != ERROR_OK)
  806. return retval;
  807. breakpoint->set = true;
  808. }
  809. LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
  810. breakpoint->unique_id,
  811. (int)(breakpoint->type),
  812. breakpoint->address,
  813. breakpoint->length,
  814. breakpoint->set);
  815. return ERROR_OK;
  816. }
  817. static int
  818. cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
  819. {
  820. int retval;
  821. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  822. struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
  823. if (!breakpoint->set)
  824. {
  825. LOG_WARNING("breakpoint not set");
  826. return ERROR_OK;
  827. }
  828. LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
  829. breakpoint->unique_id,
  830. (int)(breakpoint->type),
  831. breakpoint->address,
  832. breakpoint->length,
  833. breakpoint->set);
  834. if (breakpoint->type == BKPT_HARD)
  835. {
  836. int fp_num = breakpoint->set - 1;
  837. if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
  838. {
  839. LOG_DEBUG("Invalid FP Comparator number in breakpoint");
  840. return ERROR_OK;
  841. }
  842. comparator_list[fp_num].used = 0;
  843. comparator_list[fp_num].fpcr_value = 0;
  844. target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
  845. }
  846. else
  847. {
  848. /* restore original instruction (kept in target endianness) */
  849. if (breakpoint->length == 4)
  850. {
  851. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  852. {
  853. return retval;
  854. }
  855. }
  856. else
  857. {
  858. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  859. {
  860. return retval;
  861. }
  862. }
  863. }
  864. breakpoint->set = false;
  865. return ERROR_OK;
  866. }
  867. static int
  868. cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  869. {
  870. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  871. if (cortex_m3->auto_bp_type)
  872. {
  873. breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
  874. #ifdef ARMV7_GDB_HACKS
  875. if (breakpoint->length != 2) {
  876. /* XXX Hack: Replace all breakpoints with length != 2 with
  877. * a hardware breakpoint. */
  878. breakpoint->type = BKPT_HARD;
  879. breakpoint->length = 2;
  880. }
  881. #endif
  882. }
  883. if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
  884. {
  885. LOG_INFO("flash patch comparator requested outside code memory region");
  886. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  887. }
  888. if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
  889. {
  890. LOG_INFO("soft breakpoint requested in code (flash) memory region");
  891. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  892. }
  893. if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
  894. {
  895. LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
  896. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  897. }
  898. if ((breakpoint->length != 2))
  899. {
  900. LOG_INFO("only breakpoints of two bytes length supported");
  901. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  902. }
  903. if (breakpoint->type == BKPT_HARD)
  904. cortex_m3->fp_code_available--;
  905. cortex_m3_set_breakpoint(target, breakpoint);
  906. return ERROR_OK;
  907. }
  908. static int
  909. cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
  910. {
  911. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  912. /* REVISIT why check? FBP can be updated with core running ... */
  913. if (target->state != TARGET_HALTED)
  914. {
  915. LOG_WARNING("target not halted");
  916. return ERROR_TARGET_NOT_HALTED;
  917. }
  918. if (cortex_m3->auto_bp_type)
  919. {
  920. breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
  921. }
  922. if (breakpoint->set)
  923. {
  924. cortex_m3_unset_breakpoint(target, breakpoint);
  925. }
  926. if (breakpoint->type == BKPT_HARD)
  927. cortex_m3->fp_code_available++;
  928. return ERROR_OK;
  929. }
  930. static int
  931. cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
  932. {
  933. int dwt_num = 0;
  934. uint32_t mask, temp;
  935. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  936. /* watchpoint params were validated earlier */
  937. mask = 0;
  938. temp = watchpoint->length;
  939. while (temp) {
  940. temp >>= 1;
  941. mask++;
  942. }
  943. mask--;
  944. /* REVISIT Don't fully trust these "not used" records ... users
  945. * may set up breakpoints by hand, e.g. dual-address data value
  946. * watchpoint using comparator #1; comparator #0 matching cycle
  947. * count; send data trace info through ITM and TPIU; etc
  948. */
  949. struct cortex_m3_dwt_comparator *comparator;
  950. for (comparator = cortex_m3->dwt_comparator_list;
  951. comparator->used && dwt_num < cortex_m3->dwt_num_comp;
  952. comparator++, dwt_num++)
  953. continue;
  954. if (dwt_num >= cortex_m3->dwt_num_comp)
  955. {
  956. LOG_ERROR("Can not find free DWT Comparator");
  957. return ERROR_FAIL;
  958. }
  959. comparator->used = 1;
  960. watchpoint->set = dwt_num + 1;
  961. comparator->comp = watchpoint->address;
  962. target_write_u32(target, comparator->dwt_comparator_address + 0,
  963. comparator->comp);
  964. comparator->mask = mask;
  965. target_write_u32(target, comparator->dwt_comparator_address + 4,
  966. comparator->mask);
  967. switch (watchpoint->rw) {
  968. case WPT_READ:
  969. comparator->function = 5;
  970. break;
  971. case WPT_WRITE:
  972. comparator->function = 6;
  973. break;
  974. case WPT_ACCESS:
  975. comparator->function = 7;
  976. break;
  977. }
  978. target_write_u32(target, comparator->dwt_comparator_address + 8,
  979. comparator->function);
  980. LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
  981. watchpoint->unique_id, dwt_num,
  982. (unsigned) comparator->comp,
  983. (unsigned) comparator->mask,
  984. (unsigned) comparator->function);
  985. return ERROR_OK;
  986. }
  987. static int
  988. cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
  989. {
  990. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  991. struct cortex_m3_dwt_comparator *comparator;
  992. int dwt_num;
  993. if (!watchpoint->set)
  994. {
  995. LOG_WARNING("watchpoint (wpid: %d) not set",
  996. watchpoint->unique_id);
  997. return ERROR_OK;
  998. }
  999. dwt_num = watchpoint->set - 1;
  1000. LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
  1001. watchpoint->unique_id, dwt_num,
  1002. (unsigned) watchpoint->address);
  1003. if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
  1004. {
  1005. LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
  1006. return ERROR_OK;
  1007. }
  1008. comparator = cortex_m3->dwt_comparator_list + dwt_num;
  1009. comparator->used = 0;
  1010. comparator->function = 0;
  1011. target_write_u32(target, comparator->dwt_comparator_address + 8,
  1012. comparator->function);
  1013. watchpoint->set = false;
  1014. return ERROR_OK;
  1015. }
  1016. static int
  1017. cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  1018. {
  1019. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1020. if (cortex_m3->dwt_comp_available < 1)
  1021. {
  1022. LOG_DEBUG("no comparators?");
  1023. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1024. }
  1025. /* hardware doesn't support data value masking */
  1026. if (watchpoint->mask != ~(uint32_t)0) {
  1027. LOG_DEBUG("watchpoint value masks not supported");
  1028. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1029. }
  1030. /* hardware allows address masks of up to 32K */
  1031. unsigned mask;
  1032. for (mask = 0; mask < 16; mask++) {
  1033. if ((1u << mask) == watchpoint->length)
  1034. break;
  1035. }
  1036. if (mask == 16) {
  1037. LOG_DEBUG("unsupported watchpoint length");
  1038. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1039. }
  1040. if (watchpoint->address & ((1 << mask) - 1)) {
  1041. LOG_DEBUG("watchpoint address is unaligned");
  1042. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1043. }
  1044. /* Caller doesn't seem to be able to describe watching for data
  1045. * values of zero; that flags "no value".
  1046. *
  1047. * REVISIT This DWT may well be able to watch for specific data
  1048. * values. Requires comparator #1 to set DATAVMATCH and match
  1049. * the data, and another comparator (DATAVADDR0) matching addr.
  1050. */
  1051. if (watchpoint->value) {
  1052. LOG_DEBUG("data value watchpoint not YET supported");
  1053. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1054. }
  1055. cortex_m3->dwt_comp_available--;
  1056. LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
  1057. return ERROR_OK;
  1058. }
  1059. static int
  1060. cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
  1061. {
  1062. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1063. /* REVISIT why check? DWT can be updated with core running ... */
  1064. if (target->state != TARGET_HALTED)
  1065. {
  1066. LOG_WARNING("target not halted");
  1067. return ERROR_TARGET_NOT_HALTED;
  1068. }
  1069. if (watchpoint->set)
  1070. {
  1071. cortex_m3_unset_watchpoint(target, watchpoint);
  1072. }
  1073. cortex_m3->dwt_comp_available++;
  1074. LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
  1075. return ERROR_OK;
  1076. }
  1077. static void cortex_m3_enable_watchpoints(struct target *target)
  1078. {
  1079. struct watchpoint *watchpoint = target->watchpoints;
  1080. /* set any pending watchpoints */
  1081. while (watchpoint)
  1082. {
  1083. if (!watchpoint->set)
  1084. cortex_m3_set_watchpoint(target, watchpoint);
  1085. watchpoint = watchpoint->next;
  1086. }
  1087. }
  1088. static int cortex_m3_load_core_reg_u32(struct target *target,
  1089. enum armv7m_regtype type, uint32_t num, uint32_t * value)
  1090. {
  1091. int retval;
  1092. struct armv7m_common *armv7m = target_to_armv7m(target);
  1093. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1094. /* NOTE: we "know" here that the register identifiers used
  1095. * in the v7m header match the Cortex-M3 Debug Core Register
  1096. * Selector values for R0..R15, xPSR, MSP, and PSP.
  1097. */
  1098. switch (num) {
  1099. case 0 ... 18:
  1100. /* read a normal core register */
  1101. retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
  1102. if (retval != ERROR_OK)
  1103. {
  1104. LOG_ERROR("JTAG failure %i",retval);
  1105. return ERROR_JTAG_DEVICE_ERROR;
  1106. }
  1107. LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
  1108. break;
  1109. case ARMV7M_PRIMASK:
  1110. case ARMV7M_BASEPRI:
  1111. case ARMV7M_FAULTMASK:
  1112. case ARMV7M_CONTROL:
  1113. /* Cortex-M3 packages these four registers as bitfields
  1114. * in one Debug Core register. So say r0 and r2 docs;
  1115. * it was removed from r1 docs, but still works.
  1116. */
  1117. cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
  1118. switch (num)
  1119. {
  1120. case ARMV7M_PRIMASK:
  1121. *value = buf_get_u32((uint8_t*)value, 0, 1);
  1122. break;
  1123. case ARMV7M_BASEPRI:
  1124. *value = buf_get_u32((uint8_t*)value, 8, 8);
  1125. break;
  1126. case ARMV7M_FAULTMASK:
  1127. *value = buf_get_u32((uint8_t*)value, 16, 1);
  1128. break;
  1129. case ARMV7M_CONTROL:
  1130. *value = buf_get_u32((uint8_t*)value, 24, 2);
  1131. break;
  1132. }
  1133. LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
  1134. break;
  1135. default:
  1136. return ERROR_INVALID_ARGUMENTS;
  1137. }
  1138. return ERROR_OK;
  1139. }
  1140. static int cortex_m3_store_core_reg_u32(struct target *target,
  1141. enum armv7m_regtype type, uint32_t num, uint32_t value)
  1142. {
  1143. int retval;
  1144. uint32_t reg;
  1145. struct armv7m_common *armv7m = target_to_armv7m(target);
  1146. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1147. #ifdef ARMV7_GDB_HACKS
  1148. /* If the LR register is being modified, make sure it will put us
  1149. * in "thumb" mode, or an INVSTATE exception will occur. This is a
  1150. * hack to deal with the fact that gdb will sometimes "forge"
  1151. * return addresses, and doesn't set the LSB correctly (i.e., when
  1152. * printing expressions containing function calls, it sets LR = 0.)
  1153. * Valid exception return codes have bit 0 set too.
  1154. */
  1155. if (num == ARMV7M_R14)
  1156. value |= 0x01;
  1157. #endif
  1158. /* NOTE: we "know" here that the register identifiers used
  1159. * in the v7m header match the Cortex-M3 Debug Core Register
  1160. * Selector values for R0..R15, xPSR, MSP, and PSP.
  1161. */
  1162. switch (num) {
  1163. case 0 ... 18:
  1164. retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
  1165. if (retval != ERROR_OK)
  1166. {
  1167. struct reg *r;
  1168. LOG_ERROR("JTAG failure %i", retval);
  1169. r = armv7m->core_cache->reg_list + num;
  1170. r->dirty = r->valid;
  1171. return ERROR_JTAG_DEVICE_ERROR;
  1172. }
  1173. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
  1174. break;
  1175. case ARMV7M_PRIMASK:
  1176. case ARMV7M_BASEPRI:
  1177. case ARMV7M_FAULTMASK:
  1178. case ARMV7M_CONTROL:
  1179. /* Cortex-M3 packages these four registers as bitfields
  1180. * in one Debug Core register. So say r0 and r2 docs;
  1181. * it was removed from r1 docs, but still works.
  1182. */
  1183. cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
  1184. switch (num)
  1185. {
  1186. case ARMV7M_PRIMASK:
  1187. buf_set_u32((uint8_t*)&reg, 0, 1, value);
  1188. break;
  1189. case ARMV7M_BASEPRI:
  1190. buf_set_u32((uint8_t*)&reg, 8, 8, value);
  1191. break;
  1192. case ARMV7M_FAULTMASK:
  1193. buf_set_u32((uint8_t*)&reg, 16, 1, value);
  1194. break;
  1195. case ARMV7M_CONTROL:
  1196. buf_set_u32((uint8_t*)&reg, 24, 2, value);
  1197. break;
  1198. }
  1199. cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
  1200. LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
  1201. break;
  1202. default:
  1203. return ERROR_INVALID_ARGUMENTS;
  1204. }
  1205. return ERROR_OK;
  1206. }
  1207. static int cortex_m3_read_memory(struct target *target, uint32_t address,
  1208. uint32_t size, uint32_t count, uint8_t *buffer)
  1209. {
  1210. struct armv7m_common *armv7m = target_to_armv7m(target);
  1211. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1212. int retval = ERROR_INVALID_ARGUMENTS;
  1213. /* cortex_m3 handles unaligned memory access */
  1214. if (count && buffer) {
  1215. switch (size) {
  1216. case 4:
  1217. retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
  1218. break;
  1219. case 2:
  1220. retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
  1221. break;
  1222. case 1:
  1223. retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
  1224. break;
  1225. }
  1226. }
  1227. return retval;
  1228. }
  1229. static int cortex_m3_write_memory(struct target *target, uint32_t address,
  1230. uint32_t size, uint32_t count, uint8_t *buffer)
  1231. {
  1232. struct armv7m_common *armv7m = target_to_armv7m(target);
  1233. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1234. int retval = ERROR_INVALID_ARGUMENTS;
  1235. if (count && buffer) {
  1236. switch (size) {
  1237. case 4:
  1238. retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
  1239. break;
  1240. case 2:
  1241. retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
  1242. break;
  1243. case 1:
  1244. retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
  1245. break;
  1246. }
  1247. }
  1248. return retval;
  1249. }
  1250. static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
  1251. uint32_t count, uint8_t *buffer)
  1252. {
  1253. return cortex_m3_write_memory(target, address, 4, count, buffer);
  1254. }
  1255. static int cortex_m3_init_target(struct command_context *cmd_ctx,
  1256. struct target *target)
  1257. {
  1258. armv7m_build_reg_cache(target);
  1259. return ERROR_OK;
  1260. }
  1261. /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
  1262. * on r/w if the core is not running, and clear on resume or reset ... or
  1263. * at least, in a post_restore_context() method.
  1264. */
  1265. struct dwt_reg_state {
  1266. struct target *target;
  1267. uint32_t addr;
  1268. uint32_t value; /* scratch/cache */
  1269. };
  1270. static int cortex_m3_dwt_get_reg(struct reg *reg)
  1271. {
  1272. struct dwt_reg_state *state = reg->arch_info;
  1273. return target_read_u32(state->target, state->addr, &state->value);
  1274. }
  1275. static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
  1276. {
  1277. struct dwt_reg_state *state = reg->arch_info;
  1278. return target_write_u32(state->target, state->addr,
  1279. buf_get_u32(buf, 0, reg->size));
  1280. }
  1281. struct dwt_reg {
  1282. uint32_t addr;
  1283. char *name;
  1284. unsigned size;
  1285. };
  1286. static struct dwt_reg dwt_base_regs[] = {
  1287. { DWT_CTRL, "dwt_ctrl", 32, },
  1288. /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
  1289. * increments while the core is asleep.
  1290. */
  1291. { DWT_CYCCNT, "dwt_cyccnt", 32, },
  1292. /* plus some 8 bit counters, useful for profiling with TPIU */
  1293. };
  1294. static struct dwt_reg dwt_comp[] = {
  1295. #define DWT_COMPARATOR(i) \
  1296. { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
  1297. { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
  1298. { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
  1299. DWT_COMPARATOR(0),
  1300. DWT_COMPARATOR(1),
  1301. DWT_COMPARATOR(2),
  1302. DWT_COMPARATOR(3),
  1303. #undef DWT_COMPARATOR
  1304. };
  1305. static const struct reg_arch_type dwt_reg_type = {
  1306. .get = cortex_m3_dwt_get_reg,
  1307. .set = cortex_m3_dwt_set_reg,
  1308. };
  1309. static void
  1310. cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
  1311. {
  1312. struct dwt_reg_state *state;
  1313. state = calloc(1, sizeof *state);
  1314. if (!state)
  1315. return;
  1316. state->addr = d->addr;
  1317. state->target = t;
  1318. r->name = d->name;
  1319. r->size = d->size;
  1320. r->value = &state->value;
  1321. r->arch_info = state;
  1322. r->type = &dwt_reg_type;
  1323. }
  1324. static void
  1325. cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
  1326. {
  1327. uint32_t dwtcr;
  1328. struct reg_cache *cache;
  1329. struct cortex_m3_dwt_comparator *comparator;
  1330. int reg, i;
  1331. target_read_u32(target, DWT_CTRL, &dwtcr);
  1332. if (!dwtcr) {
  1333. LOG_DEBUG("no DWT");
  1334. return;
  1335. }
  1336. cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
  1337. cm3->dwt_comp_available = cm3->dwt_num_comp;
  1338. cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
  1339. sizeof(struct cortex_m3_dwt_comparator));
  1340. if (!cm3->dwt_comparator_list) {
  1341. fail0:
  1342. cm3->dwt_num_comp = 0;
  1343. LOG_ERROR("out of mem");
  1344. return;
  1345. }
  1346. cache = calloc(1, sizeof *cache);
  1347. if (!cache) {
  1348. fail1:
  1349. free(cm3->dwt_comparator_list);
  1350. goto fail0;
  1351. }
  1352. cache->name = "cortex-m3 dwt registers";
  1353. cache->num_regs = 2 + cm3->dwt_num_comp * 3;
  1354. cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
  1355. if (!cache->reg_list) {
  1356. free(cache);
  1357. goto fail1;
  1358. }
  1359. for (reg = 0; reg < 2; reg++)
  1360. cortex_m3_dwt_addreg(target, cache->reg_list + reg,
  1361. dwt_base_regs + reg);
  1362. comparator = cm3->dwt_comparator_list;
  1363. for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
  1364. int j;
  1365. comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
  1366. for (j = 0; j < 3; j++, reg++)
  1367. cortex_m3_dwt_addreg(target, cache->reg_list + reg,
  1368. dwt_comp + 3 * i + j);
  1369. }
  1370. *register_get_last_cache_p(&target->reg_cache) = cache;
  1371. cm3->dwt_cache = cache;
  1372. LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
  1373. dwtcr, cm3->dwt_num_comp,
  1374. (dwtcr & (0xf << 24)) ? " only" : "/trigger");
  1375. /* REVISIT: if num_comp > 1, check whether comparator #1 can
  1376. * implement single-address data value watchpoints ... so we
  1377. * won't need to check it later, when asked to set one up.
  1378. */
  1379. }
  1380. static int cortex_m3_examine(struct target *target)
  1381. {
  1382. int retval;
  1383. uint32_t cpuid, fpcr;
  1384. int i;
  1385. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1386. struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
  1387. if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
  1388. return retval;
  1389. if (!target_was_examined(target))
  1390. {
  1391. target_set_examined(target);
  1392. /* Read from Device Identification Registers */
  1393. retval = target_read_u32(target, CPUID, &cpuid);
  1394. if (retval != ERROR_OK)
  1395. return retval;
  1396. if (((cpuid >> 4) & 0xc3f) == 0xc23)
  1397. LOG_DEBUG("Cortex-M3 r%dp%d processor detected",
  1398. (cpuid >> 20) & 0xf, (cpuid >> 0) & 0xf);
  1399. LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
  1400. /* NOTE: FPB and DWT are both optional. */
  1401. /* Setup FPB */
  1402. target_read_u32(target, FP_CTRL, &fpcr);
  1403. cortex_m3->auto_bp_type = 1;
  1404. cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
  1405. cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
  1406. cortex_m3->fp_code_available = cortex_m3->fp_num_code;
  1407. cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
  1408. cortex_m3->fpb_enabled = fpcr & 1;
  1409. for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
  1410. {
  1411. cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
  1412. cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
  1413. }
  1414. LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
  1415. /* Setup DWT */
  1416. cortex_m3_dwt_setup(cortex_m3, target);
  1417. /* These hardware breakpoints only work for code in flash! */
  1418. LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
  1419. target_name(target),
  1420. cortex_m3->fp_num_code,
  1421. cortex_m3->dwt_num_comp);
  1422. }
  1423. return ERROR_OK;
  1424. }
  1425. static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
  1426. {
  1427. uint16_t dcrdr;
  1428. mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
  1429. *ctrl = (uint8_t)dcrdr;
  1430. *value = (uint8_t)(dcrdr >> 8);
  1431. LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
  1432. /* write ack back to software dcc register
  1433. * signify we have read data */
  1434. if (dcrdr & (1 << 0))
  1435. {
  1436. dcrdr = 0;
  1437. mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
  1438. }
  1439. return ERROR_OK;
  1440. }
  1441. static int cortex_m3_target_request_data(struct target *target,
  1442. uint32_t size, uint8_t *buffer)
  1443. {
  1444. struct armv7m_common *armv7m = target_to_armv7m(target);
  1445. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1446. uint8_t data;
  1447. uint8_t ctrl;
  1448. uint32_t i;
  1449. for (i = 0; i < (size * 4); i++)
  1450. {
  1451. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1452. buffer[i] = data;
  1453. }
  1454. return ERROR_OK;
  1455. }
  1456. static int cortex_m3_handle_target_request(void *priv)
  1457. {
  1458. struct target *target = priv;
  1459. if (!target_was_examined(target))
  1460. return ERROR_OK;
  1461. struct armv7m_common *armv7m = target_to_armv7m(target);
  1462. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1463. if (!target->dbg_msg_enabled)
  1464. return ERROR_OK;
  1465. if (target->state == TARGET_RUNNING)
  1466. {
  1467. uint8_t data;
  1468. uint8_t ctrl;
  1469. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1470. /* check if we have data */
  1471. if (ctrl & (1 << 0))
  1472. {
  1473. uint32_t request;
  1474. /* we assume target is quick enough */
  1475. request = data;
  1476. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1477. request |= (data << 8);
  1478. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1479. request |= (data << 16);
  1480. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1481. request |= (data << 24);
  1482. target_request(target, request);
  1483. }
  1484. }
  1485. return ERROR_OK;
  1486. }
  1487. static int cortex_m3_init_arch_info(struct target *target,
  1488. struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
  1489. {
  1490. int retval;
  1491. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  1492. armv7m_init_arch_info(target, armv7m);
  1493. /* prepare JTAG information for the new target */
  1494. cortex_m3->jtag_info.tap = tap;
  1495. cortex_m3->jtag_info.scann_size = 4;
  1496. armv7m->swjdp_info.dp_select_value = -1;
  1497. armv7m->swjdp_info.ap_csw_value = -1;
  1498. armv7m->swjdp_info.ap_tar_value = -1;
  1499. armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
  1500. armv7m->swjdp_info.memaccess_tck = 8;
  1501. armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
  1502. /* register arch-specific functions */
  1503. armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
  1504. armv7m->post_debug_entry = NULL;
  1505. armv7m->pre_restore_context = NULL;
  1506. armv7m->post_restore_context = NULL;
  1507. armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
  1508. armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
  1509. target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
  1510. if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
  1511. {
  1512. return retval;
  1513. }
  1514. return ERROR_OK;
  1515. }
  1516. static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
  1517. {
  1518. struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
  1519. cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
  1520. cortex_m3_init_arch_info(target, cortex_m3, target->tap);
  1521. return ERROR_OK;
  1522. }
  1523. /*--------------------------------------------------------------------------*/
  1524. static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
  1525. struct cortex_m3_common *cm3)
  1526. {
  1527. if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
  1528. command_print(cmd_ctx, "target is not a Cortex-M3");
  1529. return ERROR_TARGET_INVALID;
  1530. }
  1531. return ERROR_OK;
  1532. }
  1533. /*
  1534. * Only stuff below this line should need to verify that its target
  1535. * is a Cortex-M3. Everything else should have indirected through the
  1536. * cortexm3_target structure, which is only used with CM3 targets.
  1537. */
  1538. /*
  1539. * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
  1540. * as at least ARM-1156T2. The interesting thing about Cortex-M is
  1541. * that *only* Thumb2 disassembly matters. There are also some small
  1542. * additions to Thumb2 that are specific to ARMv7-M.
  1543. */
  1544. COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
  1545. {
  1546. int retval;
  1547. struct target *target = get_current_target(CMD_CTX);
  1548. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1549. uint32_t address;
  1550. unsigned long count = 1;
  1551. struct arm_instruction cur_instruction;
  1552. retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
  1553. if (retval != ERROR_OK)
  1554. return retval;
  1555. errno = 0;
  1556. switch (CMD_ARGC) {
  1557. case 2:
  1558. COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
  1559. /* FALL THROUGH */
  1560. case 1:
  1561. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
  1562. break;
  1563. default:
  1564. command_print(CMD_CTX,
  1565. "usage: cortex_m3 disassemble <address> [<count>]");
  1566. return ERROR_OK;
  1567. }
  1568. while (count--) {
  1569. retval = thumb2_opcode(target, address, &cur_instruction);
  1570. if (retval != ERROR_OK)
  1571. return retval;
  1572. command_print(CMD_CTX, "%s", cur_instruction.text);
  1573. address += cur_instruction.instruction_size;
  1574. }
  1575. return ERROR_OK;
  1576. }
  1577. static const struct {
  1578. char name[10];
  1579. unsigned mask;
  1580. } vec_ids[] = {
  1581. { "hard_err", VC_HARDERR, },
  1582. { "int_err", VC_INTERR, },
  1583. { "bus_err", VC_BUSERR, },
  1584. { "state_err", VC_STATERR, },
  1585. { "chk_err", VC_CHKERR, },
  1586. { "nocp_err", VC_NOCPERR, },
  1587. { "mm_err", VC_MMERR, },
  1588. { "reset", VC_CORERESET, },
  1589. };
  1590. COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
  1591. {
  1592. struct target *target = get_current_target(CMD_CTX);
  1593. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1594. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  1595. struct swjdp_common *swjdp = &armv7m->swjdp_info;
  1596. uint32_t demcr = 0;
  1597. int retval;
  1598. retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
  1599. if (retval != ERROR_OK)
  1600. return retval;
  1601. mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
  1602. if (CMD_ARGC > 0) {
  1603. unsigned catch = 0;
  1604. if (CMD_ARGC == 1) {
  1605. if (strcmp(CMD_ARGV[0], "all") == 0) {
  1606. catch = VC_HARDERR | VC_INTERR | VC_BUSERR
  1607. | VC_STATERR | VC_CHKERR | VC_NOCPERR
  1608. | VC_MMERR | VC_CORERESET;
  1609. goto write;
  1610. } else if (strcmp(CMD_ARGV[0], "none") == 0) {
  1611. goto write;
  1612. }
  1613. }
  1614. while (CMD_ARGC-- > 0) {
  1615. unsigned i;
  1616. for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
  1617. if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
  1618. continue;
  1619. catch |= vec_ids[i].mask;
  1620. break;
  1621. }
  1622. if (i == ARRAY_SIZE(vec_ids)) {
  1623. LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
  1624. return ERROR_INVALID_ARGUMENTS;
  1625. }
  1626. }
  1627. write:
  1628. demcr &= ~0xffff;
  1629. demcr |= catch;
  1630. /* write, but don't assume it stuck */
  1631. mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
  1632. mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
  1633. }
  1634. for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
  1635. {
  1636. command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
  1637. (demcr & vec_ids[i].mask) ? "catch" : "ignore");
  1638. }
  1639. return ERROR_OK;
  1640. }
  1641. COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
  1642. {
  1643. struct target *target = get_current_target(CMD_CTX);
  1644. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1645. int retval;
  1646. retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
  1647. if (retval != ERROR_OK)
  1648. return retval;
  1649. if (target->state != TARGET_HALTED)
  1650. {
  1651. command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
  1652. return ERROR_OK;
  1653. }
  1654. if (CMD_ARGC > 0)
  1655. {
  1656. bool enable;
  1657. COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
  1658. uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
  1659. uint32_t mask_off = enable ? 0 : C_MASKINTS;
  1660. cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
  1661. }
  1662. command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
  1663. (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
  1664. return ERROR_OK;
  1665. }
  1666. static const struct command_registration cortex_m3_exec_command_handlers[] = {
  1667. {
  1668. .name = "disassemble",
  1669. .handler = handle_cortex_m3_disassemble_command,
  1670. .mode = COMMAND_EXEC,
  1671. .help = "disassemble Thumb2 instructions",
  1672. .usage = "address [count]",
  1673. },
  1674. {
  1675. .name = "maskisr",
  1676. .handler = handle_cortex_m3_mask_interrupts_command,
  1677. .mode = COMMAND_EXEC,
  1678. .help = "mask cortex_m3 interrupts",
  1679. .usage = "['on'|'off']",
  1680. },
  1681. {
  1682. .name = "vector_catch",
  1683. .handler = handle_cortex_m3_vector_catch_command,
  1684. .mode = COMMAND_EXEC,
  1685. .help = "configure hardware vectors to trigger debug entry",
  1686. .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
  1687. },
  1688. COMMAND_REGISTRATION_DONE
  1689. };
  1690. static const struct command_registration cortex_m3_command_handlers[] = {
  1691. {
  1692. .chain = armv7m_command_handlers,
  1693. },
  1694. {
  1695. .name = "cortex_m3",
  1696. .mode = COMMAND_EXEC,
  1697. .help = "Cortex-M3 command group",
  1698. .chain = cortex_m3_exec_command_handlers,
  1699. },
  1700. COMMAND_REGISTRATION_DONE
  1701. };
  1702. struct target_type cortexm3_target =
  1703. {
  1704. .name = "cortex_m3",
  1705. .poll = cortex_m3_poll,
  1706. .arch_state = armv7m_arch_state,
  1707. .target_request_data = cortex_m3_target_request_data,
  1708. .halt = cortex_m3_halt,
  1709. .resume = cortex_m3_resume,
  1710. .step = cortex_m3_step,
  1711. .assert_reset = cortex_m3_assert_reset,
  1712. .deassert_reset = cortex_m3_deassert_reset,
  1713. .soft_reset_halt = cortex_m3_soft_reset_halt,
  1714. .get_gdb_reg_list = armv7m_get_gdb_reg_list,
  1715. .read_memory = cortex_m3_read_memory,
  1716. .write_memory = cortex_m3_write_memory,
  1717. .bulk_write_memory = cortex_m3_bulk_write_memory,
  1718. .checksum_memory = armv7m_checksum_memory,
  1719. .blank_check_memory = armv7m_blank_check_memory,
  1720. .run_algorithm = armv7m_run_algorithm,
  1721. .add_breakpoint = cortex_m3_add_breakpoint,
  1722. .remove_breakpoint = cortex_m3_remove_breakpoint,
  1723. .add_watchpoint = cortex_m3_add_watchpoint,
  1724. .remove_watchpoint = cortex_m3_remove_watchpoint,
  1725. .commands = cortex_m3_command_handlers,
  1726. .target_create = cortex_m3_target_create,
  1727. .init_target = cortex_m3_init_target,
  1728. .examine = cortex_m3_examine,
  1729. };