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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Mathias Kuester *
  3. * mkdorg@users.sourceforge.net *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include <helper/jim.h>
  24. #include "target.h"
  25. #include "target_type.h"
  26. #include "register.h"
  27. #include "dsp563xx.h"
  28. #include "dsp563xx_once.h"
  29. #define DSP563XX_JTAG_INS_LEN 4
  30. #define JTAG_STATUS_NORMAL 0x01
  31. #define JTAG_STATUS_STOPWAIT 0x05
  32. #define JTAG_STATUS_BUSY 0x09
  33. #define JTAG_STATUS_DEBUG 0x0d
  34. #define JTAG_INSTR_EXTEST 0x00
  35. #define JTAG_INSTR_SAMPLE_PRELOAD 0x01
  36. #define JTAG_INSTR_IDCODE 0x02
  37. #define JTAG_INSTR_CLAMP 0x03
  38. #define JTAG_INSTR_HIZ 0x04
  39. #define JTAG_INSTR_ENABLE_ONCE 0x06
  40. #define JTAG_INSTR_DEBUG_REQUEST 0x07
  41. #define JTAG_INSTR_BYPASS 0x0F
  42. /* forward declarations */
  43. int dsp563xx_target_create(struct target *target, Jim_Interp * interp);
  44. int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target);
  45. int dsp563xx_arch_state(struct target *target);
  46. int dsp563xx_poll(struct target *target);
  47. int dsp563xx_halt(struct target *target);
  48. int dsp563xx_resume(struct target *target, int current, uint32_t address,
  49. int handle_breakpoints, int debug_execution);
  50. int dsp563xx_step(struct target *target, int current, uint32_t address,
  51. int handle_breakpoints);
  52. int dsp563xx_assert_reset(struct target *target);
  53. int dsp563xx_deassert_reset(struct target *target);
  54. int dsp563xx_soft_reset_halt(struct target *target);
  55. /* IR and DR functions */
  56. int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out);
  57. int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
  58. int len);
  59. int dsp563xx_read_memory_p(struct target *target, uint32_t address, uint32_t size,
  60. uint32_t count, uint8_t * buffer);
  61. int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size,
  62. uint32_t count, uint8_t * buffer);
  63. #define ASM_REG_R_R0 0x607000
  64. #define ASM_REG_R_R1 0x617000
  65. #define ASM_REG_R_R2 0x627000
  66. #define ASM_REG_R_R3 0x637000
  67. #define ASM_REG_R_R4 0x647000
  68. #define ASM_REG_R_R5 0x657000
  69. #define ASM_REG_R_R6 0x667000
  70. #define ASM_REG_R_R7 0x677000
  71. #define ASM_REG_W_R0 0x60F400
  72. #define ASM_REG_W_R1 0x61F400
  73. #define ASM_REG_W_R2 0x62F400
  74. #define ASM_REG_W_R3 0x63F400
  75. #define ASM_REG_W_R4 0x64F400
  76. #define ASM_REG_W_R5 0x65F400
  77. #define ASM_REG_W_R6 0x66F400
  78. #define ASM_REG_W_R7 0x67F400
  79. #define ASM_REG_R_N0 0x707000
  80. #define ASM_REG_R_N1 0x717000
  81. #define ASM_REG_R_N2 0x727000
  82. #define ASM_REG_R_N3 0x737000
  83. #define ASM_REG_R_N4 0x747000
  84. #define ASM_REG_R_N5 0x757000
  85. #define ASM_REG_R_N6 0x767000
  86. #define ASM_REG_R_N7 0x777000
  87. #define ASM_REG_W_N0 0x70F400
  88. #define ASM_REG_W_N1 0x71F400
  89. #define ASM_REG_W_N2 0x72F400
  90. #define ASM_REG_W_N3 0x73F400
  91. #define ASM_REG_W_N4 0x74F400
  92. #define ASM_REG_W_N5 0x75F400
  93. #define ASM_REG_W_N6 0x76F400
  94. #define ASM_REG_W_N7 0x77F400
  95. #define ASM_REG_R_M0 0x057020 /* control register m[0..7] */
  96. #define ASM_REG_R_M1 0x057021
  97. #define ASM_REG_R_M2 0x057022
  98. #define ASM_REG_R_M3 0x057023
  99. #define ASM_REG_R_M4 0x057024
  100. #define ASM_REG_R_M5 0x057025
  101. #define ASM_REG_R_M6 0x057026
  102. #define ASM_REG_R_M7 0x057027
  103. #define ASM_REG_W_M0 0x05F420
  104. #define ASM_REG_W_M1 0x05F421
  105. #define ASM_REG_W_M2 0x05F422
  106. #define ASM_REG_W_M3 0x05F423
  107. #define ASM_REG_W_M4 0x05F424
  108. #define ASM_REG_W_M5 0x05F425
  109. #define ASM_REG_W_M6 0x05F426
  110. #define ASM_REG_W_M7 0x05F427
  111. #define ASM_REG_R_X0 0x447000
  112. #define ASM_REG_R_X1 0x457000
  113. #define ASM_REG_W_X0 0x44F400
  114. #define ASM_REG_W_X1 0x45F400
  115. #define ASM_REG_R_Y0 0x467000
  116. #define ASM_REG_R_Y1 0x477000
  117. #define ASM_REG_W_Y0 0x46F400
  118. #define ASM_REG_W_Y1 0x47F400
  119. #define ASM_REG_R_A0 0x507000
  120. #define ASM_REG_R_A1 0x547000
  121. #define ASM_REG_R_A2 0x527000
  122. #define ASM_REG_W_A0 0x50F400
  123. #define ASM_REG_W_A1 0x54F400
  124. #define ASM_REG_W_A2 0x52F400
  125. #define ASM_REG_R_B0 0x517000
  126. #define ASM_REG_R_B1 0x557000
  127. #define ASM_REG_R_B2 0x537000
  128. #define ASM_REG_W_B0 0x51F400
  129. #define ASM_REG_W_B1 0x55F400
  130. #define ASM_REG_W_B2 0x53F400
  131. #define ASM_REG_R_VBA 0x057030 /* control register */
  132. #define ASM_REG_W_VBA 0x05F430
  133. #define ASM_REG_R_OMR 0x05703A /* control register */
  134. #define ASM_REG_W_OMR 0x05F43A
  135. #define ASM_REG_R_EP 0x05702A
  136. #define ASM_REG_W_EP 0x05F42A
  137. #define ASM_REG_R_SC 0x057031 /* stack counter */
  138. #define ASM_REG_W_SC 0x05F431
  139. #define ASM_REG_R_SZ 0x057038 /* stack size */
  140. #define ASM_REG_W_SZ 0x05F438
  141. #define ASM_REG_R_SR 0x057039 /* control register, status register */
  142. #define ASM_REG_W_SR 0x05F439
  143. #define ASM_REG_R_SP 0x05703B /* control register, stack pointer */
  144. #define ASM_REG_W_SP 0x05F43B
  145. #define ASM_REG_R_SSH 0x05703C /* control register, system stack high */
  146. #define ASM_REG_W_SSH 0x05743C
  147. #define ASM_REG_R_SSL 0x05703D /* control register, system stack low */
  148. #define ASM_REG_W_SSL 0x05F43D
  149. #define ASM_REG_R_LA 0x05703E /* control register, loop address */
  150. #define ASM_REG_W_LA 0x05F43E
  151. #define ASM_REG_R_LC 0x05703F /* control register, loop count */
  152. #define ASM_REG_W_LC 0x05F43F
  153. #define ASM_REG_R_PC 0x000000
  154. #define ASM_REG_W_PC 0x000000
  155. static const struct
  156. {
  157. unsigned id;
  158. char *name;
  159. unsigned bits;
  160. uint32_t r_cmd;
  161. uint32_t w_cmd;
  162. } dsp563xx_regs[] =
  163. {
  164. /* *INDENT-OFF* */
  165. {0, "r0", 24, ASM_REG_R_R0, ASM_REG_W_R0},
  166. {1, "r1", 24, ASM_REG_R_R1, ASM_REG_W_R1},
  167. {2, "r2", 24, ASM_REG_R_R2, ASM_REG_W_R2},
  168. {3, "r3", 24, ASM_REG_R_R3, ASM_REG_W_R3},
  169. {4, "r4", 24, ASM_REG_R_R4, ASM_REG_W_R4},
  170. {5, "r5", 24, ASM_REG_R_R5, ASM_REG_W_R5},
  171. {6, "r6", 24, ASM_REG_R_R6, ASM_REG_W_R6},
  172. {7, "r7", 24, ASM_REG_R_R7, ASM_REG_W_R7},
  173. {8, "n0", 24, ASM_REG_R_N0, ASM_REG_W_N0},
  174. {9, "n1", 24, ASM_REG_R_N1, ASM_REG_W_N1},
  175. {10, "n2", 24, ASM_REG_R_N2, ASM_REG_W_N2},
  176. {11, "n3", 24, ASM_REG_R_N3, ASM_REG_W_N3},
  177. {12, "n4", 24, ASM_REG_R_N4, ASM_REG_W_N4},
  178. {13, "n5", 24, ASM_REG_R_N5, ASM_REG_W_N5},
  179. {14, "n6", 24, ASM_REG_R_N6, ASM_REG_W_N6},
  180. {15, "n7", 24, ASM_REG_R_N7, ASM_REG_W_N7},
  181. {16, "m0", 24, ASM_REG_R_M0, ASM_REG_W_M0},
  182. {17, "m1", 24, ASM_REG_R_M1, ASM_REG_W_M1},
  183. {18, "m2", 24, ASM_REG_R_M2, ASM_REG_W_M2},
  184. {19, "m3", 24, ASM_REG_R_M3, ASM_REG_W_M3},
  185. {20, "m4", 24, ASM_REG_R_M4, ASM_REG_W_M4},
  186. {21, "m5", 24, ASM_REG_R_M5, ASM_REG_W_M5},
  187. {22, "m6", 24, ASM_REG_R_M6, ASM_REG_W_M6},
  188. {23, "m7", 24, ASM_REG_R_M7, ASM_REG_W_M7},
  189. {24, "x0", 24, ASM_REG_R_X0, ASM_REG_W_X0},
  190. {25, "x1", 24, ASM_REG_R_X1, ASM_REG_W_X1},
  191. {26, "y0", 24, ASM_REG_R_Y0, ASM_REG_W_Y0},
  192. {27, "y1", 24, ASM_REG_R_Y1, ASM_REG_W_Y1},
  193. {28, "a0", 24, ASM_REG_R_A0, ASM_REG_W_A0},
  194. {29, "a1", 24, ASM_REG_R_A1, ASM_REG_W_A1},
  195. {30, "a2", 8, ASM_REG_R_A2, ASM_REG_W_A2},
  196. {31, "b0", 24, ASM_REG_R_B0, ASM_REG_W_B0},
  197. {32, "b1", 24, ASM_REG_R_B1, ASM_REG_W_B1},
  198. {33, "b2", 8, ASM_REG_R_B2, ASM_REG_W_B2},
  199. {34, "omr", 24, ASM_REG_R_OMR, ASM_REG_W_OMR},
  200. {35, "vba", 24, ASM_REG_R_VBA, ASM_REG_W_VBA},
  201. {36, "ep", 24, ASM_REG_R_EP, ASM_REG_W_EP},
  202. {37, "sc", 24, ASM_REG_R_SC, ASM_REG_W_SC},
  203. {38, "sz", 24, ASM_REG_R_SZ, ASM_REG_W_SZ},
  204. {39, "sr", 24, ASM_REG_R_SR, ASM_REG_W_SR},
  205. {40, "sp", 24, ASM_REG_R_SP, ASM_REG_W_SP},
  206. {41, "la", 24, ASM_REG_R_LA, ASM_REG_W_LA},
  207. {42, "lc", 24, ASM_REG_R_LC, ASM_REG_W_LC},
  208. {43, "pc", 24, ASM_REG_R_PC, ASM_REG_W_PC}
  209. /* *INDENT-ON* */
  210. };
  211. int dsp563xx_read_core_reg(struct target *target, int num)
  212. {
  213. uint32_t reg_value;
  214. struct dsp563xx_core_reg *dsp563xx_core_reg;
  215. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  216. if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
  217. return ERROR_INVALID_ARGUMENTS;
  218. dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info;
  219. reg_value = dsp563xx->core_regs[num];
  220. buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
  221. dsp563xx->core_cache->reg_list[num].valid = 1;
  222. dsp563xx->core_cache->reg_list[num].dirty = 0;
  223. return ERROR_OK;
  224. }
  225. int dsp563xx_write_core_reg(struct target *target, int num)
  226. {
  227. uint32_t reg_value;
  228. struct dsp563xx_core_reg *dsp563xx_core_reg;
  229. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  230. if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
  231. return ERROR_INVALID_ARGUMENTS;
  232. reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
  233. dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info;
  234. dsp563xx->core_regs[num] = reg_value;
  235. dsp563xx->core_cache->reg_list[num].valid = 1;
  236. dsp563xx->core_cache->reg_list[num].dirty = 0;
  237. return ERROR_OK;
  238. }
  239. int dsp563xx_target_create(struct target *target, Jim_Interp * interp)
  240. {
  241. struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
  242. dsp563xx->jtag_info.tap = target->tap;
  243. target->arch_info = dsp563xx;
  244. dsp563xx->read_core_reg = dsp563xx_read_core_reg;
  245. dsp563xx->write_core_reg = dsp563xx_write_core_reg;
  246. return ERROR_OK;
  247. }
  248. int dsp563xx_get_core_reg(struct reg *reg)
  249. {
  250. int retval = 0;
  251. LOG_DEBUG("%s", __FUNCTION__);
  252. struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
  253. struct target *target = dsp563xx_reg->target;
  254. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  255. if (target->state != TARGET_HALTED)
  256. {
  257. return ERROR_TARGET_NOT_HALTED;
  258. }
  259. retval = dsp563xx->read_core_reg(target, dsp563xx_reg->num);
  260. return retval;
  261. }
  262. int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf)
  263. {
  264. LOG_DEBUG("%s", __FUNCTION__);
  265. struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
  266. struct target *target = dsp563xx_reg->target;
  267. uint32_t value = buf_get_u32(buf, 0, 32);
  268. if (target->state != TARGET_HALTED)
  269. {
  270. return ERROR_TARGET_NOT_HALTED;
  271. }
  272. buf_set_u32(reg->value, 0, reg->size, value);
  273. reg->dirty = 1;
  274. reg->valid = 1;
  275. return ERROR_OK;
  276. }
  277. int dsp563xx_save_context(struct target *target)
  278. {
  279. int i;
  280. uint32_t data = 0;
  281. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  282. struct dsp563xx_core_reg *arch_info;
  283. for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++)
  284. {
  285. // if (!dsp563xx->core_cache->reg_list[i].valid)
  286. {
  287. arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
  288. dsp563xx_once_execute_dw_ir(target->tap, arch_info->r_cmd,
  289. 0xfffffc);
  290. dsp563xx_once_execute_sw_ir(target->tap, 0x000000);
  291. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR,
  292. &data);
  293. dsp563xx->core_regs[i] = data;
  294. dsp563xx->read_core_reg(target, i);
  295. }
  296. }
  297. /* read pc */
  298. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, &data);
  299. dsp563xx->core_regs[i] = data;
  300. dsp563xx->read_core_reg(target, i);
  301. return ERROR_OK;
  302. }
  303. int dsp563xx_restore_context(struct target *target)
  304. {
  305. int i;
  306. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  307. struct dsp563xx_core_reg *arch_info;
  308. for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++)
  309. {
  310. if (dsp563xx->core_cache->reg_list[i].dirty)
  311. {
  312. arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
  313. dsp563xx->write_core_reg(target, i);
  314. dsp563xx_once_execute_dw_ir(target->tap, arch_info->w_cmd,
  315. dsp563xx->core_regs[i]);
  316. dsp563xx_once_execute_sw_ir(target->tap, 0x000000);
  317. }
  318. }
  319. return ERROR_OK;
  320. }
  321. static const struct reg_arch_type dsp563xx_reg_type = {
  322. .get = dsp563xx_get_core_reg,
  323. .set = dsp563xx_set_core_reg,
  324. };
  325. int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
  326. {
  327. /* get pointers to arch-specific information */
  328. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  329. struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
  330. struct reg_cache *cache = malloc(sizeof(struct reg_cache));
  331. struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS);
  332. struct dsp563xx_core_reg *arch_info =
  333. malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
  334. int i;
  335. LOG_DEBUG("%s", __FUNCTION__);
  336. /* Build the process context cache */
  337. cache->name = "dsp563xx registers";
  338. cache->next = NULL;
  339. cache->reg_list = reg_list;
  340. cache->num_regs = DSP563XX_NUMCOREREGS;
  341. (*cache_p) = cache;
  342. dsp563xx->core_cache = cache;
  343. for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
  344. {
  345. arch_info[i].num = dsp563xx_regs[i].id;
  346. arch_info[i].name = dsp563xx_regs[i].name;
  347. arch_info[i].size = dsp563xx_regs[i].bits;
  348. arch_info[i].r_cmd = dsp563xx_regs[i].r_cmd;
  349. arch_info[i].w_cmd = dsp563xx_regs[i].w_cmd;
  350. arch_info[i].target = target;
  351. arch_info[i].dsp563xx_common = dsp563xx;
  352. reg_list[i].name = dsp563xx_regs[i].name;
  353. reg_list[i].size = dsp563xx_regs[i].bits;
  354. reg_list[i].value = calloc(1, 4);
  355. reg_list[i].dirty = 0;
  356. reg_list[i].valid = 0;
  357. reg_list[i].type = &dsp563xx_reg_type;
  358. reg_list[i].arch_info = &arch_info[i];
  359. }
  360. return ERROR_OK;
  361. }
  362. int dsp563xx_arch_state(struct target *target)
  363. {
  364. LOG_DEBUG("%s", __FUNCTION__);
  365. return ERROR_OK;
  366. }
  367. int dsp563xx_jtag_status(struct target *target, uint8_t * status)
  368. {
  369. uint8_t ir_in;
  370. ir_in = 0;
  371. dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE);
  372. dsp563xx_execute_queue();
  373. *status = ir_in;
  374. return ERROR_OK;
  375. }
  376. int dsp563xx_jtag_debug_request(struct target *target)
  377. {
  378. uint8_t ir_in = 0;
  379. uint32_t retry = 0;
  380. while (ir_in != JTAG_STATUS_DEBUG)
  381. {
  382. dsp563xx_jtag_sendinstr(target->tap, &ir_in,
  383. JTAG_INSTR_DEBUG_REQUEST);
  384. dsp563xx_execute_queue();
  385. LOG_DEBUG("JTAG CMD 7 res: %02X", ir_in);
  386. dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE);
  387. dsp563xx_execute_queue();
  388. LOG_DEBUG("JTAG CMD 6 res: %02X", ir_in);
  389. if (retry++ == 100)
  390. return ERROR_TARGET_FAILURE;
  391. }
  392. if (ir_in != JTAG_STATUS_DEBUG)
  393. {
  394. return ERROR_TARGET_FAILURE;
  395. }
  396. return ERROR_OK;
  397. }
  398. int dsp563xx_poll(struct target *target)
  399. {
  400. uint8_t jtag_status;
  401. uint32_t once_status;
  402. dsp563xx_jtag_status(target, &jtag_status);
  403. if ((jtag_status & 1) != 1)
  404. {
  405. target->state = TARGET_UNKNOWN;
  406. LOG_ERROR
  407. ("jtag status contains invalid mode value - communication failure");
  408. return ERROR_TARGET_FAILURE;
  409. }
  410. if (jtag_status != JTAG_STATUS_DEBUG)
  411. {
  412. target->state = TARGET_RUNNING;
  413. }
  414. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, &once_status);
  415. if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M)
  416. {
  417. target->state = TARGET_HALTED;
  418. }
  419. return ERROR_OK;
  420. }
  421. int dsp563xx_halt(struct target *target)
  422. {
  423. uint8_t jtag_status;
  424. uint32_t once_status;
  425. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  426. if (target->state == TARGET_HALTED)
  427. {
  428. LOG_DEBUG("target was already halted");
  429. return ERROR_OK;
  430. }
  431. if (target->state == TARGET_UNKNOWN)
  432. {
  433. LOG_WARNING("target was in unknown state when halt was requested");
  434. }
  435. // if ( jtag_status != 0x0d )
  436. {
  437. dsp563xx_jtag_debug_request(target);
  438. /* store pipeline register */
  439. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR,
  440. &dsp563xx->pipeline_context.once_opilr);
  441. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR,
  442. &dsp563xx->pipeline_context.once_opdbr);
  443. dsp563xx_save_context(target);
  444. dsp563xx_jtag_status(target, &jtag_status);
  445. LOG_DEBUG("%02X", jtag_status);
  446. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
  447. &once_status);
  448. LOG_DEBUG("%02X", (unsigned) once_status);
  449. }
  450. LOG_DEBUG("target->state: %s", target_state_name(target));
  451. LOG_DEBUG("%s", __FUNCTION__);
  452. return ERROR_OK;
  453. }
  454. #define DSP563XX_ASM_CMD_JUMP 0x0AF080
  455. int dsp563xx_resume(struct target *target, int current, uint32_t address,
  456. int handle_breakpoints, int debug_execution)
  457. {
  458. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  459. LOG_DEBUG("%s", __FUNCTION__);
  460. dsp563xx_restore_context(target);
  461. if (current)
  462. {
  463. /* restore pipeline registers and go */
  464. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR,
  465. dsp563xx->pipeline_context.once_opilr);
  466. dsp563xx_once_reg_write(target->tap,
  467. DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX |
  468. DSP563XX_ONCE_OCR_GO,
  469. dsp563xx->pipeline_context.once_opdbr);
  470. }
  471. else
  472. {
  473. /* set to go register and jump */
  474. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR,
  475. DSP563XX_ASM_CMD_JUMP);
  476. dsp563xx_once_reg_write(target->tap,
  477. DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX
  478. | DSP563XX_ONCE_OCR_GO, address);
  479. }
  480. target->state = TARGET_RUNNING;
  481. return ERROR_OK;
  482. }
  483. int dsp563xx_step(struct target *target, int current, uint32_t address,
  484. int handle_breakpoints)
  485. {
  486. uint32_t once_status;
  487. uint32_t dr_in, cnt;
  488. struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
  489. if (target->state != TARGET_HALTED)
  490. {
  491. LOG_DEBUG("target was not halted");
  492. return ERROR_OK;
  493. }
  494. LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address);
  495. dsp563xx_jtag_debug_request(target);
  496. dsp563xx_restore_context(target);
  497. /* reset trace mode */
  498. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, 0x000000);
  499. /* enable trace mode */
  500. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
  501. DSP563XX_ONCE_OSCR_TME);
  502. cnt = 0;
  503. /* on JUMP we need one extra cycle */
  504. if (!current)
  505. cnt++;
  506. /* load step counter with N-1 */
  507. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OTC, cnt);
  508. if (current)
  509. {
  510. /* restore pipeline registers and go */
  511. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR,
  512. dsp563xx->pipeline_context.once_opilr);
  513. dsp563xx_once_reg_write(target->tap,
  514. DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX |
  515. DSP563XX_ONCE_OCR_GO,
  516. dsp563xx->pipeline_context.once_opdbr);
  517. }
  518. else
  519. {
  520. /* set to go register and jump */
  521. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR,
  522. DSP563XX_ASM_CMD_JUMP);
  523. dsp563xx_once_reg_write(target->tap,
  524. DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX
  525. | DSP563XX_ONCE_OCR_GO, address);
  526. }
  527. while (1)
  528. {
  529. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
  530. &once_status);
  531. if (once_status & DSP563XX_ONCE_OSCR_TO)
  532. {
  533. /* store pipeline register */
  534. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR,
  535. &dsp563xx->pipeline_context.
  536. once_opilr);
  537. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR,
  538. &dsp563xx->pipeline_context.
  539. once_opdbr);
  540. dsp563xx_save_context(target);
  541. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABFR,
  542. &dr_in);
  543. LOG_DEBUG("%08X", (unsigned) dr_in);
  544. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR,
  545. &dr_in);
  546. LOG_DEBUG("%08X", (unsigned) dr_in);
  547. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX,
  548. &dr_in);
  549. LOG_DEBUG("%08X", (unsigned) dr_in);
  550. /* reset trace mode */
  551. dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
  552. 0x000000);
  553. break;
  554. }
  555. }
  556. return ERROR_OK;
  557. }
  558. int dsp563xx_assert_reset(struct target *target)
  559. {
  560. target->state = TARGET_RESET;
  561. LOG_DEBUG("%s", __FUNCTION__);
  562. return ERROR_OK;
  563. }
  564. int dsp563xx_deassert_reset(struct target *target)
  565. {
  566. target->state = TARGET_RUNNING;
  567. LOG_DEBUG("%s", __FUNCTION__);
  568. return ERROR_OK;
  569. }
  570. int dsp563xx_soft_reset_halt(struct target *target)
  571. {
  572. LOG_DEBUG("%s", __FUNCTION__);
  573. return ERROR_OK;
  574. }
  575. /*
  576. * 000000 nop
  577. * 46F400 AABBCC move #$aabbcc,y0
  578. * 60F400 AABBCC move #$aabbcc,r0
  579. * 467000 AABBCC move y0,x:AABBCC
  580. * 607000 AABBCC move r0,x:AABBCC
  581. * 46E000 move x:(r0),y0
  582. * 4EE000 move y:(r0),y0
  583. * 07E086 move p:(r0),y0
  584. * 0450B9 move sr,r0
  585. * 0446BA move omr,y0
  586. * 0446BC move ssh,y0
  587. * 0446BD move ssl,y0
  588. * 0446BE move la,y0
  589. * 0446BF move lc,y0
  590. *
  591. * 61F000 AABBCC move x:AABBCC,r1
  592. * 076190 movem r0,p:(r1)
  593. *
  594. */
  595. int dsp563xx_read_memory_p(struct target *target, uint32_t address,
  596. uint32_t size, uint32_t count, uint8_t * buffer)
  597. {
  598. uint32_t i, x;
  599. uint32_t data;
  600. uint8_t *b;
  601. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8"
  602. PRIx32, address, size, count);
  603. if (target->state != TARGET_HALTED)
  604. {
  605. LOG_WARNING("target not halted");
  606. return ERROR_TARGET_NOT_HALTED;
  607. }
  608. x = count;
  609. for (i = 0; i < x; i++)
  610. {
  611. dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, address + i);
  612. dsp563xx_once_execute_sw_ir_nq(target->tap, 0x07E086);
  613. dsp563xx_once_execute_dw_ir_nq(target->tap, 0x467000, 0xfffffc);
  614. dsp563xx_execute_queue();
  615. dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, &data);
  616. b = buffer + 4 * i;
  617. if (size > 0)
  618. *b++ = data >> 0;
  619. if (size > 1)
  620. *b++ = data >> 8;
  621. if (size > 2)
  622. *b++ = data >> 16;
  623. if (size > 3)
  624. *b++ = 0x00;
  625. }
  626. return ERROR_OK;
  627. }
  628. int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size,
  629. uint32_t count, uint8_t * buffer)
  630. {
  631. uint32_t i, x;
  632. uint32_t data;
  633. uint8_t *b;
  634. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8"
  635. PRIx32 "", address, size, count);
  636. if (target->state != TARGET_HALTED)
  637. {
  638. LOG_WARNING("target not halted");
  639. return ERROR_TARGET_NOT_HALTED;
  640. }
  641. x = count;
  642. for (i = 0; i < x; i++)
  643. {
  644. b = buffer + 4 * i;
  645. data = 0;
  646. if (size > 0)
  647. data = *buffer++;
  648. if (size > 1)
  649. data |= (*buffer++) << 8;
  650. if (size > 2)
  651. data |= (*buffer++) << 16;
  652. if (size > 3)
  653. data |= (*buffer++) << 24;
  654. // LOG_DEBUG("%08X", data);
  655. dsp563xx_once_execute_dw_ir_nq(target->tap, 0x61F400, address + i);
  656. dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, data);
  657. dsp563xx_once_execute_sw_ir_nq(target->tap, 0x076190);
  658. dsp563xx_execute_queue();
  659. }
  660. return ERROR_OK;
  661. }
  662. int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
  663. int len)
  664. {
  665. return dsp563xx_write_dr_u32(tap, dr_in, dr_out, len, 1);
  666. }
  667. int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out)
  668. {
  669. return dsp563xx_write_ir_u8(tap, ir_in, ir_out, DSP563XX_JTAG_INS_LEN, 1);
  670. }
  671. /* IR and DR functions */
  672. int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out,
  673. int ir_len, int rti)
  674. {
  675. if (NULL == tap)
  676. {
  677. LOG_ERROR("invalid tap");
  678. return ERROR_FAIL;
  679. }
  680. if (ir_len != tap->ir_length)
  681. {
  682. LOG_ERROR("invalid ir_len");
  683. return ERROR_FAIL;
  684. }
  685. {
  686. struct scan_field field[1];
  687. field[0].tap = tap;
  688. field[0].num_bits = tap->ir_length;
  689. field[0].out_value = ir_out;
  690. field[0].in_value = ir_in;
  691. jtag_add_plain_ir_scan(ARRAY_SIZE(field), field,
  692. jtag_set_end_state(TAP_IDLE));
  693. }
  694. return ERROR_OK;
  695. }
  696. int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out,
  697. int dr_len, int rti)
  698. {
  699. if (NULL == tap)
  700. {
  701. LOG_ERROR("invalid tap");
  702. return ERROR_FAIL;
  703. }
  704. {
  705. struct scan_field field[1];
  706. field[0].tap = tap;
  707. field[0].num_bits = dr_len;
  708. field[0].out_value = dr_out;
  709. field[0].in_value = dr_in;
  710. jtag_add_plain_dr_scan(ARRAY_SIZE(field), field,
  711. jtag_set_end_state(TAP_IDLE));
  712. }
  713. return ERROR_OK;
  714. }
  715. int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
  716. int ir_len, int rti)
  717. {
  718. if (ir_len > 8)
  719. {
  720. LOG_ERROR("ir_len overflow, maxium is 8");
  721. return ERROR_FAIL;
  722. }
  723. dsp563xx_write_ir(tap, ir_in, &ir_out, ir_len, rti);
  724. return ERROR_OK;
  725. }
  726. int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * dr_in, uint8_t dr_out,
  727. int dr_len, int rti)
  728. {
  729. if (dr_len > 8)
  730. {
  731. LOG_ERROR("dr_len overflow, maxium is 8");
  732. return ERROR_FAIL;
  733. }
  734. dsp563xx_write_dr(tap, dr_in, &dr_out, dr_len, rti);
  735. return ERROR_OK;
  736. }
  737. int dsp563xx_write_ir_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out,
  738. int ir_len, int rti)
  739. {
  740. if (ir_len > 16)
  741. {
  742. LOG_ERROR("ir_len overflow, maxium is 16");
  743. return ERROR_FAIL;
  744. }
  745. dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti);
  746. return ERROR_OK;
  747. }
  748. int dsp563xx_write_dr_u16(struct jtag_tap *tap, uint16_t * dr_in, uint16_t dr_out,
  749. int dr_len, int rti)
  750. {
  751. if (dr_len > 16)
  752. {
  753. LOG_ERROR("dr_len overflow, maxium is 16");
  754. return ERROR_FAIL;
  755. }
  756. dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti);
  757. return ERROR_OK;
  758. }
  759. int dsp563xx_write_ir_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out,
  760. int ir_len, int rti)
  761. {
  762. if (ir_len > 32)
  763. {
  764. LOG_ERROR("ir_len overflow, maxium is 32");
  765. return ERROR_FAIL;
  766. }
  767. dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti);
  768. return ERROR_OK;
  769. }
  770. int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
  771. int dr_len, int rti)
  772. {
  773. if (dr_len > 32)
  774. {
  775. LOG_ERROR("dr_len overflow, maxium is 32");
  776. return ERROR_FAIL;
  777. }
  778. dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti);
  779. return ERROR_OK;
  780. }
  781. int dsp563xx_execute_queue(void)
  782. {
  783. return jtag_execute_queue();
  784. }
  785. /** Holds methods for DSP563XX targets. */
  786. struct target_type dsp563xx_target = {
  787. .name = "dsp563xx",
  788. .poll = dsp563xx_poll,
  789. .arch_state = dsp563xx_arch_state,
  790. .target_request_data = NULL,
  791. .halt = dsp563xx_halt,
  792. .resume = dsp563xx_resume,
  793. .step = dsp563xx_step,
  794. .assert_reset = dsp563xx_assert_reset,
  795. .deassert_reset = dsp563xx_deassert_reset,
  796. .soft_reset_halt = dsp563xx_soft_reset_halt,
  797. .read_memory = dsp563xx_read_memory_p,
  798. .write_memory = dsp563xx_write_memory_p,
  799. .target_create = dsp563xx_target_create,
  800. .init_target = dsp563xx_init_target,
  801. };