You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

2218 lines
57 KiB

  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "arm.h"
  24. #include "etm.h"
  25. #include "etb.h"
  26. #include "image.h"
  27. #include "arm_disassembler.h"
  28. #include "register.h"
  29. #include "etm_dummy.h"
  30. #if BUILD_OOCD_TRACE == 1
  31. #include "oocd_trace.h"
  32. #endif
  33. /*
  34. * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  35. *
  36. * ETM modules collect instruction and/or data trace information, compress
  37. * it, and transfer it to a debugging host through either a (buffered) trace
  38. * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  39. *
  40. * There are several generations of these modules. Original versions have
  41. * JTAG access through a dedicated scan chain. Recent versions have added
  42. * access via coprocessor instructions, memory addressing, and the ARM Debug
  43. * Interface v5 (ADIv5); and phased out direct JTAG access.
  44. *
  45. * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  46. * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
  47. * implying non-JTAG connectivity options.
  48. *
  49. * Relevant documentation includes:
  50. * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  51. * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  52. * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  53. */
  54. enum {
  55. RO, /* read/only */
  56. WO, /* write/only */
  57. RW, /* read/write */
  58. };
  59. struct etm_reg_info {
  60. uint8_t addr;
  61. uint8_t size; /* low-N of 32 bits */
  62. uint8_t mode; /* RO, WO, RW */
  63. uint8_t bcd_vers; /* 1.0, 2.0, etc */
  64. char *name;
  65. };
  66. /*
  67. * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  68. * (Or on some processors, through coprocessor operations.)
  69. * Newer versions of ETM make some W/O registers R/W, and
  70. * provide definitions for some previously-unused bits.
  71. */
  72. /* core registers used to version/configure the ETM */
  73. static const struct etm_reg_info etm_core[] = {
  74. /* NOTE: we "know" the order here ... */
  75. { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  76. { ETM_ID, 32, RO, 0x20, "ETM_id", },
  77. };
  78. /* basic registers that are always there given the right ETM version */
  79. static const struct etm_reg_info etm_basic[] = {
  80. /* ETM Trace Registers */
  81. { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  82. { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  83. { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
  84. { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
  85. { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
  86. /* TraceEnable configuration */
  87. { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  88. { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  89. { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  90. { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  91. /* ViewData configuration (data trace) */
  92. { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  93. { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
  94. { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
  95. { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
  96. /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
  97. { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
  98. { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
  99. { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
  100. { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
  101. { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
  102. };
  103. static const struct etm_reg_info etm_fifofull[] = {
  104. /* FIFOFULL configuration */
  105. { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
  106. { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
  107. };
  108. static const struct etm_reg_info etm_addr_comp[] = {
  109. /* Address comparator register pairs */
  110. #define ADDR_COMPARATOR(i) \
  111. { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
  112. "ETM_addr_" #i "_comparator_value", }, \
  113. { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
  114. "ETM_addr_" #i "_access_type", }
  115. ADDR_COMPARATOR(1),
  116. ADDR_COMPARATOR(2),
  117. ADDR_COMPARATOR(3),
  118. ADDR_COMPARATOR(4),
  119. ADDR_COMPARATOR(5),
  120. ADDR_COMPARATOR(6),
  121. ADDR_COMPARATOR(7),
  122. ADDR_COMPARATOR(8),
  123. ADDR_COMPARATOR(9),
  124. ADDR_COMPARATOR(10),
  125. ADDR_COMPARATOR(11),
  126. ADDR_COMPARATOR(12),
  127. ADDR_COMPARATOR(13),
  128. ADDR_COMPARATOR(14),
  129. ADDR_COMPARATOR(15),
  130. ADDR_COMPARATOR(16),
  131. #undef ADDR_COMPARATOR
  132. };
  133. static const struct etm_reg_info etm_data_comp[] = {
  134. /* Data Value Comparators (NOTE: odd addresses are reserved) */
  135. #define DATA_COMPARATOR(i) \
  136. { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
  137. "ETM_data_" #i "_comparator_value", }, \
  138. { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
  139. "ETM_data_" #i "_comparator_mask", }
  140. DATA_COMPARATOR(1),
  141. DATA_COMPARATOR(2),
  142. DATA_COMPARATOR(3),
  143. DATA_COMPARATOR(4),
  144. DATA_COMPARATOR(5),
  145. DATA_COMPARATOR(6),
  146. DATA_COMPARATOR(7),
  147. DATA_COMPARATOR(8),
  148. #undef DATA_COMPARATOR
  149. };
  150. static const struct etm_reg_info etm_counters[] = {
  151. #define ETM_COUNTER(i) \
  152. { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
  153. "ETM_counter_" #i "_reload_value", }, \
  154. { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
  155. "ETM_counter_" #i "_enable", }, \
  156. { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
  157. "ETM_counter_" #i "_reload_event", }, \
  158. { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
  159. "ETM_counter_" #i "_value", }
  160. ETM_COUNTER(1),
  161. ETM_COUNTER(2),
  162. ETM_COUNTER(3),
  163. ETM_COUNTER(4),
  164. #undef ETM_COUNTER
  165. };
  166. static const struct etm_reg_info etm_sequencer[] = {
  167. #define ETM_SEQ(i) \
  168. { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
  169. "ETM_sequencer_event" #i, }
  170. ETM_SEQ(0), /* 1->2 */
  171. ETM_SEQ(1), /* 2->1 */
  172. ETM_SEQ(2), /* 2->3 */
  173. ETM_SEQ(3), /* 3->1 */
  174. ETM_SEQ(4), /* 3->2 */
  175. ETM_SEQ(5), /* 1->3 */
  176. #undef ETM_SEQ
  177. /* 0x66 reserved */
  178. { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
  179. };
  180. static const struct etm_reg_info etm_outputs[] = {
  181. #define ETM_OUTPUT(i) \
  182. { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
  183. "ETM_external_output" #i, }
  184. ETM_OUTPUT(1),
  185. ETM_OUTPUT(2),
  186. ETM_OUTPUT(3),
  187. ETM_OUTPUT(4),
  188. #undef ETM_OUTPUT
  189. };
  190. #if 0
  191. /* registers from 0x6c..0x7f were added after ETMv1.3 */
  192. /* Context ID Comparators */
  193. { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
  194. { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
  195. { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
  196. { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
  197. #endif
  198. static int etm_get_reg(struct reg *reg);
  199. static int etm_read_reg_w_check(struct reg *reg,
  200. uint8_t* check_value, uint8_t* check_mask);
  201. static int etm_register_user_commands(struct command_context *cmd_ctx);
  202. static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
  203. static int etm_write_reg(struct reg *reg, uint32_t value);
  204. static const struct reg_arch_type etm_scan6_type = {
  205. .get = etm_get_reg,
  206. .set = etm_set_reg_w_exec,
  207. };
  208. /* Look up register by ID ... most ETM instances only
  209. * support a subset of the possible registers.
  210. */
  211. static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
  212. {
  213. struct reg_cache *cache = etm_ctx->reg_cache;
  214. unsigned i;
  215. for (i = 0; i < cache->num_regs; i++) {
  216. struct etm_reg *reg = cache->reg_list[i].arch_info;
  217. if (reg->reg_info->addr == id)
  218. return &cache->reg_list[i];
  219. }
  220. /* caller asking for nonexistent register is a bug! */
  221. /* REVISIT say which of the N targets was involved */
  222. LOG_ERROR("ETM: register 0x%02x not available", id);
  223. return NULL;
  224. }
  225. static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
  226. struct reg_cache *cache, struct etm_reg *ereg,
  227. const struct etm_reg_info *r, unsigned nreg)
  228. {
  229. struct reg *reg = cache->reg_list;
  230. reg += cache->num_regs;
  231. ereg += cache->num_regs;
  232. /* add up to "nreg" registers from "r", if supported by this
  233. * version of the ETM, to the specified cache.
  234. */
  235. for (; nreg--; r++) {
  236. /* this ETM may be too old to have some registers */
  237. if (r->bcd_vers > bcd_vers)
  238. continue;
  239. reg->name = r->name;
  240. reg->size = r->size;
  241. reg->value = &ereg->value;
  242. reg->arch_info = ereg;
  243. reg->type = &etm_scan6_type;
  244. reg++;
  245. cache->num_regs++;
  246. ereg->reg_info = r;
  247. ereg->jtag_info = jtag_info;
  248. ereg++;
  249. }
  250. }
  251. struct reg_cache *etm_build_reg_cache(struct target *target,
  252. struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
  253. {
  254. struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
  255. struct reg *reg_list = NULL;
  256. struct etm_reg *arch_info = NULL;
  257. unsigned bcd_vers, config;
  258. /* the actual registers are kept in two arrays */
  259. reg_list = calloc(128, sizeof(struct reg));
  260. arch_info = calloc(128, sizeof(struct etm_reg));
  261. /* fill in values for the reg cache */
  262. reg_cache->name = "etm registers";
  263. reg_cache->next = NULL;
  264. reg_cache->reg_list = reg_list;
  265. reg_cache->num_regs = 0;
  266. /* add ETM_CONFIG, then parse its values to see
  267. * which other registers exist in this ETM
  268. */
  269. etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
  270. etm_core, 1);
  271. etm_get_reg(reg_list);
  272. etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
  273. config = etm_ctx->config;
  274. /* figure ETM version then add base registers */
  275. if (config & (1 << 31)) {
  276. bcd_vers = 0x20;
  277. LOG_WARNING("ETMv2+ support is incomplete");
  278. /* REVISIT more registers may exist; they may now be
  279. * readable; more register bits have defined meanings;
  280. * don't presume trace start/stop support is present;
  281. * and include any context ID comparator registers.
  282. */
  283. etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
  284. etm_core + 1, 1);
  285. etm_get_reg(reg_list + 1);
  286. etm_ctx->id = buf_get_u32(
  287. (void *)&arch_info[1].value, 0, 32);
  288. LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
  289. bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
  290. } else {
  291. switch (config >> 28) {
  292. case 7:
  293. case 5:
  294. case 3:
  295. bcd_vers = 0x13;
  296. break;
  297. case 4:
  298. case 2:
  299. bcd_vers = 0x12;
  300. break;
  301. case 1:
  302. bcd_vers = 0x11;
  303. break;
  304. case 0:
  305. bcd_vers = 0x10;
  306. break;
  307. default:
  308. LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
  309. goto fail;
  310. }
  311. }
  312. etm_ctx->bcd_vers = bcd_vers;
  313. LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
  314. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  315. etm_basic, ARRAY_SIZE(etm_basic));
  316. /* address and data comparators; counters; outputs */
  317. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  318. etm_addr_comp, 4 * (0x0f & (config >> 0)));
  319. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  320. etm_data_comp, 2 * (0x0f & (config >> 4)));
  321. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  322. etm_counters, 4 * (0x07 & (config >> 13)));
  323. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  324. etm_outputs, (0x07 & (config >> 20)));
  325. /* FIFOFULL presence is optional
  326. * REVISIT for ETMv1.2 and later, don't bother adding this
  327. * unless ETM_SYS_CONFIG says it's also *supported* ...
  328. */
  329. if (config & (1 << 23))
  330. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  331. etm_fifofull, ARRAY_SIZE(etm_fifofull));
  332. /* sequencer is optional (for state-dependant triggering) */
  333. if (config & (1 << 16))
  334. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  335. etm_sequencer, ARRAY_SIZE(etm_sequencer));
  336. /* REVISIT could realloc and likely save half the memory
  337. * in the two chunks we allocated...
  338. */
  339. /* the ETM might have an ETB connected */
  340. if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
  341. {
  342. struct etb *etb = etm_ctx->capture_driver_priv;
  343. if (!etb)
  344. {
  345. LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
  346. goto fail;
  347. }
  348. reg_cache->next = etb_build_reg_cache(etb);
  349. etb->reg_cache = reg_cache->next;
  350. }
  351. etm_ctx->reg_cache = reg_cache;
  352. return reg_cache;
  353. fail:
  354. free(reg_cache);
  355. free(reg_list);
  356. free(arch_info);
  357. return NULL;
  358. }
  359. static int etm_read_reg(struct reg *reg)
  360. {
  361. return etm_read_reg_w_check(reg, NULL, NULL);
  362. }
  363. static int etm_store_reg(struct reg *reg)
  364. {
  365. return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
  366. }
  367. int etm_setup(struct target *target)
  368. {
  369. int retval;
  370. uint32_t etm_ctrl_value;
  371. struct arm *arm = target_to_arm(target);
  372. struct etm_context *etm_ctx = arm->etm;
  373. struct reg *etm_ctrl_reg;
  374. etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
  375. if (!etm_ctrl_reg)
  376. return ERROR_OK;
  377. /* initialize some ETM control register settings */
  378. etm_get_reg(etm_ctrl_reg);
  379. etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
  380. /* clear the ETM powerdown bit (0) */
  381. etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
  382. /* configure port width (21,6:4), mode (13,17:16) and
  383. * for older modules clocking (13)
  384. */
  385. etm_ctrl_value = (etm_ctrl_value
  386. & ~ETM_PORT_WIDTH_MASK
  387. & ~ETM_PORT_MODE_MASK
  388. & ~ETM_CTRL_DBGRQ
  389. & ~ETM_PORT_CLOCK_MASK)
  390. | etm_ctx->control;
  391. buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
  392. etm_store_reg(etm_ctrl_reg);
  393. etm_ctx->control = etm_ctrl_value;
  394. if ((retval = jtag_execute_queue()) != ERROR_OK)
  395. return retval;
  396. /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
  397. * verify that those width and mode settings are OK ...
  398. */
  399. if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
  400. {
  401. LOG_ERROR("ETM capture driver initialization failed");
  402. return retval;
  403. }
  404. return ERROR_OK;
  405. }
  406. static int etm_get_reg(struct reg *reg)
  407. {
  408. int retval;
  409. if ((retval = etm_read_reg(reg)) != ERROR_OK)
  410. {
  411. LOG_ERROR("BUG: error scheduling etm register read");
  412. return retval;
  413. }
  414. if ((retval = jtag_execute_queue()) != ERROR_OK)
  415. {
  416. LOG_ERROR("register read failed");
  417. return retval;
  418. }
  419. return ERROR_OK;
  420. }
  421. static int etm_read_reg_w_check(struct reg *reg,
  422. uint8_t* check_value, uint8_t* check_mask)
  423. {
  424. struct etm_reg *etm_reg = reg->arch_info;
  425. const struct etm_reg_info *r = etm_reg->reg_info;
  426. uint8_t reg_addr = r->addr & 0x7f;
  427. struct scan_field fields[3];
  428. if (etm_reg->reg_info->mode == WO) {
  429. LOG_ERROR("BUG: can't read write-only register %s", r->name);
  430. return ERROR_INVALID_ARGUMENTS;
  431. }
  432. LOG_DEBUG("%s (%u)", r->name, reg_addr);
  433. jtag_set_end_state(TAP_IDLE);
  434. arm_jtag_scann(etm_reg->jtag_info, 0x6);
  435. arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
  436. fields[0].tap = etm_reg->jtag_info->tap;
  437. fields[0].num_bits = 32;
  438. fields[0].out_value = reg->value;
  439. fields[0].in_value = NULL;
  440. fields[0].check_value = NULL;
  441. fields[0].check_mask = NULL;
  442. fields[1].tap = etm_reg->jtag_info->tap;
  443. fields[1].num_bits = 7;
  444. fields[1].out_value = malloc(1);
  445. buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
  446. fields[1].in_value = NULL;
  447. fields[1].check_value = NULL;
  448. fields[1].check_mask = NULL;
  449. fields[2].tap = etm_reg->jtag_info->tap;
  450. fields[2].num_bits = 1;
  451. fields[2].out_value = malloc(1);
  452. buf_set_u32(fields[2].out_value, 0, 1, 0);
  453. fields[2].in_value = NULL;
  454. fields[2].check_value = NULL;
  455. fields[2].check_mask = NULL;
  456. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  457. fields[0].in_value = reg->value;
  458. fields[0].check_value = check_value;
  459. fields[0].check_mask = check_mask;
  460. jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
  461. free(fields[1].out_value);
  462. free(fields[2].out_value);
  463. return ERROR_OK;
  464. }
  465. static int etm_set_reg(struct reg *reg, uint32_t value)
  466. {
  467. int retval;
  468. if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
  469. {
  470. LOG_ERROR("BUG: error scheduling etm register write");
  471. return retval;
  472. }
  473. buf_set_u32(reg->value, 0, reg->size, value);
  474. reg->valid = 1;
  475. reg->dirty = 0;
  476. return ERROR_OK;
  477. }
  478. static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
  479. {
  480. int retval;
  481. etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
  482. if ((retval = jtag_execute_queue()) != ERROR_OK)
  483. {
  484. LOG_ERROR("register write failed");
  485. return retval;
  486. }
  487. return ERROR_OK;
  488. }
  489. static int etm_write_reg(struct reg *reg, uint32_t value)
  490. {
  491. struct etm_reg *etm_reg = reg->arch_info;
  492. const struct etm_reg_info *r = etm_reg->reg_info;
  493. uint8_t reg_addr = r->addr & 0x7f;
  494. struct scan_field fields[3];
  495. if (etm_reg->reg_info->mode == RO) {
  496. LOG_ERROR("BUG: can't write read--only register %s", r->name);
  497. return ERROR_INVALID_ARGUMENTS;
  498. }
  499. LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
  500. jtag_set_end_state(TAP_IDLE);
  501. arm_jtag_scann(etm_reg->jtag_info, 0x6);
  502. arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
  503. fields[0].tap = etm_reg->jtag_info->tap;
  504. fields[0].num_bits = 32;
  505. uint8_t tmp1[4];
  506. fields[0].out_value = tmp1;
  507. buf_set_u32(fields[0].out_value, 0, 32, value);
  508. fields[0].in_value = NULL;
  509. fields[1].tap = etm_reg->jtag_info->tap;
  510. fields[1].num_bits = 7;
  511. uint8_t tmp2;
  512. fields[1].out_value = &tmp2;
  513. buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
  514. fields[1].in_value = NULL;
  515. fields[2].tap = etm_reg->jtag_info->tap;
  516. fields[2].num_bits = 1;
  517. uint8_t tmp3;
  518. fields[2].out_value = &tmp3;
  519. buf_set_u32(fields[2].out_value, 0, 1, 1);
  520. fields[2].in_value = NULL;
  521. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  522. return ERROR_OK;
  523. }
  524. /* ETM trace analysis functionality */
  525. static struct etm_capture_driver *etm_capture_drivers[] =
  526. {
  527. &etb_capture_driver,
  528. &etm_dummy_capture_driver,
  529. #if BUILD_OOCD_TRACE == 1
  530. &oocd_trace_capture_driver,
  531. #endif
  532. NULL
  533. };
  534. static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
  535. {
  536. int i;
  537. int section = -1;
  538. size_t size_read;
  539. uint32_t opcode;
  540. int retval;
  541. if (!ctx->image)
  542. return ERROR_TRACE_IMAGE_UNAVAILABLE;
  543. /* search for the section the current instruction belongs to */
  544. for (i = 0; i < ctx->image->num_sections; i++)
  545. {
  546. if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
  547. (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
  548. {
  549. section = i;
  550. break;
  551. }
  552. }
  553. if (section == -1)
  554. {
  555. /* current instruction couldn't be found in the image */
  556. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  557. }
  558. if (ctx->core_state == ARM_STATE_ARM)
  559. {
  560. uint8_t buf[4];
  561. if ((retval = image_read_section(ctx->image, section,
  562. ctx->current_pc - ctx->image->sections[section].base_address,
  563. 4, buf, &size_read)) != ERROR_OK)
  564. {
  565. LOG_ERROR("error while reading instruction: %i", retval);
  566. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  567. }
  568. opcode = target_buffer_get_u32(ctx->target, buf);
  569. arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
  570. }
  571. else if (ctx->core_state == ARM_STATE_THUMB)
  572. {
  573. uint8_t buf[2];
  574. if ((retval = image_read_section(ctx->image, section,
  575. ctx->current_pc - ctx->image->sections[section].base_address,
  576. 2, buf, &size_read)) != ERROR_OK)
  577. {
  578. LOG_ERROR("error while reading instruction: %i", retval);
  579. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  580. }
  581. opcode = target_buffer_get_u16(ctx->target, buf);
  582. thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
  583. }
  584. else if (ctx->core_state == ARM_STATE_JAZELLE)
  585. {
  586. LOG_ERROR("BUG: tracing of jazelle code not supported");
  587. return ERROR_FAIL;
  588. }
  589. else
  590. {
  591. LOG_ERROR("BUG: unknown core state encountered");
  592. return ERROR_FAIL;
  593. }
  594. return ERROR_OK;
  595. }
  596. static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
  597. {
  598. while (ctx->data_index < ctx->trace_depth)
  599. {
  600. /* if the caller specified an address packet offset, skip until the
  601. * we reach the n-th cycle marked with tracesync */
  602. if (apo > 0)
  603. {
  604. if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
  605. apo--;
  606. if (apo > 0)
  607. {
  608. ctx->data_index++;
  609. ctx->data_half = 0;
  610. }
  611. continue;
  612. }
  613. /* no tracedata output during a TD cycle
  614. * or in a trigger cycle */
  615. if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
  616. || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
  617. {
  618. ctx->data_index++;
  619. ctx->data_half = 0;
  620. continue;
  621. }
  622. /* FIXME there are more port widths than these... */
  623. if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
  624. {
  625. if (ctx->data_half == 0)
  626. {
  627. *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
  628. ctx->data_half = 1;
  629. }
  630. else
  631. {
  632. *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
  633. ctx->data_half = 0;
  634. ctx->data_index++;
  635. }
  636. }
  637. else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
  638. {
  639. *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
  640. ctx->data_index++;
  641. }
  642. else
  643. {
  644. /* on a 4-bit port, a packet will be output during two consecutive cycles */
  645. if (ctx->data_index > (ctx->trace_depth - 2))
  646. return -1;
  647. *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
  648. *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
  649. ctx->data_index += 2;
  650. }
  651. return 0;
  652. }
  653. return -1;
  654. }
  655. static int etmv1_branch_address(struct etm_context *ctx)
  656. {
  657. int retval;
  658. uint8_t packet;
  659. int shift = 0;
  660. int apo;
  661. uint32_t i;
  662. /* quit analysis if less than two cycles are left in the trace
  663. * because we can't extract the APO */
  664. if (ctx->data_index > (ctx->trace_depth - 2))
  665. return -1;
  666. /* a BE could be output during an APO cycle, skip the current
  667. * and continue with the new one */
  668. if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
  669. return 1;
  670. if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
  671. return 2;
  672. /* address packet offset encoded in the next two cycles' pipestat bits */
  673. apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
  674. apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
  675. /* count number of tracesync cycles between current pipe_index and data_index
  676. * i.e. the number of tracesyncs that data_index already passed by
  677. * to subtract them from the APO */
  678. for (i = ctx->pipe_index; i < ctx->data_index; i++)
  679. {
  680. if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
  681. apo--;
  682. }
  683. /* extract up to four 7-bit packets */
  684. do {
  685. if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
  686. return -1;
  687. ctx->last_branch &= ~(0x7f << shift);
  688. ctx->last_branch |= (packet & 0x7f) << shift;
  689. shift += 7;
  690. } while ((packet & 0x80) && (shift < 28));
  691. /* one last packet holding 4 bits of the address, plus the branch reason code */
  692. if ((shift == 28) && (packet & 0x80))
  693. {
  694. if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
  695. return -1;
  696. ctx->last_branch &= 0x0fffffff;
  697. ctx->last_branch |= (packet & 0x0f) << 28;
  698. ctx->last_branch_reason = (packet & 0x70) >> 4;
  699. shift += 4;
  700. }
  701. else
  702. {
  703. ctx->last_branch_reason = 0;
  704. }
  705. if (shift == 32)
  706. {
  707. ctx->pc_ok = 1;
  708. }
  709. /* if a full address was output, we might have branched into Jazelle state */
  710. if ((shift == 32) && (packet & 0x80))
  711. {
  712. ctx->core_state = ARM_STATE_JAZELLE;
  713. }
  714. else
  715. {
  716. /* if we didn't branch into Jazelle state, the current processor state is
  717. * encoded in bit 0 of the branch target address */
  718. if (ctx->last_branch & 0x1)
  719. {
  720. ctx->core_state = ARM_STATE_THUMB;
  721. ctx->last_branch &= ~0x1;
  722. }
  723. else
  724. {
  725. ctx->core_state = ARM_STATE_ARM;
  726. ctx->last_branch &= ~0x3;
  727. }
  728. }
  729. return 0;
  730. }
  731. static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
  732. {
  733. int j;
  734. uint8_t buf[4];
  735. int retval;
  736. for (j = 0; j < size; j++)
  737. {
  738. if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
  739. return -1;
  740. }
  741. if (size == 8)
  742. {
  743. LOG_ERROR("TODO: add support for 64-bit values");
  744. return -1;
  745. }
  746. else if (size == 4)
  747. *data = target_buffer_get_u32(ctx->target, buf);
  748. else if (size == 2)
  749. *data = target_buffer_get_u16(ctx->target, buf);
  750. else if (size == 1)
  751. *data = buf[0];
  752. else
  753. return -1;
  754. return 0;
  755. }
  756. static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
  757. {
  758. int retval;
  759. struct arm_instruction instruction;
  760. /* read the trace data if it wasn't read already */
  761. if (ctx->trace_depth == 0)
  762. ctx->capture_driver->read_trace(ctx);
  763. /* start at the beginning of the captured trace */
  764. ctx->pipe_index = 0;
  765. ctx->data_index = 0;
  766. ctx->data_half = 0;
  767. /* neither the PC nor the data pointer are valid */
  768. ctx->pc_ok = 0;
  769. ctx->ptr_ok = 0;
  770. while (ctx->pipe_index < ctx->trace_depth)
  771. {
  772. uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
  773. uint32_t next_pc = ctx->current_pc;
  774. uint32_t old_data_index = ctx->data_index;
  775. uint32_t old_data_half = ctx->data_half;
  776. uint32_t old_index = ctx->pipe_index;
  777. uint32_t last_instruction = ctx->last_instruction;
  778. uint32_t cycles = 0;
  779. int current_pc_ok = ctx->pc_ok;
  780. if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
  781. {
  782. command_print(cmd_ctx, "--- trigger ---");
  783. }
  784. /* instructions execute in IE/D or BE/D cycles */
  785. if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
  786. ctx->last_instruction = ctx->pipe_index;
  787. /* if we don't have a valid pc skip until we reach an indirect branch */
  788. if ((!ctx->pc_ok) && (pipestat != STAT_BE))
  789. {
  790. ctx->pipe_index++;
  791. continue;
  792. }
  793. /* any indirect branch could have interrupted instruction flow
  794. * - the branch reason code could indicate a trace discontinuity
  795. * - a branch to the exception vectors indicates an exception
  796. */
  797. if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
  798. {
  799. /* backup current data index, to be able to consume the branch address
  800. * before examining data address and values
  801. */
  802. old_data_index = ctx->data_index;
  803. old_data_half = ctx->data_half;
  804. ctx->last_instruction = ctx->pipe_index;
  805. if ((retval = etmv1_branch_address(ctx)) != 0)
  806. {
  807. /* negative return value from etmv1_branch_address means we ran out of packets,
  808. * quit analysing the trace */
  809. if (retval < 0)
  810. break;
  811. /* a positive return values means the current branch was abandoned,
  812. * and a new branch was encountered in cycle ctx->pipe_index + retval;
  813. */
  814. LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
  815. ctx->pipe_index += retval;
  816. continue;
  817. }
  818. /* skip over APO cycles */
  819. ctx->pipe_index += 2;
  820. switch (ctx->last_branch_reason)
  821. {
  822. case 0x0: /* normal PC change */
  823. next_pc = ctx->last_branch;
  824. break;
  825. case 0x1: /* tracing enabled */
  826. command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
  827. ctx->current_pc = ctx->last_branch;
  828. ctx->pipe_index++;
  829. continue;
  830. break;
  831. case 0x2: /* trace restarted after FIFO overflow */
  832. command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
  833. ctx->current_pc = ctx->last_branch;
  834. ctx->pipe_index++;
  835. continue;
  836. break;
  837. case 0x3: /* exit from debug state */
  838. command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
  839. ctx->current_pc = ctx->last_branch;
  840. ctx->pipe_index++;
  841. continue;
  842. break;
  843. case 0x4: /* periodic synchronization point */
  844. next_pc = ctx->last_branch;
  845. /* if we had no valid PC prior to this synchronization point,
  846. * we have to move on with the next trace cycle
  847. */
  848. if (!current_pc_ok)
  849. {
  850. command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
  851. ctx->current_pc = next_pc;
  852. ctx->pipe_index++;
  853. continue;
  854. }
  855. break;
  856. default: /* reserved */
  857. LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
  858. return ERROR_FAIL;
  859. }
  860. /* if we got here the branch was a normal PC change
  861. * (or a periodic synchronization point, which means the same for that matter)
  862. * if we didn't accquire a complete PC continue with the next cycle
  863. */
  864. if (!ctx->pc_ok)
  865. continue;
  866. /* indirect branch to the exception vector means an exception occured */
  867. if ((ctx->last_branch <= 0x20)
  868. || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
  869. {
  870. if ((ctx->last_branch & 0xff) == 0x10)
  871. {
  872. command_print(cmd_ctx, "data abort");
  873. }
  874. else
  875. {
  876. command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
  877. ctx->current_pc = ctx->last_branch;
  878. ctx->pipe_index++;
  879. continue;
  880. }
  881. }
  882. }
  883. /* an instruction was executed (or not, depending on the condition flags)
  884. * retrieve it from the image for displaying */
  885. if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
  886. !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
  887. ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
  888. {
  889. if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
  890. {
  891. /* can't continue tracing with no image available */
  892. if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
  893. {
  894. return retval;
  895. }
  896. else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
  897. {
  898. /* TODO: handle incomplete images
  899. * for now we just quit the analsysis*/
  900. return retval;
  901. }
  902. }
  903. cycles = old_index - last_instruction;
  904. }
  905. if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
  906. {
  907. uint32_t new_data_index = ctx->data_index;
  908. uint32_t new_data_half = ctx->data_half;
  909. /* in case of a branch with data, the branch target address was consumed before
  910. * we temporarily go back to the saved data index */
  911. if (pipestat == STAT_BD)
  912. {
  913. ctx->data_index = old_data_index;
  914. ctx->data_half = old_data_half;
  915. }
  916. if (ctx->control & ETM_CTRL_TRACE_ADDR)
  917. {
  918. uint8_t packet;
  919. int shift = 0;
  920. do {
  921. if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
  922. return ERROR_ETM_ANALYSIS_FAILED;
  923. ctx->last_ptr &= ~(0x7f << shift);
  924. ctx->last_ptr |= (packet & 0x7f) << shift;
  925. shift += 7;
  926. } while ((packet & 0x80) && (shift < 32));
  927. if (shift >= 32)
  928. ctx->ptr_ok = 1;
  929. if (ctx->ptr_ok)
  930. {
  931. command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
  932. }
  933. }
  934. if (ctx->control & ETM_CTRL_TRACE_DATA)
  935. {
  936. if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
  937. {
  938. int i;
  939. for (i = 0; i < 16; i++)
  940. {
  941. if (instruction.info.load_store_multiple.register_list & (1 << i))
  942. {
  943. uint32_t data;
  944. if (etmv1_data(ctx, 4, &data) != 0)
  945. return ERROR_ETM_ANALYSIS_FAILED;
  946. command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
  947. }
  948. }
  949. }
  950. else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
  951. {
  952. uint32_t data;
  953. if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
  954. return ERROR_ETM_ANALYSIS_FAILED;
  955. command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
  956. }
  957. }
  958. /* restore data index after consuming BD address and data */
  959. if (pipestat == STAT_BD)
  960. {
  961. ctx->data_index = new_data_index;
  962. ctx->data_half = new_data_half;
  963. }
  964. }
  965. /* adjust PC */
  966. if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
  967. {
  968. if (((instruction.type == ARM_B) ||
  969. (instruction.type == ARM_BL) ||
  970. (instruction.type == ARM_BLX)) &&
  971. (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
  972. {
  973. next_pc = instruction.info.b_bl_bx_blx.target_address;
  974. }
  975. else
  976. {
  977. next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
  978. }
  979. }
  980. else if (pipestat == STAT_IN)
  981. {
  982. next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
  983. }
  984. if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
  985. {
  986. char cycles_text[32] = "";
  987. /* if the trace was captured with cycle accurate tracing enabled,
  988. * output the number of cycles since the last executed instruction
  989. */
  990. if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
  991. {
  992. snprintf(cycles_text, 32, " (%i %s)",
  993. (int)cycles,
  994. (cycles == 1) ? "cycle" : "cycles");
  995. }
  996. command_print(cmd_ctx, "%s%s%s",
  997. instruction.text,
  998. (pipestat == STAT_IN) ? " (not executed)" : "",
  999. cycles_text);
  1000. ctx->current_pc = next_pc;
  1001. /* packets for an instruction don't start on or before the preceding
  1002. * functional pipestat (i.e. other than WT or TD)
  1003. */
  1004. if (ctx->data_index <= ctx->pipe_index)
  1005. {
  1006. ctx->data_index = ctx->pipe_index + 1;
  1007. ctx->data_half = 0;
  1008. }
  1009. }
  1010. ctx->pipe_index += 1;
  1011. }
  1012. return ERROR_OK;
  1013. }
  1014. static COMMAND_HELPER(handle_etm_tracemode_command_update,
  1015. uint32_t *mode)
  1016. {
  1017. uint32_t tracemode;
  1018. /* what parts of data access are traced? */
  1019. if (strcmp(CMD_ARGV[0], "none") == 0)
  1020. tracemode = 0;
  1021. else if (strcmp(CMD_ARGV[0], "data") == 0)
  1022. tracemode = ETM_CTRL_TRACE_DATA;
  1023. else if (strcmp(CMD_ARGV[0], "address") == 0)
  1024. tracemode = ETM_CTRL_TRACE_ADDR;
  1025. else if (strcmp(CMD_ARGV[0], "all") == 0)
  1026. tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
  1027. else
  1028. {
  1029. command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
  1030. return ERROR_INVALID_ARGUMENTS;
  1031. }
  1032. uint8_t context_id;
  1033. COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
  1034. switch (context_id)
  1035. {
  1036. case 0:
  1037. tracemode |= ETM_CTRL_CONTEXTID_NONE;
  1038. break;
  1039. case 8:
  1040. tracemode |= ETM_CTRL_CONTEXTID_8;
  1041. break;
  1042. case 16:
  1043. tracemode |= ETM_CTRL_CONTEXTID_16;
  1044. break;
  1045. case 32:
  1046. tracemode |= ETM_CTRL_CONTEXTID_32;
  1047. break;
  1048. default:
  1049. command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
  1050. return ERROR_INVALID_ARGUMENTS;
  1051. }
  1052. bool etmv1_cycle_accurate;
  1053. COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
  1054. if (etmv1_cycle_accurate)
  1055. tracemode |= ETM_CTRL_CYCLE_ACCURATE;
  1056. bool etmv1_branch_output;
  1057. COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
  1058. if (etmv1_branch_output)
  1059. tracemode |= ETM_CTRL_BRANCH_OUTPUT;
  1060. /* IGNORED:
  1061. * - CPRT tracing (coprocessor register transfers)
  1062. * - debug request (causes debug entry on trigger)
  1063. * - stall on FIFOFULL (preventing tracedata lossage)
  1064. */
  1065. *mode = tracemode;
  1066. return ERROR_OK;
  1067. }
  1068. COMMAND_HANDLER(handle_etm_tracemode_command)
  1069. {
  1070. struct target *target = get_current_target(CMD_CTX);
  1071. struct arm *arm = target_to_arm(target);
  1072. struct etm_context *etm;
  1073. if (!is_arm(arm)) {
  1074. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1075. return ERROR_FAIL;
  1076. }
  1077. etm = arm->etm;
  1078. if (!etm) {
  1079. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1080. return ERROR_FAIL;
  1081. }
  1082. uint32_t tracemode = etm->control;
  1083. switch (CMD_ARGC)
  1084. {
  1085. case 0:
  1086. break;
  1087. case 4:
  1088. CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
  1089. &tracemode);
  1090. break;
  1091. default:
  1092. command_print(CMD_CTX, "usage: tracemode "
  1093. "('none'|'data'|'address'|'all') "
  1094. "context_id_bits "
  1095. "('enable'|'disable') "
  1096. "('enable'|'disable')"
  1097. );
  1098. return ERROR_FAIL;
  1099. }
  1100. /**
  1101. * todo: fail if parameters were invalid for this hardware,
  1102. * or couldn't be written; display actual hardware state...
  1103. */
  1104. command_print(CMD_CTX, "current tracemode configuration:");
  1105. switch (tracemode & ETM_CTRL_TRACE_MASK)
  1106. {
  1107. default:
  1108. command_print(CMD_CTX, "data tracing: none");
  1109. break;
  1110. case ETM_CTRL_TRACE_DATA:
  1111. command_print(CMD_CTX, "data tracing: data only");
  1112. break;
  1113. case ETM_CTRL_TRACE_ADDR:
  1114. command_print(CMD_CTX, "data tracing: address only");
  1115. break;
  1116. case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
  1117. command_print(CMD_CTX, "data tracing: address and data");
  1118. break;
  1119. }
  1120. switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
  1121. {
  1122. case ETM_CTRL_CONTEXTID_NONE:
  1123. command_print(CMD_CTX, "contextid tracing: none");
  1124. break;
  1125. case ETM_CTRL_CONTEXTID_8:
  1126. command_print(CMD_CTX, "contextid tracing: 8 bit");
  1127. break;
  1128. case ETM_CTRL_CONTEXTID_16:
  1129. command_print(CMD_CTX, "contextid tracing: 16 bit");
  1130. break;
  1131. case ETM_CTRL_CONTEXTID_32:
  1132. command_print(CMD_CTX, "contextid tracing: 32 bit");
  1133. break;
  1134. }
  1135. if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
  1136. {
  1137. command_print(CMD_CTX, "cycle-accurate tracing enabled");
  1138. }
  1139. else
  1140. {
  1141. command_print(CMD_CTX, "cycle-accurate tracing disabled");
  1142. }
  1143. if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
  1144. {
  1145. command_print(CMD_CTX, "full branch address output enabled");
  1146. }
  1147. else
  1148. {
  1149. command_print(CMD_CTX, "full branch address output disabled");
  1150. }
  1151. #define TRACEMODE_MASK ( \
  1152. ETM_CTRL_CONTEXTID_MASK \
  1153. | ETM_CTRL_BRANCH_OUTPUT \
  1154. | ETM_CTRL_CYCLE_ACCURATE \
  1155. | ETM_CTRL_TRACE_MASK \
  1156. )
  1157. /* only update ETM_CTRL register if tracemode changed */
  1158. if ((etm->control & TRACEMODE_MASK) != tracemode)
  1159. {
  1160. struct reg *etm_ctrl_reg;
  1161. etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
  1162. if (!etm_ctrl_reg)
  1163. return ERROR_FAIL;
  1164. etm->control &= ~TRACEMODE_MASK;
  1165. etm->control |= tracemode & TRACEMODE_MASK;
  1166. buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
  1167. etm_store_reg(etm_ctrl_reg);
  1168. /* invalidate old trace data */
  1169. etm->capture_status = TRACE_IDLE;
  1170. if (etm->trace_depth > 0)
  1171. {
  1172. free(etm->trace_data);
  1173. etm->trace_data = NULL;
  1174. }
  1175. etm->trace_depth = 0;
  1176. }
  1177. #undef TRACEMODE_MASK
  1178. return ERROR_OK;
  1179. }
  1180. COMMAND_HANDLER(handle_etm_config_command)
  1181. {
  1182. struct target *target;
  1183. struct arm *arm;
  1184. uint32_t portmode = 0x0;
  1185. struct etm_context *etm_ctx;
  1186. int i;
  1187. if (CMD_ARGC != 5)
  1188. return ERROR_COMMAND_SYNTAX_ERROR;
  1189. target = get_target(CMD_ARGV[0]);
  1190. if (!target)
  1191. {
  1192. LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
  1193. return ERROR_FAIL;
  1194. }
  1195. arm = target_to_arm(target);
  1196. if (!is_arm(arm)) {
  1197. command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
  1198. target_name(target),
  1199. target_type_name(target));
  1200. return ERROR_FAIL;
  1201. }
  1202. /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
  1203. * version we'll be using!! -- so we can't know how to validate
  1204. * params yet. "etm config" should likely be *AFTER* hookup...
  1205. *
  1206. * - Many more widths might be supported ... and we can easily
  1207. * check whether our setting "took".
  1208. *
  1209. * - The "clock" and "mode" bits are interpreted differently.
  1210. * See ARM IHI 0014O table 2-17 for the old behavior, and
  1211. * table 2-18 for the new. With ETB it's best to specify
  1212. * "normal full" ...
  1213. */
  1214. uint8_t port_width;
  1215. COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
  1216. switch (port_width)
  1217. {
  1218. /* before ETMv3.0 */
  1219. case 4:
  1220. portmode |= ETM_PORT_4BIT;
  1221. break;
  1222. case 8:
  1223. portmode |= ETM_PORT_8BIT;
  1224. break;
  1225. case 16:
  1226. portmode |= ETM_PORT_16BIT;
  1227. break;
  1228. /* ETMv3.0 and later*/
  1229. case 24:
  1230. portmode |= ETM_PORT_24BIT;
  1231. break;
  1232. case 32:
  1233. portmode |= ETM_PORT_32BIT;
  1234. break;
  1235. case 48:
  1236. portmode |= ETM_PORT_48BIT;
  1237. break;
  1238. case 64:
  1239. portmode |= ETM_PORT_64BIT;
  1240. break;
  1241. case 1:
  1242. portmode |= ETM_PORT_1BIT;
  1243. break;
  1244. case 2:
  1245. portmode |= ETM_PORT_2BIT;
  1246. break;
  1247. default:
  1248. command_print(CMD_CTX,
  1249. "unsupported ETM port width '%s'", CMD_ARGV[1]);
  1250. return ERROR_FAIL;
  1251. }
  1252. if (strcmp("normal", CMD_ARGV[2]) == 0)
  1253. {
  1254. portmode |= ETM_PORT_NORMAL;
  1255. }
  1256. else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
  1257. {
  1258. portmode |= ETM_PORT_MUXED;
  1259. }
  1260. else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
  1261. {
  1262. portmode |= ETM_PORT_DEMUXED;
  1263. }
  1264. else
  1265. {
  1266. command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
  1267. return ERROR_FAIL;
  1268. }
  1269. if (strcmp("half", CMD_ARGV[3]) == 0)
  1270. {
  1271. portmode |= ETM_PORT_HALF_CLOCK;
  1272. }
  1273. else if (strcmp("full", CMD_ARGV[3]) == 0)
  1274. {
  1275. portmode |= ETM_PORT_FULL_CLOCK;
  1276. }
  1277. else
  1278. {
  1279. command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
  1280. return ERROR_FAIL;
  1281. }
  1282. etm_ctx = calloc(1, sizeof(struct etm_context));
  1283. if (!etm_ctx) {
  1284. LOG_DEBUG("out of memory");
  1285. return ERROR_FAIL;
  1286. }
  1287. for (i = 0; etm_capture_drivers[i]; i++)
  1288. {
  1289. if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
  1290. {
  1291. int retval = register_commands(CMD_CTX, NULL,
  1292. etm_capture_drivers[i]->commands);
  1293. if (ERROR_OK != retval)
  1294. {
  1295. free(etm_ctx);
  1296. return retval;
  1297. }
  1298. etm_ctx->capture_driver = etm_capture_drivers[i];
  1299. break;
  1300. }
  1301. }
  1302. if (!etm_capture_drivers[i])
  1303. {
  1304. /* no supported capture driver found, don't register an ETM */
  1305. free(etm_ctx);
  1306. LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
  1307. return ERROR_FAIL;
  1308. }
  1309. etm_ctx->target = target;
  1310. etm_ctx->trace_data = NULL;
  1311. etm_ctx->control = portmode;
  1312. etm_ctx->core_state = ARM_STATE_ARM;
  1313. arm->etm = etm_ctx;
  1314. return etm_register_user_commands(CMD_CTX);
  1315. }
  1316. COMMAND_HANDLER(handle_etm_info_command)
  1317. {
  1318. struct target *target;
  1319. struct arm *arm;
  1320. struct etm_context *etm;
  1321. struct reg *etm_sys_config_reg;
  1322. int max_port_size;
  1323. uint32_t config;
  1324. target = get_current_target(CMD_CTX);
  1325. arm = target_to_arm(target);
  1326. if (!is_arm(arm))
  1327. {
  1328. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1329. return ERROR_FAIL;
  1330. }
  1331. etm = arm->etm;
  1332. if (!etm)
  1333. {
  1334. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1335. return ERROR_FAIL;
  1336. }
  1337. command_print(CMD_CTX, "ETM v%d.%d",
  1338. etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
  1339. command_print(CMD_CTX, "pairs of address comparators: %i",
  1340. (int) (etm->config >> 0) & 0x0f);
  1341. command_print(CMD_CTX, "data comparators: %i",
  1342. (int) (etm->config >> 4) & 0x0f);
  1343. command_print(CMD_CTX, "memory map decoders: %i",
  1344. (int) (etm->config >> 8) & 0x1f);
  1345. command_print(CMD_CTX, "number of counters: %i",
  1346. (int) (etm->config >> 13) & 0x07);
  1347. command_print(CMD_CTX, "sequencer %spresent",
  1348. (int) (etm->config & (1 << 16)) ? "" : "not ");
  1349. command_print(CMD_CTX, "number of ext. inputs: %i",
  1350. (int) (etm->config >> 17) & 0x07);
  1351. command_print(CMD_CTX, "number of ext. outputs: %i",
  1352. (int) (etm->config >> 20) & 0x07);
  1353. command_print(CMD_CTX, "FIFO full %spresent",
  1354. (int) (etm->config & (1 << 23)) ? "" : "not ");
  1355. if (etm->bcd_vers < 0x20)
  1356. command_print(CMD_CTX, "protocol version: %i",
  1357. (int) (etm->config >> 28) & 0x07);
  1358. else {
  1359. command_print(CMD_CTX,
  1360. "coprocessor and memory access %ssupported",
  1361. (etm->config & (1 << 26)) ? "" : "not ");
  1362. command_print(CMD_CTX, "trace start/stop %spresent",
  1363. (etm->config & (1 << 26)) ? "" : "not ");
  1364. command_print(CMD_CTX, "number of context comparators: %i",
  1365. (int) (etm->config >> 24) & 0x03);
  1366. }
  1367. /* SYS_CONFIG isn't present before ETMv1.2 */
  1368. etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
  1369. if (!etm_sys_config_reg)
  1370. return ERROR_OK;
  1371. etm_get_reg(etm_sys_config_reg);
  1372. config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
  1373. LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
  1374. max_port_size = config & 0x7;
  1375. if (etm->bcd_vers >= 0x30)
  1376. max_port_size |= (config >> 6) & 0x08;
  1377. switch (max_port_size)
  1378. {
  1379. /* before ETMv3.0 */
  1380. case 0:
  1381. max_port_size = 4;
  1382. break;
  1383. case 1:
  1384. max_port_size = 8;
  1385. break;
  1386. case 2:
  1387. max_port_size = 16;
  1388. break;
  1389. /* ETMv3.0 and later*/
  1390. case 3:
  1391. max_port_size = 24;
  1392. break;
  1393. case 4:
  1394. max_port_size = 32;
  1395. break;
  1396. case 5:
  1397. max_port_size = 48;
  1398. break;
  1399. case 6:
  1400. max_port_size = 64;
  1401. break;
  1402. case 8:
  1403. max_port_size = 1;
  1404. break;
  1405. case 9:
  1406. max_port_size = 2;
  1407. break;
  1408. default:
  1409. LOG_ERROR("Illegal max_port_size");
  1410. return ERROR_FAIL;
  1411. }
  1412. command_print(CMD_CTX, "max. port size: %i", max_port_size);
  1413. if (etm->bcd_vers < 0x30) {
  1414. command_print(CMD_CTX, "half-rate clocking %ssupported",
  1415. (config & (1 << 3)) ? "" : "not ");
  1416. command_print(CMD_CTX, "full-rate clocking %ssupported",
  1417. (config & (1 << 4)) ? "" : "not ");
  1418. command_print(CMD_CTX, "normal trace format %ssupported",
  1419. (config & (1 << 5)) ? "" : "not ");
  1420. command_print(CMD_CTX, "multiplex trace format %ssupported",
  1421. (config & (1 << 6)) ? "" : "not ");
  1422. command_print(CMD_CTX, "demultiplex trace format %ssupported",
  1423. (config & (1 << 7)) ? "" : "not ");
  1424. } else {
  1425. /* REVISIT show which size and format are selected ... */
  1426. command_print(CMD_CTX, "current port size %ssupported",
  1427. (config & (1 << 10)) ? "" : "not ");
  1428. command_print(CMD_CTX, "current trace format %ssupported",
  1429. (config & (1 << 11)) ? "" : "not ");
  1430. }
  1431. if (etm->bcd_vers >= 0x21)
  1432. command_print(CMD_CTX, "fetch comparisons %ssupported",
  1433. (config & (1 << 17)) ? "not " : "");
  1434. command_print(CMD_CTX, "FIFO full %ssupported",
  1435. (config & (1 << 8)) ? "" : "not ");
  1436. return ERROR_OK;
  1437. }
  1438. COMMAND_HANDLER(handle_etm_status_command)
  1439. {
  1440. struct target *target;
  1441. struct arm *arm;
  1442. struct etm_context *etm;
  1443. trace_status_t trace_status;
  1444. target = get_current_target(CMD_CTX);
  1445. arm = target_to_arm(target);
  1446. if (!is_arm(arm))
  1447. {
  1448. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1449. return ERROR_FAIL;
  1450. }
  1451. etm = arm->etm;
  1452. if (!etm)
  1453. {
  1454. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1455. return ERROR_FAIL;
  1456. }
  1457. /* ETM status */
  1458. if (etm->bcd_vers >= 0x11) {
  1459. struct reg *reg;
  1460. reg = etm_reg_lookup(etm, ETM_STATUS);
  1461. if (!reg)
  1462. return ERROR_FAIL;
  1463. if (etm_get_reg(reg) == ERROR_OK) {
  1464. unsigned s = buf_get_u32(reg->value, 0, reg->size);
  1465. command_print(CMD_CTX, "etm: %s%s%s%s",
  1466. /* bit(1) == progbit */
  1467. (etm->bcd_vers >= 0x12)
  1468. ? ((s & (1 << 1))
  1469. ? "disabled" : "enabled")
  1470. : "?",
  1471. ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
  1472. ? " triggered" : "",
  1473. ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
  1474. ? " start/stop" : "",
  1475. ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
  1476. ? " untraced-overflow" : "");
  1477. } /* else ignore and try showing trace port status */
  1478. }
  1479. /* Trace Port Driver status */
  1480. trace_status = etm->capture_driver->status(etm);
  1481. if (trace_status == TRACE_IDLE)
  1482. {
  1483. command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
  1484. }
  1485. else
  1486. {
  1487. static char *completed = " completed";
  1488. static char *running = " is running";
  1489. static char *overflowed = ", overflowed";
  1490. static char *triggered = ", triggered";
  1491. command_print(CMD_CTX, "%s: trace collection%s%s%s",
  1492. etm->capture_driver->name,
  1493. (trace_status & TRACE_RUNNING) ? running : completed,
  1494. (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
  1495. (trace_status & TRACE_TRIGGERED) ? triggered : "");
  1496. if (etm->trace_depth > 0)
  1497. {
  1498. command_print(CMD_CTX, "%i frames of trace data read",
  1499. (int)(etm->trace_depth));
  1500. }
  1501. }
  1502. return ERROR_OK;
  1503. }
  1504. COMMAND_HANDLER(handle_etm_image_command)
  1505. {
  1506. struct target *target;
  1507. struct arm *arm;
  1508. struct etm_context *etm_ctx;
  1509. if (CMD_ARGC < 1)
  1510. {
  1511. command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
  1512. return ERROR_FAIL;
  1513. }
  1514. target = get_current_target(CMD_CTX);
  1515. arm = target_to_arm(target);
  1516. if (!is_arm(arm))
  1517. {
  1518. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1519. return ERROR_FAIL;
  1520. }
  1521. etm_ctx = arm->etm;
  1522. if (!etm_ctx)
  1523. {
  1524. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1525. return ERROR_FAIL;
  1526. }
  1527. if (etm_ctx->image)
  1528. {
  1529. image_close(etm_ctx->image);
  1530. free(etm_ctx->image);
  1531. command_print(CMD_CTX, "previously loaded image found and closed");
  1532. }
  1533. etm_ctx->image = malloc(sizeof(struct image));
  1534. etm_ctx->image->base_address_set = 0;
  1535. etm_ctx->image->start_address_set = 0;
  1536. /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
  1537. if (CMD_ARGC >= 2)
  1538. {
  1539. etm_ctx->image->base_address_set = 1;
  1540. COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
  1541. }
  1542. else
  1543. {
  1544. etm_ctx->image->base_address_set = 0;
  1545. }
  1546. if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
  1547. {
  1548. free(etm_ctx->image);
  1549. etm_ctx->image = NULL;
  1550. return ERROR_FAIL;
  1551. }
  1552. return ERROR_OK;
  1553. }
  1554. COMMAND_HANDLER(handle_etm_dump_command)
  1555. {
  1556. struct fileio file;
  1557. struct target *target;
  1558. struct arm *arm;
  1559. struct etm_context *etm_ctx;
  1560. uint32_t i;
  1561. if (CMD_ARGC != 1)
  1562. {
  1563. command_print(CMD_CTX, "usage: etm dump <file>");
  1564. return ERROR_FAIL;
  1565. }
  1566. target = get_current_target(CMD_CTX);
  1567. arm = target_to_arm(target);
  1568. if (!is_arm(arm))
  1569. {
  1570. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1571. return ERROR_FAIL;
  1572. }
  1573. etm_ctx = arm->etm;
  1574. if (!etm_ctx)
  1575. {
  1576. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1577. return ERROR_FAIL;
  1578. }
  1579. if (etm_ctx->capture_driver->status == TRACE_IDLE)
  1580. {
  1581. command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
  1582. return ERROR_OK;
  1583. }
  1584. if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
  1585. {
  1586. /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
  1587. command_print(CMD_CTX, "trace capture not completed");
  1588. return ERROR_FAIL;
  1589. }
  1590. /* read the trace data if it wasn't read already */
  1591. if (etm_ctx->trace_depth == 0)
  1592. etm_ctx->capture_driver->read_trace(etm_ctx);
  1593. if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
  1594. {
  1595. return ERROR_FAIL;
  1596. }
  1597. fileio_write_u32(&file, etm_ctx->capture_status);
  1598. fileio_write_u32(&file, etm_ctx->control);
  1599. fileio_write_u32(&file, etm_ctx->trace_depth);
  1600. for (i = 0; i < etm_ctx->trace_depth; i++)
  1601. {
  1602. fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
  1603. fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
  1604. fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
  1605. }
  1606. fileio_close(&file);
  1607. return ERROR_OK;
  1608. }
  1609. COMMAND_HANDLER(handle_etm_load_command)
  1610. {
  1611. struct fileio file;
  1612. struct target *target;
  1613. struct arm *arm;
  1614. struct etm_context *etm_ctx;
  1615. uint32_t i;
  1616. if (CMD_ARGC != 1)
  1617. {
  1618. command_print(CMD_CTX, "usage: etm load <file>");
  1619. return ERROR_FAIL;
  1620. }
  1621. target = get_current_target(CMD_CTX);
  1622. arm = target_to_arm(target);
  1623. if (!is_arm(arm))
  1624. {
  1625. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1626. return ERROR_FAIL;
  1627. }
  1628. etm_ctx = arm->etm;
  1629. if (!etm_ctx)
  1630. {
  1631. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1632. return ERROR_FAIL;
  1633. }
  1634. if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
  1635. {
  1636. command_print(CMD_CTX, "trace capture running, stop first");
  1637. return ERROR_FAIL;
  1638. }
  1639. if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
  1640. {
  1641. return ERROR_FAIL;
  1642. }
  1643. if (file.size % 4)
  1644. {
  1645. command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
  1646. fileio_close(&file);
  1647. return ERROR_FAIL;
  1648. }
  1649. if (etm_ctx->trace_depth > 0)
  1650. {
  1651. free(etm_ctx->trace_data);
  1652. etm_ctx->trace_data = NULL;
  1653. }
  1654. {
  1655. uint32_t tmp;
  1656. fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
  1657. fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
  1658. fileio_read_u32(&file, &etm_ctx->trace_depth);
  1659. }
  1660. etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
  1661. if (etm_ctx->trace_data == NULL)
  1662. {
  1663. command_print(CMD_CTX, "not enough memory to perform operation");
  1664. fileio_close(&file);
  1665. return ERROR_FAIL;
  1666. }
  1667. for (i = 0; i < etm_ctx->trace_depth; i++)
  1668. {
  1669. uint32_t pipestat, packet, flags;
  1670. fileio_read_u32(&file, &pipestat);
  1671. fileio_read_u32(&file, &packet);
  1672. fileio_read_u32(&file, &flags);
  1673. etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
  1674. etm_ctx->trace_data[i].packet = packet & 0xffff;
  1675. etm_ctx->trace_data[i].flags = flags;
  1676. }
  1677. fileio_close(&file);
  1678. return ERROR_OK;
  1679. }
  1680. COMMAND_HANDLER(handle_etm_start_command)
  1681. {
  1682. struct target *target;
  1683. struct arm *arm;
  1684. struct etm_context *etm_ctx;
  1685. struct reg *etm_ctrl_reg;
  1686. target = get_current_target(CMD_CTX);
  1687. arm = target_to_arm(target);
  1688. if (!is_arm(arm))
  1689. {
  1690. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1691. return ERROR_FAIL;
  1692. }
  1693. etm_ctx = arm->etm;
  1694. if (!etm_ctx)
  1695. {
  1696. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1697. return ERROR_FAIL;
  1698. }
  1699. /* invalidate old tracing data */
  1700. etm_ctx->capture_status = TRACE_IDLE;
  1701. if (etm_ctx->trace_depth > 0)
  1702. {
  1703. free(etm_ctx->trace_data);
  1704. etm_ctx->trace_data = NULL;
  1705. }
  1706. etm_ctx->trace_depth = 0;
  1707. etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
  1708. if (!etm_ctrl_reg)
  1709. return ERROR_FAIL;
  1710. etm_get_reg(etm_ctrl_reg);
  1711. /* Clear programming bit (10), set port selection bit (11) */
  1712. buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
  1713. etm_store_reg(etm_ctrl_reg);
  1714. jtag_execute_queue();
  1715. etm_ctx->capture_driver->start_capture(etm_ctx);
  1716. return ERROR_OK;
  1717. }
  1718. COMMAND_HANDLER(handle_etm_stop_command)
  1719. {
  1720. struct target *target;
  1721. struct arm *arm;
  1722. struct etm_context *etm_ctx;
  1723. struct reg *etm_ctrl_reg;
  1724. target = get_current_target(CMD_CTX);
  1725. arm = target_to_arm(target);
  1726. if (!is_arm(arm))
  1727. {
  1728. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1729. return ERROR_FAIL;
  1730. }
  1731. etm_ctx = arm->etm;
  1732. if (!etm_ctx)
  1733. {
  1734. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1735. return ERROR_FAIL;
  1736. }
  1737. etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
  1738. if (!etm_ctrl_reg)
  1739. return ERROR_FAIL;
  1740. etm_get_reg(etm_ctrl_reg);
  1741. /* Set programming bit (10), clear port selection bit (11) */
  1742. buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
  1743. etm_store_reg(etm_ctrl_reg);
  1744. jtag_execute_queue();
  1745. etm_ctx->capture_driver->stop_capture(etm_ctx);
  1746. return ERROR_OK;
  1747. }
  1748. COMMAND_HANDLER(handle_etm_trigger_debug_command)
  1749. {
  1750. struct target *target;
  1751. struct arm *arm;
  1752. struct etm_context *etm;
  1753. target = get_current_target(CMD_CTX);
  1754. arm = target_to_arm(target);
  1755. if (!is_arm(arm))
  1756. {
  1757. command_print(CMD_CTX, "ETM: %s isn't an ARM",
  1758. target_name(target));
  1759. return ERROR_FAIL;
  1760. }
  1761. etm = arm->etm;
  1762. if (!etm)
  1763. {
  1764. command_print(CMD_CTX, "ETM: no ETM configured for %s",
  1765. target_name(target));
  1766. return ERROR_FAIL;
  1767. }
  1768. if (CMD_ARGC == 1) {
  1769. struct reg *etm_ctrl_reg;
  1770. bool dbgrq;
  1771. etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
  1772. if (!etm_ctrl_reg)
  1773. return ERROR_FAIL;
  1774. COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
  1775. if (dbgrq)
  1776. etm->control |= ETM_CTRL_DBGRQ;
  1777. else
  1778. etm->control &= ~ETM_CTRL_DBGRQ;
  1779. /* etm->control will be written to hardware
  1780. * the next time an "etm start" is issued.
  1781. */
  1782. buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
  1783. }
  1784. command_print(CMD_CTX, "ETM: %s debug halt",
  1785. (etm->control & ETM_CTRL_DBGRQ)
  1786. ? "triggers"
  1787. : "does not trigger");
  1788. return ERROR_OK;
  1789. }
  1790. COMMAND_HANDLER(handle_etm_analyze_command)
  1791. {
  1792. struct target *target;
  1793. struct arm *arm;
  1794. struct etm_context *etm_ctx;
  1795. int retval;
  1796. target = get_current_target(CMD_CTX);
  1797. arm = target_to_arm(target);
  1798. if (!is_arm(arm))
  1799. {
  1800. command_print(CMD_CTX, "ETM: current target isn't an ARM");
  1801. return ERROR_FAIL;
  1802. }
  1803. etm_ctx = arm->etm;
  1804. if (!etm_ctx)
  1805. {
  1806. command_print(CMD_CTX, "current target doesn't have an ETM configured");
  1807. return ERROR_FAIL;
  1808. }
  1809. if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
  1810. {
  1811. switch (retval)
  1812. {
  1813. case ERROR_ETM_ANALYSIS_FAILED:
  1814. command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
  1815. break;
  1816. case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
  1817. command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
  1818. break;
  1819. case ERROR_TRACE_IMAGE_UNAVAILABLE:
  1820. command_print(CMD_CTX, "no image available for trace analysis");
  1821. break;
  1822. default:
  1823. command_print(CMD_CTX, "unknown error: %i", retval);
  1824. }
  1825. }
  1826. return retval;
  1827. }
  1828. static const struct command_registration etm_config_command_handlers[] = {
  1829. {
  1830. /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
  1831. * possibly over SWD, not JTAG scanchain 6 of 'target'.
  1832. *
  1833. * Also, these parameters don't match ETM v3+ modules...
  1834. */
  1835. .name = "config",
  1836. .handler = handle_etm_config_command,
  1837. .mode = COMMAND_CONFIG,
  1838. .help = "Set up ETM output port.",
  1839. .usage = "target port_width port_mode clocking capture_driver",
  1840. },
  1841. COMMAND_REGISTRATION_DONE
  1842. };
  1843. const struct command_registration etm_command_handlers[] = {
  1844. {
  1845. .name = "etm",
  1846. .mode = COMMAND_ANY,
  1847. .help = "Emebdded Trace Macrocell command group",
  1848. .chain = etm_config_command_handlers,
  1849. },
  1850. COMMAND_REGISTRATION_DONE
  1851. };
  1852. static const struct command_registration etm_exec_command_handlers[] = {
  1853. {
  1854. .name = "tracemode",
  1855. .handler = handle_etm_tracemode_command,
  1856. .mode = COMMAND_EXEC,
  1857. .help = "configure/display trace mode",
  1858. .usage = "('none'|'data'|'address'|'all') "
  1859. "context_id_bits "
  1860. "['enable'|'disable'] "
  1861. "['enable'|'disable']",
  1862. },
  1863. {
  1864. .name = "info",
  1865. .handler = handle_etm_info_command,
  1866. .mode = COMMAND_EXEC,
  1867. .help = "display info about the current target's ETM",
  1868. },
  1869. {
  1870. .name = "status",
  1871. .handler = handle_etm_status_command,
  1872. .mode = COMMAND_EXEC,
  1873. .help = "display current target's ETM status",
  1874. },
  1875. {
  1876. .name = "start",
  1877. .handler = handle_etm_start_command,
  1878. .mode = COMMAND_EXEC,
  1879. .help = "start ETM trace collection",
  1880. },
  1881. {
  1882. .name = "stop",
  1883. .handler = handle_etm_stop_command,
  1884. .mode = COMMAND_EXEC,
  1885. .help = "stop ETM trace collection",
  1886. },
  1887. {
  1888. .name = "trigger_debug",
  1889. .handler = handle_etm_trigger_debug_command,
  1890. .mode = COMMAND_EXEC,
  1891. .help = "enable/disable debug entry on trigger",
  1892. .usage = "['enable'|'disable']",
  1893. },
  1894. {
  1895. .name = "analyze",
  1896. .handler = handle_etm_analyze_command,
  1897. .mode = COMMAND_EXEC,
  1898. .help = "analyze collected ETM trace",
  1899. },
  1900. {
  1901. .name = "image",
  1902. .handler = handle_etm_image_command,
  1903. .mode = COMMAND_EXEC,
  1904. .help = "load image from file with optional offset",
  1905. .usage = "filename [offset]",
  1906. },
  1907. {
  1908. .name = "dump",
  1909. .handler = handle_etm_dump_command,
  1910. .mode = COMMAND_EXEC,
  1911. .help = "dump captured trace data to file",
  1912. .usage = "filename",
  1913. },
  1914. {
  1915. .name = "load",
  1916. .handler = handle_etm_load_command,
  1917. .mode = COMMAND_EXEC,
  1918. .help = "load trace data for analysis <file>",
  1919. },
  1920. COMMAND_REGISTRATION_DONE
  1921. };
  1922. static int etm_register_user_commands(struct command_context *cmd_ctx)
  1923. {
  1924. struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
  1925. return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
  1926. }