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  1. /***************************************************************************
  2. * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. *
  3. * Written by Nicolas Pitre <nico@marvell.com> *
  4. * *
  5. * Copyright (C) 2008 by Hongtao Zheng *
  6. * hontor@126.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. /*
  24. * Marvell Feroceon/Dragonite support.
  25. *
  26. * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others,
  27. * mimics the ARM926 ICE interface with the following differences:
  28. *
  29. * - the MOE (method of entry) reporting is not implemented
  30. *
  31. * - breakpoint/watchpoint comparator #1 is seemingly not implemented
  32. *
  33. * - due to a different pipeline implementation, some injected debug
  34. * instruction sequences have to be somewhat different
  35. *
  36. * Other issues:
  37. *
  38. * - asserting DBGRQ doesn't work if target is looping on the undef vector
  39. *
  40. * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
  41. * not at the top, and rather meaningless due to existing discrepencies
  42. *
  43. * - the DCC channel is half duplex (only one FIFO for both directions) with
  44. * seemingly no proper flow control.
  45. *
  46. * The Dragonite core is the non-mmu version based on the ARM966 model, and
  47. * it shares the above issues as well.
  48. */
  49. #ifdef HAVE_CONFIG_H
  50. #include "config.h"
  51. #endif
  52. #include "arm926ejs.h"
  53. #include "arm966e.h"
  54. #include "target_type.h"
  55. #include "register.h"
  56. #include "arm_opcodes.h"
  57. int feroceon_assert_reset(struct target *target)
  58. {
  59. struct arm *armv4_5 = target->arch_info;
  60. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  61. int ud = arm7_9->use_dbgrq;
  62. arm7_9->use_dbgrq = 0;
  63. if (target->reset_halt)
  64. arm7_9_halt(target);
  65. arm7_9->use_dbgrq = ud;
  66. return arm7_9_assert_reset(target);
  67. }
  68. int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
  69. {
  70. struct scan_field fields[3];
  71. uint8_t out_buf[4];
  72. uint8_t instr_buf[4];
  73. uint8_t sysspeed_buf = 0x0;
  74. /* prepare buffer */
  75. buf_set_u32(out_buf, 0, 32, 0);
  76. buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
  77. jtag_set_end_state(TAP_DRPAUSE);
  78. arm_jtag_scann(jtag_info, 0x1);
  79. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  80. fields[0].tap = jtag_info->tap;
  81. fields[0].num_bits = 32;
  82. fields[0].out_value = out_buf;
  83. fields[0].in_value = NULL;
  84. fields[1].tap = jtag_info->tap;
  85. fields[1].num_bits = 3;
  86. fields[1].out_value = &sysspeed_buf;
  87. fields[1].in_value = NULL;
  88. fields[2].tap = jtag_info->tap;
  89. fields[2].num_bits = 32;
  90. fields[2].out_value = instr_buf;
  91. fields[2].in_value = NULL;
  92. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  93. /* no jtag_add_runtest(0, jtag_get_end_state()) here */
  94. return ERROR_OK;
  95. }
  96. void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
  97. {
  98. struct arm *armv4_5 = target->arch_info;
  99. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  100. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  101. /*
  102. * save r0 before using it and put system in ARM state
  103. * to allow common handling of ARM and THUMB debugging
  104. */
  105. feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
  106. feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
  107. feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
  108. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
  109. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  110. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  111. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
  112. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  113. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  114. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
  115. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
  116. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  117. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  118. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
  119. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  120. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  121. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(15), 0, NULL, 0);
  122. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  123. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  124. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  125. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  126. jtag_execute_queue();
  127. /*
  128. * fix program counter:
  129. * MOV R0, PC was the 7th instruction (+12)
  130. * reading PC in Thumb state gives address of instruction + 4
  131. */
  132. *pc -= (12 + 4);
  133. }
  134. void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16])
  135. {
  136. int i;
  137. struct arm *armv4_5 = target->arch_info;
  138. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  139. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  140. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  141. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  142. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  143. for (i = 0; i <= 15; i++)
  144. if (mask & (1 << i))
  145. arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
  146. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  147. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  148. }
  149. void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size)
  150. {
  151. int i;
  152. struct arm *armv4_5 = target->arch_info;
  153. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  154. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  155. int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
  156. uint32_t *buf_u32 = buffer;
  157. uint16_t *buf_u16 = buffer;
  158. uint8_t *buf_u8 = buffer;
  159. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  160. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  161. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  162. for (i = 0; i <= 15; i++)
  163. {
  164. if (mask & (1 << i)) {
  165. switch (size)
  166. {
  167. case 4:
  168. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
  169. break;
  170. case 2:
  171. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
  172. break;
  173. case 1:
  174. arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
  175. break;
  176. }
  177. }
  178. }
  179. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  180. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  181. }
  182. void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
  183. {
  184. struct arm *armv4_5 = target->arch_info;
  185. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  186. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  187. arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
  188. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  189. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  190. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  191. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  192. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  193. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  194. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
  195. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  196. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  197. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
  198. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  199. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  200. }
  201. void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
  202. {
  203. struct arm *armv4_5 = target->arch_info;
  204. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  205. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  206. LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
  207. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
  208. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  209. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  210. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  211. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  212. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  213. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  214. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
  215. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  216. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  217. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  218. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  219. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  220. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  221. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
  222. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  223. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  224. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  225. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  226. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  227. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  228. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
  229. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  230. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  231. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  232. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  233. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  234. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  235. }
  236. void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
  237. {
  238. struct arm *armv4_5 = target->arch_info;
  239. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  240. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  241. LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
  242. arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
  243. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  244. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  245. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  246. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  247. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  248. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  249. }
  250. void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
  251. {
  252. int i;
  253. struct arm *armv4_5 = target->arch_info;
  254. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  255. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  256. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
  257. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  258. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  259. for (i = 0; i <= 15; i++)
  260. if (mask & (1 << i))
  261. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
  262. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  263. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  264. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  265. }
  266. void feroceon_branch_resume(struct target *target)
  267. {
  268. struct arm *armv4_5 = target->arch_info;
  269. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  270. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  271. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  272. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  273. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  274. arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffff9, 0), 0, NULL, 0);
  275. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  276. arm7_9->need_bypass_before_restart = 1;
  277. }
  278. void feroceon_branch_resume_thumb(struct target *target)
  279. {
  280. LOG_DEBUG("-");
  281. struct arm *armv4_5 = target->arch_info;
  282. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  283. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  284. uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
  285. uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  286. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  287. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  288. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  289. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  290. arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); // add r0,pc,#1
  291. arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
  292. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  293. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  294. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0);
  295. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  296. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  297. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0);
  298. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  299. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
  300. pc = (pc & 2) >> 1;
  301. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7e9 + pc), 0, NULL, 0);
  302. arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 1);
  303. arm7_9->need_bypass_before_restart = 1;
  304. }
  305. int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
  306. {
  307. struct arm *armv4_5 = target->arch_info;
  308. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  309. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  310. int err;
  311. arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
  312. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  313. err = arm7_9_execute_sys_speed(target);
  314. if (err != ERROR_OK)
  315. return err;
  316. arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
  317. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  318. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  319. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, value, 0);
  320. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  321. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  322. return jtag_execute_queue();
  323. }
  324. int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
  325. {
  326. struct arm *armv4_5 = target->arch_info;
  327. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  328. struct arm_jtag *jtag_info = &arm7_9->jtag_info;
  329. arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
  330. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  331. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  332. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, value, NULL, 0);
  333. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  334. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  335. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
  336. arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
  337. arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
  338. return arm7_9_execute_sys_speed(target);
  339. }
  340. void feroceon_set_dbgrq(struct target *target)
  341. {
  342. struct arm *armv4_5 = target->arch_info;
  343. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  344. struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  345. buf_set_u32(dbg_ctrl->value, 0, 8, 2);
  346. embeddedice_store_reg(dbg_ctrl);
  347. }
  348. void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
  349. {
  350. struct arm *armv4_5 = target->arch_info;
  351. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  352. /* set a breakpoint there */
  353. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
  354. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0);
  355. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  356. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
  357. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
  358. }
  359. void feroceon_disable_single_step(struct target *target)
  360. {
  361. struct arm *armv4_5 = target->arch_info;
  362. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  363. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
  364. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
  365. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
  366. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
  367. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
  368. }
  369. int feroceon_examine_debug_reason(struct target *target)
  370. {
  371. /* the MOE is not implemented */
  372. if (target->debug_reason != DBG_REASON_SINGLESTEP)
  373. {
  374. target->debug_reason = DBG_REASON_DBGRQ;
  375. }
  376. return ERROR_OK;
  377. }
  378. int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
  379. {
  380. int retval;
  381. struct arm *armv4_5 = target->arch_info;
  382. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  383. enum arm_state core_state = armv4_5->core_state;
  384. uint32_t x, flip, shift, save[7];
  385. uint32_t i;
  386. /*
  387. * We can't use the dcc flow control bits, so let's transfer data
  388. * with 31 bits and flip the MSB each time a new data word is sent.
  389. */
  390. static uint32_t dcc_code[] =
  391. {
  392. 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
  393. 0xe3a0301e, /* 1: mov r3, #30 */
  394. 0xe3a04002, /* mov r4, #2 */
  395. 0xee111e10, /* 2: mrc p14, 0, r1, c1, c0, 0 */
  396. 0xe1310005, /* teq r1, r5 */
  397. 0x0afffffc, /* beq 1b */
  398. 0xe1a05001, /* mov r5, r1 */
  399. 0xe1a01081, /* mov r1, r1, lsl #1 */
  400. 0xee112e10, /* 3: mrc p14, 0, r2, c1, c0, 0 */
  401. 0xe1320005, /* teq r2, r5 */
  402. 0x0afffffc, /* beq 3b */
  403. 0xe1a05002, /* mov r5, r2 */
  404. 0xe3c22102, /* bic r2, r2, #0x80000000 */
  405. 0xe1811332, /* orr r1, r1, r2, lsr r3 */
  406. 0xe2533001, /* subs r3, r3, #1 */
  407. 0xe4801004, /* str r1, [r0], #4 */
  408. 0xe1a01412, /* mov r1, r2, lsl r4 */
  409. 0xe2844001, /* add r4, r4, #1 */
  410. 0x4affffed, /* bmi 1b */
  411. 0xeafffff3, /* b 3b */
  412. };
  413. uint32_t dcc_size = sizeof(dcc_code);
  414. if (!arm7_9->dcc_downloads)
  415. return target_write_memory(target, address, 4, count, buffer);
  416. /* regrab previously allocated working_area, or allocate a new one */
  417. if (!arm7_9->dcc_working_area)
  418. {
  419. uint8_t dcc_code_buf[dcc_size];
  420. /* make sure we have a working area */
  421. if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
  422. {
  423. LOG_INFO("no working area available, falling back to memory writes");
  424. return target_write_memory(target, address, 4, count, buffer);
  425. }
  426. /* copy target instructions to target endianness */
  427. for (i = 0; i < dcc_size/4; i++)
  428. target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
  429. /* write DCC code to working area */
  430. if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK)
  431. {
  432. return retval;
  433. }
  434. }
  435. /* backup clobbered processor state */
  436. for (i = 0; i <= 5; i++)
  437. save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
  438. save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  439. /* set up target address in r0 */
  440. buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
  441. armv4_5->core_cache->reg_list[0].valid = 1;
  442. armv4_5->core_cache->reg_list[0].dirty = 1;
  443. armv4_5->core_state = ARM_STATE_ARM;
  444. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
  445. arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
  446. /* send data over */
  447. x = 0;
  448. flip = 0;
  449. shift = 1;
  450. for (i = 0; i < count; i++)
  451. {
  452. uint32_t y = target_buffer_get_u32(target, buffer);
  453. uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
  454. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
  455. x = y << (32 - shift);
  456. if (++shift >= 32 || i + 1 >= count)
  457. {
  458. z = (x >> 1) | (flip ^= 0x80000000);
  459. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
  460. x = 0;
  461. shift = 1;
  462. }
  463. buffer += 4;
  464. }
  465. retval = target_halt(target);
  466. if (retval == ERROR_OK)
  467. retval = target_wait_state(target, TARGET_HALTED, 500);
  468. if (retval == ERROR_OK) {
  469. uint32_t endaddress =
  470. buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
  471. if (endaddress != address + count*4) {
  472. LOG_ERROR("DCC write failed,"
  473. " expected end address 0x%08" PRIx32
  474. " got 0x%0" PRIx32 "",
  475. address + count*4, endaddress);
  476. retval = ERROR_FAIL;
  477. }
  478. }
  479. /* restore target state */
  480. for (i = 0; i <= 5; i++)
  481. {
  482. buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, save[i]);
  483. armv4_5->core_cache->reg_list[i].valid = 1;
  484. armv4_5->core_cache->reg_list[i].dirty = 1;
  485. }
  486. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
  487. armv4_5->core_cache->reg_list[15].valid = 1;
  488. armv4_5->core_cache->reg_list[15].dirty = 1;
  489. armv4_5->core_state = core_state;
  490. return retval;
  491. }
  492. int feroceon_init_target(struct command_context *cmd_ctx, struct target *target)
  493. {
  494. arm9tdmi_init_target(cmd_ctx, target);
  495. return ERROR_OK;
  496. }
  497. void feroceon_common_setup(struct target *target)
  498. {
  499. struct arm *armv4_5 = target->arch_info;
  500. struct arm7_9_common *arm7_9 = armv4_5->arch_info;
  501. /* override some insn sequence functions */
  502. arm7_9->change_to_arm = feroceon_change_to_arm;
  503. arm7_9->read_core_regs = feroceon_read_core_regs;
  504. arm7_9->read_core_regs_target_buffer = feroceon_read_core_regs_target_buffer;
  505. arm7_9->read_xpsr = feroceon_read_xpsr;
  506. arm7_9->write_xpsr = feroceon_write_xpsr;
  507. arm7_9->write_xpsr_im8 = feroceon_write_xpsr_im8;
  508. arm7_9->write_core_regs = feroceon_write_core_regs;
  509. arm7_9->branch_resume = feroceon_branch_resume;
  510. arm7_9->branch_resume_thumb = feroceon_branch_resume_thumb;
  511. /* must be implemented with only one comparator */
  512. arm7_9->enable_single_step = feroceon_enable_single_step;
  513. arm7_9->disable_single_step = feroceon_disable_single_step;
  514. /* MOE is not implemented */
  515. arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
  516. /* Note: asserting DBGRQ might not win over the undef exception.
  517. If that happens then just use "arm7_9 dbgrq disable". */
  518. arm7_9->use_dbgrq = 1;
  519. arm7_9->set_special_dbgrq = feroceon_set_dbgrq;
  520. /* only one working comparator */
  521. arm7_9->wp_available_max = 1;
  522. arm7_9->wp1_used_default = -1;
  523. }
  524. int feroceon_target_create(struct target *target, Jim_Interp *interp)
  525. {
  526. struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
  527. arm926ejs_init_arch_info(target, arm926ejs, target->tap);
  528. feroceon_common_setup(target);
  529. /* the standard ARM926 methods don't always work (don't ask...) */
  530. arm926ejs->read_cp15 = feroceon_read_cp15;
  531. arm926ejs->write_cp15 = feroceon_write_cp15;
  532. return ERROR_OK;
  533. }
  534. int dragonite_target_create(struct target *target, Jim_Interp *interp)
  535. {
  536. struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
  537. arm966e_init_arch_info(target, arm966e, target->tap);
  538. feroceon_common_setup(target);
  539. return ERROR_OK;
  540. }
  541. int feroceon_examine(struct target *target)
  542. {
  543. struct arm *armv4_5;
  544. struct arm7_9_common *arm7_9;
  545. int retval;
  546. retval = arm7_9_examine(target);
  547. if (retval != ERROR_OK)
  548. return retval;
  549. armv4_5 = target->arch_info;
  550. arm7_9 = armv4_5->arch_info;
  551. /* the COMMS_CTRL bits are all contiguous */
  552. if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
  553. LOG_ERROR("unexpected Feroceon EICE version signature");
  554. arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
  555. arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
  556. arm7_9->has_monitor_mode = 1;
  557. /* vector catch reg is not initialized on reset */
  558. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
  559. /* clear monitor mode, enable comparators */
  560. embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
  561. jtag_execute_queue();
  562. buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
  563. buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
  564. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
  565. return ERROR_OK;
  566. }
  567. struct target_type feroceon_target =
  568. {
  569. .name = "feroceon",
  570. .poll = arm7_9_poll,
  571. .arch_state = arm926ejs_arch_state,
  572. .target_request_data = arm7_9_target_request_data,
  573. .halt = arm7_9_halt,
  574. .resume = arm7_9_resume,
  575. .step = arm7_9_step,
  576. .assert_reset = feroceon_assert_reset,
  577. .deassert_reset = arm7_9_deassert_reset,
  578. .soft_reset_halt = arm926ejs_soft_reset_halt,
  579. .get_gdb_reg_list = arm_get_gdb_reg_list,
  580. .read_memory = arm7_9_read_memory,
  581. .write_memory = arm926ejs_write_memory,
  582. .bulk_write_memory = feroceon_bulk_write_memory,
  583. .checksum_memory = arm_checksum_memory,
  584. .blank_check_memory = arm_blank_check_memory,
  585. .run_algorithm = armv4_5_run_algorithm,
  586. .add_breakpoint = arm7_9_add_breakpoint,
  587. .remove_breakpoint = arm7_9_remove_breakpoint,
  588. .add_watchpoint = arm7_9_add_watchpoint,
  589. .remove_watchpoint = arm7_9_remove_watchpoint,
  590. .commands = arm926ejs_command_handlers,
  591. .target_create = feroceon_target_create,
  592. .init_target = feroceon_init_target,
  593. .examine = feroceon_examine,
  594. };
  595. struct target_type dragonite_target =
  596. {
  597. .name = "dragonite",
  598. .poll = arm7_9_poll,
  599. .arch_state = arm_arch_state,
  600. .target_request_data = arm7_9_target_request_data,
  601. .halt = arm7_9_halt,
  602. .resume = arm7_9_resume,
  603. .step = arm7_9_step,
  604. .assert_reset = feroceon_assert_reset,
  605. .deassert_reset = arm7_9_deassert_reset,
  606. .soft_reset_halt = arm7_9_soft_reset_halt,
  607. .get_gdb_reg_list = arm_get_gdb_reg_list,
  608. .read_memory = arm7_9_read_memory,
  609. .write_memory = arm7_9_write_memory,
  610. .bulk_write_memory = feroceon_bulk_write_memory,
  611. .checksum_memory = arm_checksum_memory,
  612. .blank_check_memory = arm_blank_check_memory,
  613. .run_algorithm = armv4_5_run_algorithm,
  614. .add_breakpoint = arm7_9_add_breakpoint,
  615. .remove_breakpoint = arm7_9_remove_breakpoint,
  616. .add_watchpoint = arm7_9_add_watchpoint,
  617. .remove_watchpoint = arm7_9_remove_watchpoint,
  618. .commands = arm966e_command_handlers,
  619. .target_create = dragonite_target_create,
  620. .init_target = feroceon_init_target,
  621. .examine = feroceon_examine,
  622. };