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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2007,2008 √ėyvind Harboe *
  8. * oyvind.harboe@zylin.com *
  9. * *
  10. * This program is free software; you can redistribute it and/or modify *
  11. * it under the terms of the GNU General Public License as published by *
  12. * the Free Software Foundation; either version 2 of the License, or *
  13. * (at your option) any later version. *
  14. * *
  15. * This program is distributed in the hope that it will be useful, *
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  18. * GNU General Public License for more details. *
  19. * *
  20. * You should have received a copy of the GNU General Public License *
  21. * along with this program; if not, write to the *
  22. * Free Software Foundation, Inc., *
  23. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  24. ***************************************************************************/
  25. #ifdef HAVE_CONFIG_H
  26. #include "config.h"
  27. #endif
  28. #include "mips32.h"
  29. #include "register.h"
  30. char* mips32_core_reg_list[] =
  31. {
  32. "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
  33. "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
  34. "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
  35. "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
  36. "status", "lo", "hi", "badvaddr", "cause", "pc"
  37. };
  38. const char *mips_isa_strings[] =
  39. {
  40. "MIPS32", "MIPS16e"
  41. };
  42. struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
  43. {
  44. {0, NULL, NULL},
  45. {1, NULL, NULL},
  46. {2, NULL, NULL},
  47. {3, NULL, NULL},
  48. {4, NULL, NULL},
  49. {5, NULL, NULL},
  50. {6, NULL, NULL},
  51. {7, NULL, NULL},
  52. {8, NULL, NULL},
  53. {9, NULL, NULL},
  54. {10, NULL, NULL},
  55. {11, NULL, NULL},
  56. {12, NULL, NULL},
  57. {13, NULL, NULL},
  58. {14, NULL, NULL},
  59. {15, NULL, NULL},
  60. {16, NULL, NULL},
  61. {17, NULL, NULL},
  62. {18, NULL, NULL},
  63. {19, NULL, NULL},
  64. {20, NULL, NULL},
  65. {21, NULL, NULL},
  66. {22, NULL, NULL},
  67. {23, NULL, NULL},
  68. {24, NULL, NULL},
  69. {25, NULL, NULL},
  70. {26, NULL, NULL},
  71. {27, NULL, NULL},
  72. {28, NULL, NULL},
  73. {29, NULL, NULL},
  74. {30, NULL, NULL},
  75. {31, NULL, NULL},
  76. {32, NULL, NULL},
  77. {33, NULL, NULL},
  78. {34, NULL, NULL},
  79. {35, NULL, NULL},
  80. {36, NULL, NULL},
  81. {37, NULL, NULL},
  82. };
  83. /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
  84. * we also add 18 unknown registers to handle gdb requests */
  85. #define MIPS32NUMFPREGS 34 + 18
  86. uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
  87. struct reg mips32_gdb_dummy_fp_reg =
  88. {
  89. .name = "GDB dummy floating-point register",
  90. .value = mips32_gdb_dummy_fp_value,
  91. .dirty = 0,
  92. .valid = 1,
  93. .size = 32,
  94. .arch_info = NULL,
  95. };
  96. int mips32_get_core_reg(struct reg *reg)
  97. {
  98. int retval;
  99. struct mips32_core_reg *mips32_reg = reg->arch_info;
  100. struct target *target = mips32_reg->target;
  101. struct mips32_common *mips32_target = target_to_mips32(target);
  102. if (target->state != TARGET_HALTED)
  103. {
  104. return ERROR_TARGET_NOT_HALTED;
  105. }
  106. retval = mips32_target->read_core_reg(target, mips32_reg->num);
  107. return retval;
  108. }
  109. int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
  110. {
  111. struct mips32_core_reg *mips32_reg = reg->arch_info;
  112. struct target *target = mips32_reg->target;
  113. uint32_t value = buf_get_u32(buf, 0, 32);
  114. if (target->state != TARGET_HALTED)
  115. {
  116. return ERROR_TARGET_NOT_HALTED;
  117. }
  118. buf_set_u32(reg->value, 0, 32, value);
  119. reg->dirty = 1;
  120. reg->valid = 1;
  121. return ERROR_OK;
  122. }
  123. int mips32_read_core_reg(struct target *target, int num)
  124. {
  125. uint32_t reg_value;
  126. struct mips32_core_reg *mips_core_reg;
  127. /* get pointers to arch-specific information */
  128. struct mips32_common *mips32 = target_to_mips32(target);
  129. if ((num < 0) || (num >= MIPS32NUMCOREREGS))
  130. return ERROR_INVALID_ARGUMENTS;
  131. mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
  132. reg_value = mips32->core_regs[num];
  133. buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
  134. mips32->core_cache->reg_list[num].valid = 1;
  135. mips32->core_cache->reg_list[num].dirty = 0;
  136. return ERROR_OK;
  137. }
  138. int mips32_write_core_reg(struct target *target, int num)
  139. {
  140. uint32_t reg_value;
  141. struct mips32_core_reg *mips_core_reg;
  142. /* get pointers to arch-specific information */
  143. struct mips32_common *mips32 = target_to_mips32(target);
  144. if ((num < 0) || (num >= MIPS32NUMCOREREGS))
  145. return ERROR_INVALID_ARGUMENTS;
  146. reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
  147. mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
  148. mips32->core_regs[num] = reg_value;
  149. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
  150. mips32->core_cache->reg_list[num].valid = 1;
  151. mips32->core_cache->reg_list[num].dirty = 0;
  152. return ERROR_OK;
  153. }
  154. int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
  155. {
  156. /* get pointers to arch-specific information */
  157. struct mips32_common *mips32 = target_to_mips32(target);
  158. int i;
  159. /* include floating point registers */
  160. *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
  161. *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
  162. for (i = 0; i < MIPS32NUMCOREREGS; i++)
  163. {
  164. (*reg_list)[i] = &mips32->core_cache->reg_list[i];
  165. }
  166. /* add dummy floating points regs */
  167. for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
  168. {
  169. (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
  170. }
  171. return ERROR_OK;
  172. }
  173. int mips32_save_context(struct target *target)
  174. {
  175. int i;
  176. /* get pointers to arch-specific information */
  177. struct mips32_common *mips32 = target_to_mips32(target);
  178. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  179. /* read core registers */
  180. mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
  181. for (i = 0; i < MIPS32NUMCOREREGS; i++)
  182. {
  183. if (!mips32->core_cache->reg_list[i].valid)
  184. {
  185. mips32->read_core_reg(target, i);
  186. }
  187. }
  188. return ERROR_OK;
  189. }
  190. int mips32_restore_context(struct target *target)
  191. {
  192. int i;
  193. /* get pointers to arch-specific information */
  194. struct mips32_common *mips32 = target_to_mips32(target);
  195. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  196. for (i = 0; i < MIPS32NUMCOREREGS; i++)
  197. {
  198. if (mips32->core_cache->reg_list[i].dirty)
  199. {
  200. mips32->write_core_reg(target, i);
  201. }
  202. }
  203. /* write core regs */
  204. mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
  205. return ERROR_OK;
  206. }
  207. int mips32_arch_state(struct target *target)
  208. {
  209. struct mips32_common *mips32 = target_to_mips32(target);
  210. LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
  211. mips_isa_strings[mips32->isa_mode],
  212. debug_reason_name(target),
  213. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
  214. return ERROR_OK;
  215. }
  216. static const struct reg_arch_type mips32_reg_type = {
  217. .get = mips32_get_core_reg,
  218. .set = mips32_set_core_reg,
  219. };
  220. struct reg_cache *mips32_build_reg_cache(struct target *target)
  221. {
  222. /* get pointers to arch-specific information */
  223. struct mips32_common *mips32 = target_to_mips32(target);
  224. int num_regs = MIPS32NUMCOREREGS;
  225. struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
  226. struct reg_cache *cache = malloc(sizeof(struct reg_cache));
  227. struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
  228. struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
  229. int i;
  230. register_init_dummy(&mips32_gdb_dummy_fp_reg);
  231. /* Build the process context cache */
  232. cache->name = "mips32 registers";
  233. cache->next = NULL;
  234. cache->reg_list = reg_list;
  235. cache->num_regs = num_regs;
  236. (*cache_p) = cache;
  237. mips32->core_cache = cache;
  238. for (i = 0; i < num_regs; i++)
  239. {
  240. arch_info[i] = mips32_core_reg_list_arch_info[i];
  241. arch_info[i].target = target;
  242. arch_info[i].mips32_common = mips32;
  243. reg_list[i].name = mips32_core_reg_list[i];
  244. reg_list[i].size = 32;
  245. reg_list[i].value = calloc(1, 4);
  246. reg_list[i].dirty = 0;
  247. reg_list[i].valid = 0;
  248. reg_list[i].type = &mips32_reg_type;
  249. reg_list[i].arch_info = &arch_info[i];
  250. }
  251. return cache;
  252. }
  253. int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
  254. {
  255. target->arch_info = mips32;
  256. mips32->common_magic = MIPS32_COMMON_MAGIC;
  257. /* has breakpoint/watchpint unit been scanned */
  258. mips32->bp_scanned = 0;
  259. mips32->data_break_list = NULL;
  260. mips32->ejtag_info.tap = tap;
  261. mips32->read_core_reg = mips32_read_core_reg;
  262. mips32->write_core_reg = mips32_write_core_reg;
  263. return ERROR_OK;
  264. }
  265. int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
  266. {
  267. /*TODO*/
  268. return ERROR_OK;
  269. }
  270. int mips32_examine(struct target *target)
  271. {
  272. struct mips32_common *mips32 = target_to_mips32(target);
  273. if (!target_was_examined(target))
  274. {
  275. target_set_examined(target);
  276. /* we will configure later */
  277. mips32->bp_scanned = 0;
  278. mips32->num_inst_bpoints = 0;
  279. mips32->num_data_bpoints = 0;
  280. mips32->num_inst_bpoints_avail = 0;
  281. mips32->num_data_bpoints_avail = 0;
  282. }
  283. return ERROR_OK;
  284. }
  285. int mips32_configure_break_unit(struct target *target)
  286. {
  287. /* get pointers to arch-specific information */
  288. struct mips32_common *mips32 = target_to_mips32(target);
  289. int retval;
  290. uint32_t dcr, bpinfo;
  291. int i;
  292. if (mips32->bp_scanned)
  293. return ERROR_OK;
  294. /* get info about breakpoint support */
  295. if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
  296. return retval;
  297. if (dcr & EJTAG_DCR_IB)
  298. {
  299. /* get number of inst breakpoints */
  300. if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
  301. return retval;
  302. mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
  303. mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
  304. mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
  305. for (i = 0; i < mips32->num_inst_bpoints; i++)
  306. {
  307. mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
  308. }
  309. /* clear IBIS reg */
  310. if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
  311. return retval;
  312. }
  313. if (dcr & EJTAG_DCR_DB)
  314. {
  315. /* get number of data breakpoints */
  316. if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
  317. return retval;
  318. mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
  319. mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
  320. mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
  321. for (i = 0; i < mips32->num_data_bpoints; i++)
  322. {
  323. mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
  324. }
  325. /* clear DBIS reg */
  326. if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
  327. return retval;
  328. }
  329. LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
  330. mips32->bp_scanned = 1;
  331. return ERROR_OK;
  332. }
  333. int mips32_enable_interrupts(struct target *target, int enable)
  334. {
  335. int retval;
  336. int update = 0;
  337. uint32_t dcr;
  338. /* read debug control register */
  339. if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
  340. return retval;
  341. if (enable)
  342. {
  343. if (!(dcr & EJTAG_DCR_INTE))
  344. {
  345. /* enable interrupts */
  346. dcr |= EJTAG_DCR_INTE;
  347. update = 1;
  348. }
  349. }
  350. else
  351. {
  352. if (dcr & EJTAG_DCR_INTE)
  353. {
  354. /* disable interrupts */
  355. dcr &= ~EJTAG_DCR_INTE;
  356. update = 1;
  357. }
  358. }
  359. if (update)
  360. {
  361. if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
  362. return retval;
  363. }
  364. return ERROR_OK;
  365. }