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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "breakpoints.h"
  28. #include "mips32.h"
  29. #include "mips_m4k.h"
  30. #include "mips32_dmaacc.h"
  31. #include "target_type.h"
  32. #include "register.h"
  33. /* cli handling */
  34. /* forward declarations */
  35. int mips_m4k_poll(struct target *target);
  36. int mips_m4k_halt(struct target *target);
  37. int mips_m4k_soft_reset_halt(struct target *target);
  38. int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
  39. int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
  40. int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  41. int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  42. int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target);
  43. int mips_m4k_target_create(struct target *target, Jim_Interp *interp);
  44. int mips_m4k_examine(struct target *target);
  45. int mips_m4k_assert_reset(struct target *target);
  46. int mips_m4k_deassert_reset(struct target *target);
  47. int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum);
  48. struct target_type mips_m4k_target =
  49. {
  50. .name = "mips_m4k",
  51. .poll = mips_m4k_poll,
  52. .arch_state = mips32_arch_state,
  53. .target_request_data = NULL,
  54. .halt = mips_m4k_halt,
  55. .resume = mips_m4k_resume,
  56. .step = mips_m4k_step,
  57. .assert_reset = mips_m4k_assert_reset,
  58. .deassert_reset = mips_m4k_deassert_reset,
  59. .soft_reset_halt = mips_m4k_soft_reset_halt,
  60. .get_gdb_reg_list = mips32_get_gdb_reg_list,
  61. .read_memory = mips_m4k_read_memory,
  62. .write_memory = mips_m4k_write_memory,
  63. .bulk_write_memory = mips_m4k_bulk_write_memory,
  64. .checksum_memory = mips_m4k_checksum_memory,
  65. .blank_check_memory = NULL,
  66. .run_algorithm = mips32_run_algorithm,
  67. .add_breakpoint = mips_m4k_add_breakpoint,
  68. .remove_breakpoint = mips_m4k_remove_breakpoint,
  69. .add_watchpoint = mips_m4k_add_watchpoint,
  70. .remove_watchpoint = mips_m4k_remove_watchpoint,
  71. .target_create = mips_m4k_target_create,
  72. .init_target = mips_m4k_init_target,
  73. .examine = mips_m4k_examine,
  74. };
  75. int mips_m4k_examine_debug_reason(struct target *target)
  76. {
  77. uint32_t break_status;
  78. int retval;
  79. if ((target->debug_reason != DBG_REASON_DBGRQ)
  80. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  81. {
  82. /* get info about inst breakpoint support */
  83. if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
  84. return retval;
  85. if (break_status & 0x1f)
  86. {
  87. /* we have halted on a breakpoint */
  88. if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
  89. return retval;
  90. target->debug_reason = DBG_REASON_BREAKPOINT;
  91. }
  92. /* get info about data breakpoint support */
  93. if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
  94. return retval;
  95. if (break_status & 0x1f)
  96. {
  97. /* we have halted on a breakpoint */
  98. if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
  99. return retval;
  100. target->debug_reason = DBG_REASON_WATCHPOINT;
  101. }
  102. }
  103. return ERROR_OK;
  104. }
  105. int mips_m4k_debug_entry(struct target *target)
  106. {
  107. struct mips32_common *mips32 = target_to_mips32(target);
  108. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  109. uint32_t debug_reg;
  110. /* read debug register */
  111. mips_ejtag_read_debug(ejtag_info, &debug_reg);
  112. /* make sure break unit configured */
  113. mips32_configure_break_unit(target);
  114. /* attempt to find halt reason */
  115. mips_m4k_examine_debug_reason(target);
  116. /* clear single step if active */
  117. if (debug_reg & EJTAG_DEBUG_DSS)
  118. {
  119. /* stopped due to single step - clear step bit */
  120. mips_ejtag_config_step(ejtag_info, 0);
  121. }
  122. mips32_save_context(target);
  123. /* default to mips32 isa, it will be changed below if required */
  124. mips32->isa_mode = MIPS32_ISA_MIPS32;
  125. if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
  126. {
  127. if (buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32) & 0x01)
  128. {
  129. /* core is running mips16e isa */
  130. mips32->isa_mode = MIPS32_ISA_MIPS16E;
  131. }
  132. }
  133. LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
  134. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
  135. target_state_name(target));
  136. return ERROR_OK;
  137. }
  138. int mips_m4k_poll(struct target *target)
  139. {
  140. int retval;
  141. struct mips32_common *mips32 = target_to_mips32(target);
  142. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  143. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
  144. /* read ejtag control reg */
  145. jtag_set_end_state(TAP_IDLE);
  146. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  147. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  148. /* clear this bit before handling polling
  149. * as after reset registers will read zero */
  150. if (ejtag_ctrl & EJTAG_CTRL_ROCC)
  151. {
  152. /* we have detected a reset, clear flag
  153. * otherwise ejtag will not work */
  154. jtag_set_end_state(TAP_IDLE);
  155. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
  156. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  157. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  158. LOG_DEBUG("Reset Detected");
  159. }
  160. /* check for processor halted */
  161. if (ejtag_ctrl & EJTAG_CTRL_BRKST)
  162. {
  163. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
  164. {
  165. jtag_set_end_state(TAP_IDLE);
  166. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
  167. target->state = TARGET_HALTED;
  168. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  169. return retval;
  170. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  171. }
  172. else if (target->state == TARGET_DEBUG_RUNNING)
  173. {
  174. target->state = TARGET_HALTED;
  175. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  176. return retval;
  177. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  178. }
  179. }
  180. else
  181. {
  182. target->state = TARGET_RUNNING;
  183. }
  184. // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
  185. return ERROR_OK;
  186. }
  187. int mips_m4k_halt(struct target *target)
  188. {
  189. struct mips32_common *mips32 = target_to_mips32(target);
  190. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  191. LOG_DEBUG("target->state: %s",
  192. target_state_name(target));
  193. if (target->state == TARGET_HALTED)
  194. {
  195. LOG_DEBUG("target was already halted");
  196. return ERROR_OK;
  197. }
  198. if (target->state == TARGET_UNKNOWN)
  199. {
  200. LOG_WARNING("target was in unknown state when halt was requested");
  201. }
  202. if (target->state == TARGET_RESET)
  203. {
  204. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  205. {
  206. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  207. return ERROR_TARGET_FAILURE;
  208. }
  209. else
  210. {
  211. /* we came here in a reset_halt or reset_init sequence
  212. * debug entry was already prepared in mips32_prepare_reset_halt()
  213. */
  214. target->debug_reason = DBG_REASON_DBGRQ;
  215. return ERROR_OK;
  216. }
  217. }
  218. /* break processor */
  219. mips_ejtag_enter_debug(ejtag_info);
  220. target->debug_reason = DBG_REASON_DBGRQ;
  221. return ERROR_OK;
  222. }
  223. int mips_m4k_assert_reset(struct target *target)
  224. {
  225. struct mips32_common *mips32 = target_to_mips32(target);
  226. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  227. LOG_DEBUG("target->state: %s",
  228. target_state_name(target));
  229. enum reset_types jtag_reset_config = jtag_get_reset_config();
  230. if (!(jtag_reset_config & RESET_HAS_SRST))
  231. {
  232. LOG_ERROR("Can't assert SRST");
  233. return ERROR_FAIL;
  234. }
  235. if (target->reset_halt)
  236. {
  237. /* use hardware to catch reset */
  238. jtag_set_end_state(TAP_IDLE);
  239. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
  240. }
  241. else
  242. {
  243. jtag_set_end_state(TAP_IDLE);
  244. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
  245. }
  246. if (strcmp(target->variant, "ejtag_srst") == 0)
  247. {
  248. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
  249. LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
  250. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
  251. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  252. }
  253. else
  254. {
  255. /* here we should issue a srst only, but we may have to assert trst as well */
  256. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  257. {
  258. jtag_add_reset(1, 1);
  259. }
  260. else
  261. {
  262. jtag_add_reset(0, 1);
  263. }
  264. }
  265. target->state = TARGET_RESET;
  266. jtag_add_sleep(50000);
  267. register_cache_invalidate(mips32->core_cache);
  268. if (target->reset_halt)
  269. {
  270. int retval;
  271. if ((retval = target_halt(target)) != ERROR_OK)
  272. return retval;
  273. }
  274. return ERROR_OK;
  275. }
  276. int mips_m4k_deassert_reset(struct target *target)
  277. {
  278. LOG_DEBUG("target->state: %s",
  279. target_state_name(target));
  280. /* deassert reset lines */
  281. jtag_add_reset(0, 0);
  282. return ERROR_OK;
  283. }
  284. int mips_m4k_soft_reset_halt(struct target *target)
  285. {
  286. /* TODO */
  287. return ERROR_OK;
  288. }
  289. int mips_m4k_single_step_core(struct target *target)
  290. {
  291. struct mips32_common *mips32 = target_to_mips32(target);
  292. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  293. /* configure single step mode */
  294. mips_ejtag_config_step(ejtag_info, 1);
  295. /* disable interrupts while stepping */
  296. mips32_enable_interrupts(target, 0);
  297. /* exit debug mode */
  298. mips_ejtag_exit_debug(ejtag_info);
  299. mips_m4k_debug_entry(target);
  300. return ERROR_OK;
  301. }
  302. int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
  303. {
  304. struct mips32_common *mips32 = target_to_mips32(target);
  305. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  306. struct breakpoint *breakpoint = NULL;
  307. uint32_t resume_pc;
  308. if (target->state != TARGET_HALTED)
  309. {
  310. LOG_WARNING("target not halted");
  311. return ERROR_TARGET_NOT_HALTED;
  312. }
  313. if (!debug_execution)
  314. {
  315. target_free_all_working_areas(target);
  316. mips_m4k_enable_breakpoints(target);
  317. mips_m4k_enable_watchpoints(target);
  318. }
  319. /* current = 1: continue on current pc, otherwise continue at <address> */
  320. if (!current)
  321. {
  322. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  323. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  324. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  325. }
  326. resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
  327. mips32_restore_context(target);
  328. /* the front-end may request us not to handle breakpoints */
  329. if (handle_breakpoints)
  330. {
  331. /* Single step past breakpoint at current address */
  332. if ((breakpoint = breakpoint_find(target, resume_pc)))
  333. {
  334. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  335. mips_m4k_unset_breakpoint(target, breakpoint);
  336. mips_m4k_single_step_core(target);
  337. mips_m4k_set_breakpoint(target, breakpoint);
  338. }
  339. }
  340. /* enable interrupts if we are running */
  341. mips32_enable_interrupts(target, !debug_execution);
  342. /* exit debug mode */
  343. mips_ejtag_exit_debug(ejtag_info);
  344. target->debug_reason = DBG_REASON_NOTHALTED;
  345. /* registers are now invalid */
  346. register_cache_invalidate(mips32->core_cache);
  347. if (!debug_execution)
  348. {
  349. target->state = TARGET_RUNNING;
  350. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  351. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  352. }
  353. else
  354. {
  355. target->state = TARGET_DEBUG_RUNNING;
  356. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  357. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  358. }
  359. return ERROR_OK;
  360. }
  361. int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
  362. {
  363. /* get pointers to arch-specific information */
  364. struct mips32_common *mips32 = target_to_mips32(target);
  365. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  366. struct breakpoint *breakpoint = NULL;
  367. if (target->state != TARGET_HALTED)
  368. {
  369. LOG_WARNING("target not halted");
  370. return ERROR_TARGET_NOT_HALTED;
  371. }
  372. /* current = 1: continue on current pc, otherwise continue at <address> */
  373. if (!current)
  374. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  375. /* the front-end may request us not to handle breakpoints */
  376. if (handle_breakpoints)
  377. if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
  378. mips_m4k_unset_breakpoint(target, breakpoint);
  379. /* restore context */
  380. mips32_restore_context(target);
  381. /* configure single step mode */
  382. mips_ejtag_config_step(ejtag_info, 1);
  383. target->debug_reason = DBG_REASON_SINGLESTEP;
  384. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  385. /* disable interrupts while stepping */
  386. mips32_enable_interrupts(target, 0);
  387. /* exit debug mode */
  388. mips_ejtag_exit_debug(ejtag_info);
  389. /* registers are now invalid */
  390. register_cache_invalidate(mips32->core_cache);
  391. if (breakpoint)
  392. mips_m4k_set_breakpoint(target, breakpoint);
  393. LOG_DEBUG("target stepped ");
  394. mips_m4k_debug_entry(target);
  395. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  396. return ERROR_OK;
  397. }
  398. void mips_m4k_enable_breakpoints(struct target *target)
  399. {
  400. struct breakpoint *breakpoint = target->breakpoints;
  401. /* set any pending breakpoints */
  402. while (breakpoint)
  403. {
  404. if (breakpoint->set == 0)
  405. mips_m4k_set_breakpoint(target, breakpoint);
  406. breakpoint = breakpoint->next;
  407. }
  408. }
  409. int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
  410. {
  411. struct mips32_common *mips32 = target_to_mips32(target);
  412. struct mips32_comparator * comparator_list = mips32->inst_break_list;
  413. int retval;
  414. if (breakpoint->set)
  415. {
  416. LOG_WARNING("breakpoint already set");
  417. return ERROR_OK;
  418. }
  419. if (breakpoint->type == BKPT_HARD)
  420. {
  421. int bp_num = 0;
  422. while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
  423. bp_num++;
  424. if (bp_num >= mips32->num_inst_bpoints)
  425. {
  426. LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
  427. breakpoint->unique_id );
  428. return ERROR_FAIL;
  429. }
  430. breakpoint->set = bp_num + 1;
  431. comparator_list[bp_num].used = 1;
  432. comparator_list[bp_num].bp_value = breakpoint->address;
  433. target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
  434. target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
  435. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
  436. LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
  437. breakpoint->unique_id,
  438. bp_num, comparator_list[bp_num].bp_value);
  439. }
  440. else if (breakpoint->type == BKPT_SOFT)
  441. {
  442. LOG_DEBUG("bpid: %d", breakpoint->unique_id );
  443. if (breakpoint->length == 4)
  444. {
  445. uint32_t verify = 0xffffffff;
  446. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
  447. {
  448. return retval;
  449. }
  450. if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
  451. {
  452. return retval;
  453. }
  454. if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
  455. {
  456. return retval;
  457. }
  458. if (verify != MIPS32_SDBBP)
  459. {
  460. LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  461. return ERROR_OK;
  462. }
  463. }
  464. else
  465. {
  466. uint16_t verify = 0xffff;
  467. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
  468. {
  469. return retval;
  470. }
  471. if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
  472. {
  473. return retval;
  474. }
  475. if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
  476. {
  477. return retval;
  478. }
  479. if (verify != MIPS16_SDBBP)
  480. {
  481. LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  482. return ERROR_OK;
  483. }
  484. }
  485. breakpoint->set = 20; /* Any nice value but 0 */
  486. }
  487. return ERROR_OK;
  488. }
  489. int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
  490. {
  491. /* get pointers to arch-specific information */
  492. struct mips32_common *mips32 = target_to_mips32(target);
  493. struct mips32_comparator *comparator_list = mips32->inst_break_list;
  494. int retval;
  495. if (!breakpoint->set)
  496. {
  497. LOG_WARNING("breakpoint not set");
  498. return ERROR_OK;
  499. }
  500. if (breakpoint->type == BKPT_HARD)
  501. {
  502. int bp_num = breakpoint->set - 1;
  503. if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
  504. {
  505. LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
  506. breakpoint->unique_id);
  507. return ERROR_OK;
  508. }
  509. LOG_DEBUG("bpid: %d - releasing hw: %d",
  510. breakpoint->unique_id,
  511. bp_num );
  512. comparator_list[bp_num].used = 0;
  513. comparator_list[bp_num].bp_value = 0;
  514. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
  515. }
  516. else
  517. {
  518. /* restore original instruction (kept in target endianness) */
  519. LOG_DEBUG("bpid: %d", breakpoint->unique_id);
  520. if (breakpoint->length == 4)
  521. {
  522. uint32_t current_instr;
  523. /* check that user program has not modified breakpoint instruction */
  524. if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
  525. {
  526. return retval;
  527. }
  528. if (current_instr == MIPS32_SDBBP)
  529. {
  530. if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  531. {
  532. return retval;
  533. }
  534. }
  535. }
  536. else
  537. {
  538. uint16_t current_instr;
  539. /* check that user program has not modified breakpoint instruction */
  540. if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
  541. {
  542. return retval;
  543. }
  544. if (current_instr == MIPS16_SDBBP)
  545. {
  546. if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  547. {
  548. return retval;
  549. }
  550. }
  551. }
  552. }
  553. breakpoint->set = 0;
  554. return ERROR_OK;
  555. }
  556. int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  557. {
  558. struct mips32_common *mips32 = target_to_mips32(target);
  559. if (breakpoint->type == BKPT_HARD)
  560. {
  561. if (mips32->num_inst_bpoints_avail < 1)
  562. {
  563. LOG_INFO("no hardware breakpoint available");
  564. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  565. }
  566. mips32->num_inst_bpoints_avail--;
  567. }
  568. mips_m4k_set_breakpoint(target, breakpoint);
  569. return ERROR_OK;
  570. }
  571. int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
  572. {
  573. /* get pointers to arch-specific information */
  574. struct mips32_common *mips32 = target_to_mips32(target);
  575. if (target->state != TARGET_HALTED)
  576. {
  577. LOG_WARNING("target not halted");
  578. return ERROR_TARGET_NOT_HALTED;
  579. }
  580. if (breakpoint->set)
  581. {
  582. mips_m4k_unset_breakpoint(target, breakpoint);
  583. }
  584. if (breakpoint->type == BKPT_HARD)
  585. mips32->num_inst_bpoints_avail++;
  586. return ERROR_OK;
  587. }
  588. int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
  589. {
  590. struct mips32_common *mips32 = target_to_mips32(target);
  591. struct mips32_comparator *comparator_list = mips32->data_break_list;
  592. int wp_num = 0;
  593. /*
  594. * watchpoint enabled, ignore all byte lanes in value register
  595. * and exclude both load and store accesses from watchpoint
  596. * condition evaluation
  597. */
  598. int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
  599. (0xff << EJTAG_DBCn_BLM_SHIFT);
  600. if (watchpoint->set)
  601. {
  602. LOG_WARNING("watchpoint already set");
  603. return ERROR_OK;
  604. }
  605. while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
  606. wp_num++;
  607. if (wp_num >= mips32->num_data_bpoints)
  608. {
  609. LOG_ERROR("Can not find free FP Comparator");
  610. return ERROR_FAIL;
  611. }
  612. if (watchpoint->length != 4)
  613. {
  614. LOG_ERROR("Only watchpoints of length 4 are supported");
  615. return ERROR_TARGET_UNALIGNED_ACCESS;
  616. }
  617. if (watchpoint->address % 4)
  618. {
  619. LOG_ERROR("Watchpoints address should be word aligned");
  620. return ERROR_TARGET_UNALIGNED_ACCESS;
  621. }
  622. switch (watchpoint->rw)
  623. {
  624. case WPT_READ:
  625. enable &= ~EJTAG_DBCn_NOLB;
  626. break;
  627. case WPT_WRITE:
  628. enable &= ~EJTAG_DBCn_NOSB;
  629. break;
  630. case WPT_ACCESS:
  631. enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
  632. break;
  633. default:
  634. LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
  635. }
  636. watchpoint->set = wp_num + 1;
  637. comparator_list[wp_num].used = 1;
  638. comparator_list[wp_num].bp_value = watchpoint->address;
  639. target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
  640. target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
  641. target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
  642. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
  643. target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
  644. LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
  645. return ERROR_OK;
  646. }
  647. int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
  648. {
  649. /* get pointers to arch-specific information */
  650. struct mips32_common *mips32 = target_to_mips32(target);
  651. struct mips32_comparator *comparator_list = mips32->data_break_list;
  652. if (!watchpoint->set)
  653. {
  654. LOG_WARNING("watchpoint not set");
  655. return ERROR_OK;
  656. }
  657. int wp_num = watchpoint->set - 1;
  658. if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
  659. {
  660. LOG_DEBUG("Invalid FP Comparator number in watchpoint");
  661. return ERROR_OK;
  662. }
  663. comparator_list[wp_num].used = 0;
  664. comparator_list[wp_num].bp_value = 0;
  665. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
  666. watchpoint->set = 0;
  667. return ERROR_OK;
  668. }
  669. int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  670. {
  671. struct mips32_common *mips32 = target_to_mips32(target);
  672. if (mips32->num_data_bpoints_avail < 1)
  673. {
  674. LOG_INFO("no hardware watchpoints available");
  675. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  676. }
  677. mips32->num_data_bpoints_avail--;
  678. mips_m4k_set_watchpoint(target, watchpoint);
  679. return ERROR_OK;
  680. }
  681. int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
  682. {
  683. /* get pointers to arch-specific information */
  684. struct mips32_common *mips32 = target_to_mips32(target);
  685. if (target->state != TARGET_HALTED)
  686. {
  687. LOG_WARNING("target not halted");
  688. return ERROR_TARGET_NOT_HALTED;
  689. }
  690. if (watchpoint->set)
  691. {
  692. mips_m4k_unset_watchpoint(target, watchpoint);
  693. }
  694. mips32->num_data_bpoints_avail++;
  695. return ERROR_OK;
  696. }
  697. void mips_m4k_enable_watchpoints(struct target *target)
  698. {
  699. struct watchpoint *watchpoint = target->watchpoints;
  700. /* set any pending watchpoints */
  701. while (watchpoint)
  702. {
  703. if (watchpoint->set == 0)
  704. mips_m4k_set_watchpoint(target, watchpoint);
  705. watchpoint = watchpoint->next;
  706. }
  707. }
  708. int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  709. {
  710. struct mips32_common *mips32 = target_to_mips32(target);
  711. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  712. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
  713. if (target->state != TARGET_HALTED)
  714. {
  715. LOG_WARNING("target not halted");
  716. return ERROR_TARGET_NOT_HALTED;
  717. }
  718. /* sanitize arguments */
  719. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  720. return ERROR_INVALID_ARGUMENTS;
  721. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  722. return ERROR_TARGET_UNALIGNED_ACCESS;
  723. /* if noDMA off, use DMAACC mode for memory read */
  724. int retval;
  725. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  726. retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  727. else
  728. retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  729. if (ERROR_OK != retval)
  730. return retval;
  731. return ERROR_OK;
  732. }
  733. int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  734. {
  735. struct mips32_common *mips32 = target_to_mips32(target);
  736. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  737. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
  738. if (target->state != TARGET_HALTED)
  739. {
  740. LOG_WARNING("target not halted");
  741. return ERROR_TARGET_NOT_HALTED;
  742. }
  743. /* sanitize arguments */
  744. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  745. return ERROR_INVALID_ARGUMENTS;
  746. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  747. return ERROR_TARGET_UNALIGNED_ACCESS;
  748. /* if noDMA off, use DMAACC mode for memory write */
  749. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  750. return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  751. else
  752. return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  753. }
  754. int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
  755. {
  756. mips32_build_reg_cache(target);
  757. return ERROR_OK;
  758. }
  759. int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
  760. {
  761. struct mips32_common *mips32 = &mips_m4k->mips32_common;
  762. mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
  763. /* initialize mips4k specific info */
  764. mips32_init_arch_info(target, mips32, tap);
  765. mips32->arch_info = mips_m4k;
  766. return ERROR_OK;
  767. }
  768. int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
  769. {
  770. struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
  771. mips_m4k_init_arch_info(target, mips_m4k, target->tap);
  772. return ERROR_OK;
  773. }
  774. int mips_m4k_examine(struct target *target)
  775. {
  776. int retval;
  777. struct mips32_common *mips32 = target_to_mips32(target);
  778. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  779. uint32_t idcode = 0;
  780. if (!target_was_examined(target))
  781. {
  782. mips_ejtag_get_idcode(ejtag_info, &idcode);
  783. ejtag_info->idcode = idcode;
  784. if (((idcode >> 1) & 0x7FF) == 0x29)
  785. {
  786. /* we are using a pic32mx so select ejtag port
  787. * as it is not selected by default */
  788. mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
  789. LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
  790. }
  791. }
  792. /* init rest of ejtag interface */
  793. if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
  794. return retval;
  795. if ((retval = mips32_examine(target)) != ERROR_OK)
  796. return retval;
  797. return ERROR_OK;
  798. }
  799. int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
  800. {
  801. struct mips32_common *mips32 = target_to_mips32(target);
  802. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  803. struct working_area *source;
  804. int retval;
  805. int write = 1;
  806. LOG_DEBUG("address: 0x%8.8x, count: 0x%8.8x", address, count);
  807. if (target->state != TARGET_HALTED)
  808. {
  809. LOG_WARNING("target not halted");
  810. return ERROR_TARGET_NOT_HALTED;
  811. }
  812. /* check alignment */
  813. if (address & 0x3u)
  814. return ERROR_TARGET_UNALIGNED_ACCESS;
  815. /* Get memory for block write handler */
  816. retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source);
  817. if (retval != ERROR_OK)
  818. {
  819. LOG_WARNING("No working area available, falling back to non-bulk write");
  820. return mips_m4k_write_memory(target, address, 4, count, buffer);
  821. }
  822. /* TAP data register is loaded LSB first (little endian) */
  823. if (target->endianness == TARGET_BIG_ENDIAN)
  824. {
  825. uint32_t i, t32;
  826. for(i = 0; i < (count * 4); i += 4)
  827. {
  828. t32 = be_to_h_u32((uint8_t *) &buffer[i]);
  829. h_u32_to_le(&buffer[i], t32);
  830. }
  831. }
  832. retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address, count, (uint32_t*) buffer);
  833. if (retval != ERROR_OK)
  834. {
  835. /* FASTDATA access failed, try normal memory write */
  836. LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
  837. retval = mips_m4k_write_memory(target, address, 4, count, buffer);
  838. }
  839. if (source)
  840. target_free_working_area(target, source);
  841. return retval;
  842. }
  843. int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)
  844. {
  845. return ERROR_FAIL; /* use bulk read method */
  846. }