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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2007,2008 √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifndef XSCALE_H
  24. #define XSCALE_H
  25. #include "arm.h"
  26. #include "armv4_5_mmu.h"
  27. #include "trace.h"
  28. #define XSCALE_COMMON_MAGIC 0x58534341
  29. /* These four JTAG instructions are architecturally defined.
  30. * Lengths are core-specific; originally 5 bits, later 7.
  31. */
  32. #define XSCALE_DBGRX 0x02
  33. #define XSCALE_DBGTX 0x10
  34. #define XSCALE_LDIC 0x07
  35. #define XSCALE_SELDCSR 0x09
  36. /* Possible CPU types */
  37. #define XSCALE_IXP4XX_PXA2XX 0x0
  38. #define XSCALE_PXA3XX 0x4
  39. enum xscale_debug_reason
  40. {
  41. XSCALE_DBG_REASON_GENERIC,
  42. XSCALE_DBG_REASON_RESET,
  43. XSCALE_DBG_REASON_TB_FULL,
  44. };
  45. enum xscale_trace_entry_type
  46. {
  47. XSCALE_TRACE_MESSAGE = 0x0,
  48. XSCALE_TRACE_ADDRESS = 0x1,
  49. };
  50. struct xscale_trace_entry
  51. {
  52. uint8_t data;
  53. enum xscale_trace_entry_type type;
  54. };
  55. struct xscale_trace_data
  56. {
  57. struct xscale_trace_entry *entries;
  58. int depth;
  59. uint32_t chkpt0;
  60. uint32_t chkpt1;
  61. uint32_t last_instruction;
  62. struct xscale_trace_data *next;
  63. };
  64. struct xscale_trace
  65. {
  66. trace_status_t capture_status; /* current state of capture run */
  67. struct image *image; /* source for target opcodes */
  68. struct xscale_trace_data *data; /* linked list of collected trace data */
  69. int buffer_enabled; /* whether trace buffer is enabled */
  70. int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
  71. int pc_ok;
  72. uint32_t current_pc;
  73. enum arm_state core_state; /* current core state (ARM, Thumb) */
  74. };
  75. struct xscale_common
  76. {
  77. /* armv4/5 common stuff */
  78. struct arm armv4_5_common;
  79. int common_magic;
  80. /* XScale registers (CP15, DBG) */
  81. struct reg_cache *reg_cache;
  82. /* current state of the debug handler */
  83. uint32_t handler_address;
  84. /* target-endian buffers with exception vectors */
  85. uint32_t low_vectors[8];
  86. uint32_t high_vectors[8];
  87. /* static low vectors */
  88. uint8_t static_low_vectors_set; /* bit field with static vectors set by the user */
  89. uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
  90. uint32_t static_low_vectors[8];
  91. uint32_t static_high_vectors[8];
  92. /* DCache cleaning */
  93. uint32_t cache_clean_address;
  94. /* whether hold_rst and ext_dbg_break should be set */
  95. int hold_rst;
  96. int external_debug_break;
  97. /* breakpoint / watchpoint handling */
  98. int dbr_available;
  99. int dbr0_used;
  100. int dbr1_used;
  101. int ibcr_available;
  102. int ibcr0_used;
  103. int ibcr1_used;
  104. uint32_t arm_bkpt;
  105. uint16_t thumb_bkpt;
  106. uint8_t vector_catch;
  107. struct xscale_trace trace;
  108. int arch_debug_reason;
  109. /* MMU/Caches */
  110. struct armv4_5_mmu_common armv4_5_mmu;
  111. uint32_t cp15_control_reg;
  112. int fast_memory_access;
  113. /* CPU variant */
  114. int xscale_variant;
  115. };
  116. static inline struct xscale_common *
  117. target_to_xscale(struct target *target)
  118. {
  119. return container_of(target->arch_info, struct xscale_common,
  120. armv4_5_common);
  121. }
  122. struct xscale_reg
  123. {
  124. int dbg_handler_number;
  125. struct target *target;
  126. };
  127. enum
  128. {
  129. XSCALE_MAINID, /* 0 */
  130. XSCALE_CACHETYPE,
  131. XSCALE_CTRL,
  132. XSCALE_AUXCTRL,
  133. XSCALE_TTB,
  134. XSCALE_DAC,
  135. XSCALE_FSR,
  136. XSCALE_FAR,
  137. XSCALE_PID,
  138. XSCALE_CPACCESS,
  139. XSCALE_IBCR0, /* 10 */
  140. XSCALE_IBCR1,
  141. XSCALE_DBR0,
  142. XSCALE_DBR1,
  143. XSCALE_DBCON,
  144. XSCALE_TBREG,
  145. XSCALE_CHKPT0,
  146. XSCALE_CHKPT1,
  147. XSCALE_DCSR,
  148. XSCALE_TX,
  149. XSCALE_RX, /* 20 */
  150. XSCALE_TXRXCTRL,
  151. };
  152. #define ERROR_XSCALE_NO_TRACE_DATA (-1500)
  153. #endif /* XSCALE_H */