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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009-2010 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developer Resources
  53. * Debug Adapter Hardware:: Debug Adapter Hardware
  54. * About Jim-Tcl:: About Jim-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Debug Adapter Configuration:: Debug Adapter Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * Flash Programming:: Flash Programming
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * Utility Commands:: Utility Commands
  71. * TFTP:: TFTP
  72. * GDB and OpenOCD:: Using GDB and OpenOCD
  73. * Tcl Scripting API:: Tcl Scripting API
  74. * FAQ:: Frequently Asked Questions
  75. * Tcl Crash Course:: Tcl Crash Course
  76. * License:: GNU Free Documentation License
  77. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  78. @comment case issue with ``Index.html'' and ``index.html''
  79. @comment Occurs when creating ``--html --no-split'' output
  80. @comment This fix is based on:
  81. * OpenOCD Concept Index:: Concept Index
  82. * Command and Driver Index:: Command and Driver Index
  83. @end menu
  84. @node About
  85. @unnumbered About
  86. @cindex about
  87. OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
  88. at the University of Applied Sciences Augsburg (@uref{}).
  89. Since that time, the project has grown into an active open-source project,
  90. supported by a diverse community of software and hardware developers from
  91. around the world.
  92. @section What is OpenOCD?
  93. @cindex TAP
  94. @cindex JTAG
  95. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  96. in-system programming and boundary-scan testing for embedded target
  97. devices.
  98. It does so with the assistance of a @dfn{debug adapter}, which is
  99. a small hardware module which helps provide the right kind of
  100. electrical signaling to the target being debugged. These are
  101. required since the debug host (on which OpenOCD runs) won't
  102. usually have native support for such signaling, or the connector
  103. needed to hook up to the target.
  104. Such debug adapters support one or more @dfn{transport} protocols,
  105. each of which involves different electrical signaling (and uses
  106. different messaging protocols on top of that signaling). There
  107. are many types of debug adapter, and little uniformity in what
  108. they are called. (There are also product naming differences.)
  109. These adapters are sometimes packaged as discrete dongles, which
  110. may generically be called @dfn{hardware interface dongles}.
  111. Some development boards also integrate them directly, which may
  112. let the development board connect directly to the debug
  113. host over USB (and sometimes also to power it over USB).
  114. For example, a @dfn{JTAG Adapter} supports JTAG
  115. signaling, and is used to communicate
  116. with JTAG (IEEE 1149.1) compliant TAPs on your target board.
  117. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  118. special instructions and data. TAPs are daisy-chained within and
  119. between chips and boards. JTAG supports debugging and boundary
  120. scan operations.
  121. There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
  122. signaling to communicate with some newer ARM cores, as well as debug
  123. adapters which support both JTAG and SWD transports. SWD supports only
  124. debugging, whereas JTAG also supports boundary scan operations.
  125. For some chips, there are also @dfn{Programming Adapters} supporting
  126. special transports used only to write code to flash memory, without
  127. support for on-chip debugging or boundary scan.
  128. (At this writing, OpenOCD does not support such non-debug adapters.)
  129. @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
  130. USB-based, parallel port-based, and other standalone boxes that run
  131. OpenOCD internally. @xref{Debug Adapter Hardware}.
  132. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  133. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
  134. (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
  135. based cores to be debugged via the GDB protocol.
  136. @b{Flash Programming:} Flash writing is supported for external
  137. CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
  138. internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
  139. STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
  140. controllers (LPC3180, Orion, S3C24xx, more) is included.
  141. @section OpenOCD Web Site
  142. The OpenOCD web site provides the latest public news from the community:
  143. @uref{}
  144. @section Latest User's Guide:
  145. The user's guide you are now reading may not be the latest one
  146. available. A version for more recent code may be available.
  147. Its HTML form is published regularly at:
  148. @uref{}
  149. PDF form is likewise published at:
  150. @uref{}
  151. @section OpenOCD User's Forum
  152. There is an OpenOCD forum (phpBB) hosted by SparkFun,
  153. which might be helpful to you. Note that if you want
  154. anything to come to the attention of developers, you
  155. should post it to the OpenOCD Developer Mailing List
  156. instead of this forum.
  157. @uref{}
  158. @section OpenOCD User's Mailing List
  159. The OpenOCD User Mailing List provides the primary means of
  160. communication between users:
  161. @uref{}
  162. @section OpenOCD IRC
  163. Support can also be found on irc:
  164. @uref{irc://}
  165. @node Developers
  166. @chapter OpenOCD Developer Resources
  167. @cindex developers
  168. If you are interested in improving the state of OpenOCD's debugging and
  169. testing support, new contributions will be welcome. Motivated developers
  170. can produce new target, flash or interface drivers, improve the
  171. documentation, as well as more conventional bug fixes and enhancements.
  172. The resources in this chapter are available for developers wishing to explore
  173. or expand the OpenOCD source code.
  174. @section OpenOCD Git Repository
  175. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  176. a Git repository hosted at SourceForge. The repository URL is:
  177. @uref{git://}
  178. or via http
  179. @uref{}
  180. You may prefer to use a mirror and the HTTP protocol:
  181. @uref{}
  182. With standard Git tools, use @command{git clone} to initialize
  183. a local repository, and @command{git pull} to update it.
  184. There are also gitweb pages letting you browse the repository
  185. with a web browser, or download arbitrary snapshots without
  186. needing a Git client:
  187. @uref{}
  188. The @file{README} file contains the instructions for building the project
  189. from the repository or a snapshot.
  190. Developers that want to contribute patches to the OpenOCD system are
  191. @b{strongly} encouraged to work against mainline.
  192. Patches created against older versions may require additional
  193. work from their submitter in order to be updated for newer releases.
  194. @section Doxygen Developer Manual
  195. During the 0.2.x release cycle, the OpenOCD project began
  196. providing a Doxygen reference manual. This document contains more
  197. technical information about the software internals, development
  198. processes, and similar documentation:
  199. @uref{}
  200. This document is a work-in-progress, but contributions would be welcome
  201. to fill in the gaps. All of the source files are provided in-tree,
  202. listed in the Doxyfile configuration at the top of the source tree.
  203. @section Gerrit Review System
  204. All changes in the OpenOCD Git repository go through the web-based Gerrit
  205. Code Review System:
  206. @uref{}
  207. After a one-time registration and repository setup, anyone can push commits
  208. from their local Git repository directly into Gerrit.
  209. All users and developers are encouraged to review, test, discuss and vote
  210. for changes in Gerrit. The feedback provides the basis for a maintainer to
  211. eventually submit the change to the main Git repository.
  212. The @file{HACKING} file, also available as the Patch Guide in the Doxygen
  213. Developer Manual, contains basic information about how to connect a
  214. repository to Gerrit, prepare and push patches. Patch authors are expected to
  215. maintain their changes while they're in Gerrit, respond to feedback and if
  216. necessary rework and push improved versions of the change.
  217. @section OpenOCD Developer Mailing List
  218. The OpenOCD Developer Mailing List provides the primary means of
  219. communication between developers:
  220. @uref{}
  221. @section OpenOCD Bug Tracker
  222. The OpenOCD Bug Tracker is hosted on SourceForge:
  223. @uref{}
  224. @node Debug Adapter Hardware
  225. @chapter Debug Adapter Hardware
  226. @cindex dongles
  227. @cindex FTDI
  228. @cindex wiggler
  229. @cindex zy1000
  230. @cindex printer port
  231. @cindex USB Adapter
  232. @cindex RTCK
  233. Defined: @b{dongle}: A small device that plugs into a computer and serves as
  234. an adapter .... [snip]
  235. In the OpenOCD case, this generally refers to @b{a small adapter} that
  236. attaches to your computer via USB or the parallel port. One
  237. exception is the Ultimate Solutions ZY1000, packaged as a small box you
  238. attach via an ethernet cable. The ZY1000 has the advantage that it does not
  239. require any drivers to be installed on the developer PC. It also has
  240. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  241. and has a built-in relay to power cycle targets remotely.
  242. @section Choosing a Dongle
  243. There are several things you should keep in mind when choosing a dongle.
  244. @enumerate
  245. @item @b{Transport} Does it support the kind of communication that you need?
  246. OpenOCD focusses mostly on JTAG. Your version may also support
  247. other ways to communicate with target devices.
  248. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  249. Does your dongle support it? You might need a level converter.
  250. @item @b{Pinout} What pinout does your target board use?
  251. Does your dongle support it? You may be able to use jumper
  252. wires, or an "octopus" connector, to convert pinouts.
  253. @item @b{Connection} Does your computer have the USB, parallel, or
  254. Ethernet port needed?
  255. @item @b{RTCK} Do you expect to use it with ARM chips and boards with
  256. RTCK support (also known as ``adaptive clocking'')?
  257. @end enumerate
  258. @section Stand-alone JTAG Probe
  259. The ZY1000 from Ultimate Solutions is technically not a dongle but a
  260. stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
  261. running on the developer's host computer.
  262. Once installed on a network using DHCP or a static IP assignment, users can
  263. access the ZY1000 probe locally or remotely from any host with access to the
  264. IP address assigned to the probe.
  265. The ZY1000 provides an intuitive web interface with direct access to the
  266. OpenOCD debugger.
  267. Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
  268. of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
  269. the target.
  270. The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
  271. to power cycle the target remotely.
  272. For more information, visit:
  273. @b{ZY1000} See: @url{}
  274. @section USB FT2232 Based
  275. There are many USB JTAG dongles on the market, many of them based
  276. on a chip from ``Future Technology Devices International'' (FTDI)
  277. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  278. See: @url{} for more information.
  279. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  280. chips started to become available in JTAG adapters. Around 2012, a new
  281. variant appeared - FT232H - this is a single-channel version of FT2232H.
  282. (Adapters using those high speed FT2232H or FT232H chips may support adaptive
  283. clocking.)
  284. The FT2232 chips are flexible enough to support some other
  285. transport options, such as SWD or the SPI variants used to
  286. program some chips. They have two communications channels,
  287. and one can be used for a UART adapter at the same time the
  288. other one is used to provide a debug adapter.
  289. Also, some development boards integrate an FT2232 chip to serve as
  290. a built-in low-cost debug adapter and USB-to-serial solution.
  291. @itemize @bullet
  292. @item @b{usbjtag}
  293. @* Link @url{}
  294. @item @b{jtagkey}
  295. @* See: @url{}
  296. @item @b{jtagkey2}
  297. @* See: @url{}
  298. @item @b{oocdlink}
  299. @* See: @url{} By Joern Kaipf
  300. @item @b{signalyzer}
  301. @* See: @url{}
  302. @item @b{Stellaris Eval Boards}
  303. @* See: @url{} - The Stellaris eval boards
  304. bundle FT2232-based JTAG and SWD support, which can be used to debug
  305. the Stellaris chips. Using separate JTAG adapters is optional.
  306. These boards can also be used in a "pass through" mode as JTAG adapters
  307. to other target boards, disabling the Stellaris chip.
  308. @item @b{TI/Luminary ICDI}
  309. @* See: @url{} - TI/Luminary In-Circuit Debug
  310. Interface (ICDI) Boards are included in Stellaris LM3S9B9x
  311. Evaluation Kits. Like the non-detachable FT2232 support on the other
  312. Stellaris eval boards, they can be used to debug other target boards.
  313. @item @b{olimex-jtag}
  314. @* See: @url{}
  315. @item @b{Flyswatter/Flyswatter2}
  316. @* See: @url{}
  317. @item @b{turtelizer2}
  318. @* See:
  319. @uref{, Turtelizer 2}, or
  320. @url{}
  321. @item @b{comstick}
  322. @* Link: @url{}
  323. @item @b{stm32stick}
  324. @* Link @url{}
  325. @item @b{axm0432_jtag}
  326. @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
  327. to be available anymore as of April 2012.
  328. @item @b{cortino}
  329. @* Link @url{}
  330. @item @b{dlp-usb1232h}
  331. @* Link @url{}
  332. @item @b{digilent-hs1}
  333. @* Link @url{}
  334. @item @b{opendous}
  335. @* Link @url{} FT2232H-based
  336. (OpenHardware).
  337. @item @b{JTAG-lock-pick Tiny 2}
  338. @* Link @url{} FT232H-based
  339. @item @b{GW16042}
  340. @* Link: @url{}
  341. FT2232H-based
  342. @end itemize
  343. @section USB-JTAG / Altera USB-Blaster compatibles
  344. These devices also show up as FTDI devices, but are not
  345. protocol-compatible with the FT2232 devices. They are, however,
  346. protocol-compatible among themselves. USB-JTAG devices typically consist
  347. of a FT245 followed by a CPLD that understands a particular protocol,
  348. or emulates this protocol using some other hardware.
  349. They may appear under different USB VID/PID depending on the particular
  350. product. The driver can be configured to search for any VID/PID pair
  351. (see the section on driver commands).
  352. @itemize
  353. @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
  354. @* Link: @url{}
  355. @item @b{Altera USB-Blaster}
  356. @* Link: @url{}
  357. @end itemize
  358. @section USB JLINK based
  359. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  360. an example of a micro controller based JTAG adapter, it uses an
  361. AT91SAM764 internally.
  362. @itemize @bullet
  363. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  364. @* Link: @url{}
  365. @item @b{SEGGER JLINK}
  366. @* Link: @url{}
  367. @item @b{IAR J-Link}
  368. @* Link: @url{}
  369. @end itemize
  370. @section USB RLINK based
  371. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
  372. permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
  373. SWD and not JTAG, thus not supported.
  374. @itemize @bullet
  375. @item @b{Raisonance RLink}
  376. @* Link: @url{}
  377. @item @b{STM32 Primer}
  378. @* Link: @url{}
  379. @item @b{STM32 Primer2}
  380. @* Link: @url{}
  381. @end itemize
  382. @section USB ST-LINK based
  383. ST Micro has an adapter called @b{ST-LINK}.
  384. They only work with ST Micro chips, notably STM32 and STM8.
  385. @itemize @bullet
  386. @item @b{ST-LINK}
  387. @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
  388. @* Link: @url{}
  389. @item @b{ST-LINK/V2}
  390. @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
  391. @* Link: @url{}
  392. @end itemize
  393. For info the original ST-LINK enumerates using the mass storage usb class; however,
  394. its implementation is completely broken. The result is this causes issues under Linux.
  395. The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
  396. @itemize @bullet
  397. @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
  398. @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
  399. @end itemize
  400. @section USB TI/Stellaris ICDI based
  401. Texas Instruments has an adapter called @b{ICDI}.
  402. It is not to be confused with the FTDI based adapters that were originally fitted to their
  403. evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
  404. @section USB CMSIS-DAP based
  405. ARM has released a interface standard called CMSIS-DAP that simplifies connecting
  406. debuggers to ARM Cortex based targets @url{}.
  407. @section USB Other
  408. @itemize @bullet
  409. @item @b{USBprog}
  410. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  411. @item @b{USB - Presto}
  412. @* Link: @url{}
  413. @item @b{Versaloon-Link}
  414. @* Link: @url{}
  415. @item @b{ARM-JTAG-EW}
  416. @* Link: @url{}
  417. @item @b{Buspirate}
  418. @* Link: @url{}
  419. @item @b{opendous}
  420. @* Link: @url{} - which uses an AT90USB162
  421. @item @b{estick}
  422. @* Link: @url{}
  423. @item @b{Keil ULINK v1}
  424. @* Link: @url{}
  425. @end itemize
  426. @section IBM PC Parallel Printer Port Based
  427. The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
  428. and the Macraigor Wiggler. There are many clones and variations of
  429. these on the market.
  430. Note that parallel ports are becoming much less common, so if you
  431. have the choice you should probably avoid these adapters in favor
  432. of USB-based ones.
  433. @itemize @bullet
  434. @item @b{Wiggler} - There are many clones of this.
  435. @* Link: @url{}
  436. @item @b{DLC5} - From XILINX - There are many clones of this
  437. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  438. produced, PDF schematics are easily found and it is easy to make.
  439. @item @b{Amontec - JTAG Accelerator}
  440. @* Link: @url{}
  441. @item @b{Wiggler2}
  442. @* Link: @url{}
  443. @item @b{Wiggler_ntrst_inverted}
  444. @* Yet another variation - See the source code, src/jtag/parport.c
  445. @item @b{old_amt_wiggler}
  446. @* Unknown - probably not on the market today
  447. @item @b{arm-jtag}
  448. @* Link: Most likely @url{} [another wiggler clone]
  449. @item @b{chameleon}
  450. @* Link: @url{}
  451. @item @b{Triton}
  452. @* Unknown.
  453. @item @b{Lattice}
  454. @* ispDownload from Lattice Semiconductor
  455. @url{}
  456. @item @b{flashlink}
  457. @* From ST Microsystems;
  458. @* Link: @url{}
  459. @end itemize
  460. @section Other...
  461. @itemize @bullet
  462. @item @b{ep93xx}
  463. @* An EP93xx based Linux machine using the GPIO pins directly.
  464. @item @b{at91rm9200}
  465. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  466. @item @b{bcm2835gpio}
  467. @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
  468. @item @b{jtag_vpi}
  469. @* A JTAG driver acting as a client for the JTAG VPI server interface.
  470. @* Link: @url{}
  471. @end itemize
  472. @node About Jim-Tcl
  473. @chapter About Jim-Tcl
  474. @cindex Jim-Tcl
  475. @cindex tcl
  476. OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
  477. This programming language provides a simple and extensible
  478. command interpreter.
  479. All commands presented in this Guide are extensions to Jim-Tcl.
  480. You can use them as simple commands, without needing to learn
  481. much of anything about Tcl.
  482. Alternatively, you can write Tcl programs with them.
  483. You can learn more about Jim at its website, @url{}.
  484. There is an active and responsive community, get on the mailing list
  485. if you have any questions. Jim-Tcl maintainers also lurk on the
  486. OpenOCD mailing list.
  487. @itemize @bullet
  488. @item @b{Jim vs. Tcl}
  489. @* Jim-Tcl is a stripped down version of the well known Tcl language,
  490. which can be found here: @url{}. Jim-Tcl has far
  491. fewer features. Jim-Tcl is several dozens of .C files and .H files and
  492. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  493. 4.2 MB .zip file containing 1540 files.
  494. @item @b{Missing Features}
  495. @* Our practice has been: Add/clone the real Tcl feature if/when
  496. needed. We welcome Jim-Tcl improvements, not bloat. Also there
  497. are a large number of optional Jim-Tcl features that are not
  498. enabled in OpenOCD.
  499. @item @b{Scripts}
  500. @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
  501. command interpreter today is a mixture of (newer)
  502. Jim-Tcl commands, and the (older) original command interpreter.
  503. @item @b{Commands}
  504. @* At the OpenOCD telnet command line (or via the GDB monitor command) one
  505. can type a Tcl for() loop, set variables, etc.
  506. Some of the commands documented in this guide are implemented
  507. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  508. @item @b{Historical Note}
  509. @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
  510. before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
  511. as a Git submodule, which greatly simplified upgrading Jim-Tcl
  512. to benefit from new features and bugfixes in Jim-Tcl.
  513. @item @b{Need a crash course in Tcl?}
  514. @*@xref{Tcl Crash Course}.
  515. @end itemize
  516. @node Running
  517. @chapter Running
  518. @cindex command line options
  519. @cindex logfile
  520. @cindex directory search
  521. Properly installing OpenOCD sets up your operating system to grant it access
  522. to the debug adapters. On Linux, this usually involves installing a file
  523. in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
  524. that works for many common adapters is shipped with OpenOCD in the
  525. @file{contrib} directory. MS-Windows needs
  526. complex and confusing driver configuration for every peripheral. Such issues
  527. are unique to each operating system, and are not detailed in this User's Guide.
  528. Then later you will invoke the OpenOCD server, with various options to
  529. tell it how each debug session should work.
  530. The @option{--help} option shows:
  531. @verbatim
  532. bash$ openocd --help
  533. --help | -h display this help
  534. --version | -v display OpenOCD version
  535. --file | -f use configuration file <name>
  536. --search | -s dir to search for config files and scripts
  537. --debug | -d set debug level <0-3>
  538. --log_output | -l redirect log output to file <name>
  539. --command | -c run <command>
  540. @end verbatim
  541. If you don't give any @option{-f} or @option{-c} options,
  542. OpenOCD tries to read the configuration file @file{openocd.cfg}.
  543. To specify one or more different
  544. configuration files, use @option{-f} options. For example:
  545. @example
  546. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  547. @end example
  548. Configuration files and scripts are searched for in
  549. @enumerate
  550. @item the current directory,
  551. @item any search dir specified on the command line using the @option{-s} option,
  552. @item any search dir specified using the @command{add_script_search_dir} command,
  553. @item @file{$HOME/.openocd} (not on Windows),
  554. @item the site wide script library @file{$pkgdatadir/site} and
  555. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  556. @end enumerate
  557. The first found file with a matching file name will be used.
  558. @quotation Note
  559. Don't try to use configuration script names or paths which
  560. include the "#" character. That character begins Tcl comments.
  561. @end quotation
  562. @section Simple setup, no customization
  563. In the best case, you can use two scripts from one of the script
  564. libraries, hook up your JTAG adapter, and start the server ... and
  565. your JTAG setup will just work "out of the box". Always try to
  566. start by reusing those scripts, but assume you'll need more
  567. customization even if this works. @xref{OpenOCD Project Setup}.
  568. If you find a script for your JTAG adapter, and for your board or
  569. target, you may be able to hook up your JTAG adapter then start
  570. the server with some variation of one of the following:
  571. @example
  572. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  573. openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
  574. @end example
  575. You might also need to configure which reset signals are present,
  576. using @option{-c 'reset_config trst_and_srst'} or something similar.
  577. If all goes well you'll see output something like
  578. @example
  579. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  580. For bug reports, read
  582. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  583. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  584. @end example
  585. Seeing that "tap/device found" message, and no warnings, means
  586. the JTAG communication is working. That's a key milestone, but
  587. you'll probably need more project-specific setup.
  588. @section What OpenOCD does as it starts
  589. OpenOCD starts by processing the configuration commands provided
  590. on the command line or, if there were no @option{-c command} or
  591. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  592. @xref{configurationstage,,Configuration Stage}.
  593. At the end of the configuration stage it verifies the JTAG scan
  594. chain defined using those commands; your configuration should
  595. ensure that this always succeeds.
  596. Normally, OpenOCD then starts running as a daemon.
  597. Alternatively, commands may be used to terminate the configuration
  598. stage early, perform work (such as updating some flash memory),
  599. and then shut down without acting as a daemon.
  600. Once OpenOCD starts running as a daemon, it waits for connections from
  601. clients (Telnet, GDB, Other) and processes the commands issued through
  602. those channels.
  603. If you are having problems, you can enable internal debug messages via
  604. the @option{-d} option.
  605. Also it is possible to interleave Jim-Tcl commands w/config scripts using the
  606. @option{-c} command line switch.
  607. To enable debug output (when reporting problems or working on OpenOCD
  608. itself), use the @option{-d} command line switch. This sets the
  609. @option{debug_level} to "3", outputting the most information,
  610. including debug messages. The default setting is "2", outputting only
  611. informational messages, warnings and errors. You can also change this
  612. setting from within a telnet or gdb session using @command{debug_level<n>}
  613. (@pxref{debuglevel,,debug_level}).
  614. You can redirect all output from the daemon to a file using the
  615. @option{-l <logfile>} switch.
  616. Note! OpenOCD will launch the GDB & telnet server even if it can not
  617. establish a connection with the target. In general, it is possible for
  618. the JTAG controller to be unresponsive until the target is set up
  619. correctly via e.g. GDB monitor commands in a GDB init script.
  620. @node OpenOCD Project Setup
  621. @chapter OpenOCD Project Setup
  622. To use OpenOCD with your development projects, you need to do more than
  623. just connect the JTAG adapter hardware (dongle) to your development board
  624. and start the OpenOCD server.
  625. You also need to configure your OpenOCD server so that it knows
  626. about your adapter and board, and helps your work.
  627. You may also want to connect OpenOCD to GDB, possibly
  628. using Eclipse or some other GUI.
  629. @section Hooking up the JTAG Adapter
  630. Today's most common case is a dongle with a JTAG cable on one side
  631. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  632. and a USB cable on the other.
  633. Instead of USB, some cables use Ethernet;
  634. older ones may use a PC parallel port, or even a serial port.
  635. @enumerate
  636. @item @emph{Start with power to your target board turned off},
  637. and nothing connected to your JTAG adapter.
  638. If you're particularly paranoid, unplug power to the board.
  639. It's important to have the ground signal properly set up,
  640. unless you are using a JTAG adapter which provides
  641. galvanic isolation between the target board and the
  642. debugging host.
  643. @item @emph{Be sure it's the right kind of JTAG connector.}
  644. If your dongle has a 20-pin ARM connector, you need some kind
  645. of adapter (or octopus, see below) to hook it up to
  646. boards using 14-pin or 10-pin connectors ... or to 20-pin
  647. connectors which don't use ARM's pinout.
  648. In the same vein, make sure the voltage levels are compatible.
  649. Not all JTAG adapters have the level shifters needed to work
  650. with 1.2 Volt boards.
  651. @item @emph{Be certain the cable is properly oriented} or you might
  652. damage your board. In most cases there are only two possible
  653. ways to connect the cable.
  654. Connect the JTAG cable from your adapter to the board.
  655. Be sure it's firmly connected.
  656. In the best case, the connector is keyed to physically
  657. prevent you from inserting it wrong.
  658. This is most often done using a slot on the board's male connector
  659. housing, which must match a key on the JTAG cable's female connector.
  660. If there's no housing, then you must look carefully and
  661. make sure pin 1 on the cable hooks up to pin 1 on the board.
  662. Ribbon cables are frequently all grey except for a wire on one
  663. edge, which is red. The red wire is pin 1.
  664. Sometimes dongles provide cables where one end is an ``octopus'' of
  665. color coded single-wire connectors, instead of a connector block.
  666. These are great when converting from one JTAG pinout to another,
  667. but are tedious to set up.
  668. Use these with connector pinout diagrams to help you match up the
  669. adapter signals to the right board pins.
  670. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  671. A USB, parallel, or serial port connector will go to the host which
  672. you are using to run OpenOCD.
  673. For Ethernet, consult the documentation and your network administrator.
  674. For USB-based JTAG adapters you have an easy sanity check at this point:
  675. does the host operating system see the JTAG adapter? If you're running
  676. Linux, try the @command{lsusb} command. If that host is an
  677. MS-Windows host, you'll need to install a driver before OpenOCD works.
  678. @item @emph{Connect the adapter's power supply, if needed.}
  679. This step is primarily for non-USB adapters,
  680. but sometimes USB adapters need extra power.
  681. @item @emph{Power up the target board.}
  682. Unless you just let the magic smoke escape,
  683. you're now ready to set up the OpenOCD server
  684. so you can use JTAG to work with that board.
  685. @end enumerate
  686. Talk with the OpenOCD server using
  687. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  688. @xref{GDB and OpenOCD}.
  689. @section Project Directory
  690. There are many ways you can configure OpenOCD and start it up.
  691. A simple way to organize them all involves keeping a
  692. single directory for your work with a given board.
  693. When you start OpenOCD from that directory,
  694. it searches there first for configuration files, scripts,
  695. files accessed through semihosting,
  696. and for code you upload to the target board.
  697. It is also the natural place to write files,
  698. such as log files and data you download from the board.
  699. @section Configuration Basics
  700. There are two basic ways of configuring OpenOCD, and
  701. a variety of ways you can mix them.
  702. Think of the difference as just being how you start the server:
  703. @itemize
  704. @item Many @option{-f file} or @option{-c command} options on the command line
  705. @item No options, but a @dfn{user config file}
  706. in the current directory named @file{openocd.cfg}
  707. @end itemize
  708. Here is an example @file{openocd.cfg} file for a setup
  709. using a Signalyzer FT2232-based JTAG adapter to talk to
  710. a board with an Atmel AT91SAM7X256 microcontroller:
  711. @example
  712. source [find interface/signalyzer.cfg]
  713. # GDB can also flash my flash!
  714. gdb_memory_map enable
  715. gdb_flash_program enable
  716. source [find target/sam7x256.cfg]
  717. @end example
  718. Here is the command line equivalent of that configuration:
  719. @example
  720. openocd -f interface/signalyzer.cfg \
  721. -c "gdb_memory_map enable" \
  722. -c "gdb_flash_program enable" \
  723. -f target/sam7x256.cfg
  724. @end example
  725. You could wrap such long command lines in shell scripts,
  726. each supporting a different development task.
  727. One might re-flash the board with a specific firmware version.
  728. Another might set up a particular debugging or run-time environment.
  729. @quotation Important
  730. At this writing (October 2009) the command line method has
  731. problems with how it treats variables.
  732. For example, after @option{-c "set VAR value"}, or doing the
  733. same in a script, the variable @var{VAR} will have no value
  734. that can be tested in a later script.
  735. @end quotation
  736. Here we will focus on the simpler solution: one user config
  737. file, including basic configuration plus any TCL procedures
  738. to simplify your work.
  739. @section User Config Files
  740. @cindex config file, user
  741. @cindex user config file
  742. @cindex config file, overview
  743. A user configuration file ties together all the parts of a project
  744. in one place.
  745. One of the following will match your situation best:
  746. @itemize
  747. @item Ideally almost everything comes from configuration files
  748. provided by someone else.
  749. For example, OpenOCD distributes a @file{scripts} directory
  750. (probably in @file{/usr/share/openocd/scripts} on Linux).
  751. Board and tool vendors can provide these too, as can individual
  752. user sites; the @option{-s} command line option lets you say
  753. where to find these files. (@xref{Running}.)
  754. The AT91SAM7X256 example above works this way.
  755. Three main types of non-user configuration file each have their
  756. own subdirectory in the @file{scripts} directory:
  757. @enumerate
  758. @item @b{interface} -- one for each different debug adapter;
  759. @item @b{board} -- one for each different board
  760. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  761. @end enumerate
  762. Best case: include just two files, and they handle everything else.
  763. The first is an interface config file.
  764. The second is board-specific, and it sets up the JTAG TAPs and
  765. their GDB targets (by deferring to some @file{target.cfg} file),
  766. declares all flash memory, and leaves you nothing to do except
  767. meet your deadline:
  768. @example
  769. source [find interface/olimex-jtag-tiny.cfg]
  770. source [find board/csb337.cfg]
  771. @end example
  772. Boards with a single microcontroller often won't need more
  773. than the target config file, as in the AT91SAM7X256 example.
  774. That's because there is no external memory (flash, DDR RAM), and
  775. the board differences are encapsulated by application code.
  776. @item Maybe you don't know yet what your board looks like to JTAG.
  777. Once you know the @file{interface.cfg} file to use, you may
  778. need help from OpenOCD to discover what's on the board.
  779. Once you find the JTAG TAPs, you can just search for appropriate
  780. target and board
  781. configuration files ... or write your own, from the bottom up.
  782. @xref{autoprobing,,Autoprobing}.
  783. @item You can often reuse some standard config files but
  784. need to write a few new ones, probably a @file{board.cfg} file.
  785. You will be using commands described later in this User's Guide,
  786. and working with the guidelines in the next chapter.
  787. For example, there may be configuration files for your JTAG adapter
  788. and target chip, but you need a new board-specific config file
  789. giving access to your particular flash chips.
  790. Or you might need to write another target chip configuration file
  791. for a new chip built around the Cortex M3 core.
  792. @quotation Note
  793. When you write new configuration files, please submit
  794. them for inclusion in the next OpenOCD release.
  795. For example, a @file{board/newboard.cfg} file will help the
  796. next users of that board, and a @file{target/newcpu.cfg}
  797. will help support users of any board using that chip.
  798. @end quotation
  799. @item
  800. You may may need to write some C code.
  801. It may be as simple as supporting a new FT2232 or parport
  802. based adapter; a bit more involved, like a NAND or NOR flash
  803. controller driver; or a big piece of work like supporting
  804. a new chip architecture.
  805. @end itemize
  806. Reuse the existing config files when you can.
  807. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  808. You may find a board configuration that's a good example to follow.
  809. When you write config files, separate the reusable parts
  810. (things every user of that interface, chip, or board needs)
  811. from ones specific to your environment and debugging approach.
  812. @itemize
  813. @item
  814. For example, a @code{gdb-attach} event handler that invokes
  815. the @command{reset init} command will interfere with debugging
  816. early boot code, which performs some of the same actions
  817. that the @code{reset-init} event handler does.
  818. @item
  819. Likewise, the @command{arm9 vector_catch} command (or
  820. @cindex vector_catch
  821. its siblings @command{xscale vector_catch}
  822. and @command{cortex_m vector_catch}) can be a timesaver
  823. during some debug sessions, but don't make everyone use that either.
  824. Keep those kinds of debugging aids in your user config file,
  825. along with messaging and tracing setup.
  826. (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
  827. @item
  828. You might need to override some defaults.
  829. For example, you might need to move, shrink, or back up the target's
  830. work area if your application needs much SRAM.
  831. @item
  832. TCP/IP port configuration is another example of something which
  833. is environment-specific, and should only appear in
  834. a user config file. @xref{tcpipports,,TCP/IP Ports}.
  835. @end itemize
  836. @section Project-Specific Utilities
  837. A few project-specific utility
  838. routines may well speed up your work.
  839. Write them, and keep them in your project's user config file.
  840. For example, if you are making a boot loader work on a
  841. board, it's nice to be able to debug the ``after it's
  842. loaded to RAM'' parts separately from the finicky early
  843. code which sets up the DDR RAM controller and clocks.
  844. A script like this one, or a more GDB-aware sibling,
  845. may help:
  846. @example
  847. proc ramboot @{ @} @{
  848. # Reset, running the target's "reset-init" scripts
  849. # to initialize clocks and the DDR RAM controller.
  850. # Leave the CPU halted.
  851. reset init
  852. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  853. load_image u-boot.bin 0x20000000
  854. # Start running.
  855. resume 0x20000000
  856. @}
  857. @end example
  858. Then once that code is working you will need to make it
  859. boot from NOR flash; a different utility would help.
  860. Alternatively, some developers write to flash using GDB.
  861. (You might use a similar script if you're working with a flash
  862. based microcontroller application instead of a boot loader.)
  863. @example
  864. proc newboot @{ @} @{
  865. # Reset, leaving the CPU halted. The "reset-init" event
  866. # proc gives faster access to the CPU and to NOR flash;
  867. # "reset halt" would be slower.
  868. reset init
  869. # Write standard version of U-Boot into the first two
  870. # sectors of NOR flash ... the standard version should
  871. # do the same lowlevel init as "reset-init".
  872. flash protect 0 0 1 off
  873. flash erase_sector 0 0 1
  874. flash write_bank 0 u-boot.bin 0x0
  875. flash protect 0 0 1 on
  876. # Reboot from scratch using that new boot loader.
  877. reset run
  878. @}
  879. @end example
  880. You may need more complicated utility procedures when booting
  881. from NAND.
  882. That often involves an extra bootloader stage,
  883. running from on-chip SRAM to perform DDR RAM setup so it can load
  884. the main bootloader code (which won't fit into that SRAM).
  885. Other helper scripts might be used to write production system images,
  886. involving considerably more than just a three stage bootloader.
  887. @section Target Software Changes
  888. Sometimes you may want to make some small changes to the software
  889. you're developing, to help make JTAG debugging work better.
  890. For example, in C or assembly language code you might
  891. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  892. handling issues like:
  893. @itemize @bullet
  894. @item @b{Watchdog Timers}...
  895. Watchog timers are typically used to automatically reset systems if
  896. some application task doesn't periodically reset the timer. (The
  897. assumption is that the system has locked up if the task can't run.)
  898. When a JTAG debugger halts the system, that task won't be able to run
  899. and reset the timer ... potentially causing resets in the middle of
  900. your debug sessions.
  901. It's rarely a good idea to disable such watchdogs, since their usage
  902. needs to be debugged just like all other parts of your firmware.
  903. That might however be your only option.
  904. Look instead for chip-specific ways to stop the watchdog from counting
  905. while the system is in a debug halt state. It may be simplest to set
  906. that non-counting mode in your debugger startup scripts. You may however
  907. need a different approach when, for example, a motor could be physically
  908. damaged by firmware remaining inactive in a debug halt state. That might
  909. involve a type of firmware mode where that "non-counting" mode is disabled
  910. at the beginning then re-enabled at the end; a watchdog reset might fire
  911. and complicate the debug session, but hardware (or people) would be
  912. protected.@footnote{Note that many systems support a "monitor mode" debug
  913. that is a somewhat cleaner way to address such issues. You can think of
  914. it as only halting part of the system, maybe just one task,
  915. instead of the whole thing.
  916. At this writing, January 2010, OpenOCD based debugging does not support
  917. monitor mode debug, only "halt mode" debug.}
  918. @item @b{ARM Semihosting}...
  919. @cindex ARM semihosting
  920. When linked with a special runtime library provided with many
  921. toolchains@footnote{See chapter 8 "Semihosting" in
  922. @uref{,
  923. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  924. The CodeSourcery EABI toolchain also includes a semihosting library.},
  925. your target code can use I/O facilities on the debug host. That library
  926. provides a small set of system calls which are handled by OpenOCD.
  927. It can let the debugger provide your system console and a file system,
  928. helping with early debugging or providing a more capable environment
  929. for sometimes-complex tasks like installing system firmware onto
  930. NAND or SPI flash.
  931. @item @b{ARM Wait-For-Interrupt}...
  932. Many ARM chips synchronize the JTAG clock using the core clock.
  933. Low power states which stop that core clock thus prevent JTAG access.
  934. Idle loops in tasking environments often enter those low power states
  935. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  936. You may want to @emph{disable that instruction} in source code,
  937. or otherwise prevent using that state,
  938. to ensure you can get JTAG access at any time.@footnote{As a more
  939. polite alternative, some processors have special debug-oriented
  940. registers which can be used to change various features including
  941. how the low power states are clocked while debugging.
  942. The STM32 DBGMCU_CR register is an example; at the cost of extra
  943. power consumption, JTAG can be used during low power states.}
  944. For example, the OpenOCD @command{halt} command may not
  945. work for an idle processor otherwise.
  946. @item @b{Delay after reset}...
  947. Not all chips have good support for debugger access
  948. right after reset; many LPC2xxx chips have issues here.
  949. Similarly, applications that reconfigure pins used for
  950. JTAG access as they start will also block debugger access.
  951. To work with boards like this, @emph{enable a short delay loop}
  952. the first thing after reset, before "real" startup activities.
  953. For example, one second's delay is usually more than enough
  954. time for a JTAG debugger to attach, so that
  955. early code execution can be debugged
  956. or firmware can be replaced.
  957. @item @b{Debug Communications Channel (DCC)}...
  958. Some processors include mechanisms to send messages over JTAG.
  959. Many ARM cores support these, as do some cores from other vendors.
  960. (OpenOCD may be able to use this DCC internally, speeding up some
  961. operations like writing to memory.)
  962. Your application may want to deliver various debugging messages
  963. over JTAG, by @emph{linking with a small library of code}
  964. provided with OpenOCD and using the utilities there to send
  965. various kinds of message.
  966. @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
  967. @end itemize
  968. @section Target Hardware Setup
  969. Chip vendors often provide software development boards which
  970. are highly configurable, so that they can support all options
  971. that product boards may require. @emph{Make sure that any
  972. jumpers or switches match the system configuration you are
  973. working with.}
  974. Common issues include:
  975. @itemize @bullet
  976. @item @b{JTAG setup} ...
  977. Boards may support more than one JTAG configuration.
  978. Examples include jumpers controlling pullups versus pulldowns
  979. on the nTRST and/or nSRST signals, and choice of connectors
  980. (e.g. which of two headers on the base board,
  981. or one from a daughtercard).
  982. For some Texas Instruments boards, you may need to jumper the
  983. EMU0 and EMU1 signals (which OpenOCD won't currently control).
  984. @item @b{Boot Modes} ...
  985. Complex chips often support multiple boot modes, controlled
  986. by external jumpers. Make sure this is set up correctly.
  987. For example many i.MX boards from NXP need to be jumpered
  988. to "ATX mode" to start booting using the on-chip ROM, when
  989. using second stage bootloader code stored in a NAND flash chip.
  990. Such explicit configuration is common, and not limited to
  991. booting from NAND. You might also need to set jumpers to
  992. start booting using code loaded from an MMC/SD card; external
  993. SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
  994. flash; some external host; or various other sources.
  995. @item @b{Memory Addressing} ...
  996. Boards which support multiple boot modes may also have jumpers
  997. to configure memory addressing. One board, for example, jumpers
  998. external chipselect 0 (used for booting) to address either
  999. a large SRAM (which must be pre-loaded via JTAG), NOR flash,
  1000. or NAND flash. When it's jumpered to address NAND flash, that
  1001. board must also be told to start booting from on-chip ROM.
  1002. Your @file{board.cfg} file may also need to be told this jumper
  1003. configuration, so that it can know whether to declare NOR flash
  1004. using @command{flash bank} or instead declare NAND flash with
  1005. @command{nand device}; and likewise which probe to perform in
  1006. its @code{reset-init} handler.
  1007. A closely related issue is bus width. Jumpers might need to
  1008. distinguish between 8 bit or 16 bit bus access for the flash
  1009. used to start booting.
  1010. @item @b{Peripheral Access} ...
  1011. Development boards generally provide access to every peripheral
  1012. on the chip, sometimes in multiple modes (such as by providing
  1013. multiple audio codec chips).
  1014. This interacts with software
  1015. configuration of pin multiplexing, where for example a
  1016. given pin may be routed either to the MMC/SD controller
  1017. or the GPIO controller. It also often interacts with
  1018. configuration jumpers. One jumper may be used to route
  1019. signals to an MMC/SD card slot or an expansion bus (which
  1020. might in turn affect booting); others might control which
  1021. audio or video codecs are used.
  1022. @end itemize
  1023. Plus you should of course have @code{reset-init} event handlers
  1024. which set up the hardware to match that jumper configuration.
  1025. That includes in particular any oscillator or PLL used to clock
  1026. the CPU, and any memory controllers needed to access external
  1027. memory and peripherals. Without such handlers, you won't be
  1028. able to access those resources without working target firmware
  1029. which can do that setup ... this can be awkward when you're
  1030. trying to debug that target firmware. Even if there's a ROM
  1031. bootloader which handles a few issues, it rarely provides full
  1032. access to all board-specific capabilities.
  1033. @node Config File Guidelines
  1034. @chapter Config File Guidelines
  1035. This chapter is aimed at any user who needs to write a config file,
  1036. including developers and integrators of OpenOCD and any user who
  1037. needs to get a new board working smoothly.
  1038. It provides guidelines for creating those files.
  1039. You should find the following directories under
  1040. @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
  1041. them as-is where you can; or as models for new files.
  1042. @itemize @bullet
  1043. @item @file{interface} ...
  1044. These are for debug adapters. Files that specify configuration to use
  1045. specific JTAG, SWD and other adapters go here.
  1046. @item @file{board} ...
  1047. Think Circuit Board, PWA, PCB, they go by many names. Board files
  1048. contain initialization items that are specific to a board.
  1049. They reuse target configuration files, since the same
  1050. microprocessor chips are used on many boards,
  1051. but support for external parts varies widely. For
  1052. example, the SDRAM initialization sequence for the board, or the type
  1053. of external flash and what address it uses. Any initialization
  1054. sequence to enable that external flash or SDRAM should be found in the
  1055. board file. Boards may also contain multiple targets: two CPUs; or
  1056. a CPU and an FPGA.
  1057. @item @file{target} ...
  1058. Think chip. The ``target'' directory represents the JTAG TAPs
  1059. on a chip
  1060. which OpenOCD should control, not a board. Two common types of targets
  1061. are ARM chips and FPGA or CPLD chips.
  1062. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  1063. the target config file defines all of them.
  1064. @item @emph{more} ... browse for other library files which may be useful.
  1065. For example, there are various generic and CPU-specific utilities.
  1066. @end itemize
  1067. The @file{openocd.cfg} user config
  1068. file may override features in any of the above files by
  1069. setting variables before sourcing the target file, or by adding
  1070. commands specific to their situation.
  1071. @section Interface Config Files
  1072. The user config file
  1073. should be able to source one of these files with a command like this:
  1074. @example
  1075. source [find interface/FOOBAR.cfg]
  1076. @end example
  1077. A preconfigured interface file should exist for every debug adapter
  1078. in use today with OpenOCD.
  1079. That said, perhaps some of these config files
  1080. have only been used by the developer who created it.
  1081. A separate chapter gives information about how to set these up.
  1082. @xref{Debug Adapter Configuration}.
  1083. Read the OpenOCD source code (and Developer's Guide)
  1084. if you have a new kind of hardware interface
  1085. and need to provide a driver for it.
  1086. @section Board Config Files
  1087. @cindex config file, board
  1088. @cindex board config file
  1089. The user config file
  1090. should be able to source one of these files with a command like this:
  1091. @example
  1092. source [find board/FOOBAR.cfg]
  1093. @end example
  1094. The point of a board config file is to package everything
  1095. about a given board that user config files need to know.
  1096. In summary the board files should contain (if present)
  1097. @enumerate
  1098. @item One or more @command{source [find target/...cfg]} statements
  1099. @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
  1100. @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
  1101. @item Target @code{reset} handlers for SDRAM and I/O configuration
  1102. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  1103. @item All things that are not ``inside a chip''
  1104. @end enumerate
  1105. Generic things inside target chips belong in target config files,
  1106. not board config files. So for example a @code{reset-init} event
  1107. handler should know board-specific oscillator and PLL parameters,
  1108. which it passes to target-specific utility code.
  1109. The most complex task of a board config file is creating such a
  1110. @code{reset-init} event handler.
  1111. Define those handlers last, after you verify the rest of the board
  1112. configuration works.
  1113. @subsection Communication Between Config files
  1114. In addition to target-specific utility code, another way that
  1115. board and target config files communicate is by following a
  1116. convention on how to use certain variables.
  1117. The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
  1118. Thus the rule we follow in OpenOCD is this: Variables that begin with
  1119. a leading underscore are temporary in nature, and can be modified and
  1120. used at will within a target configuration file.
  1121. Complex board config files can do the things like this,
  1122. for a board with three chips:
  1123. @example
  1124. # Chip #1: PXA270 for network side, big endian
  1125. set CHIPNAME network
  1126. set ENDIAN big
  1127. source [find target/pxa270.cfg]
  1128. # on return: _TARGETNAME = network.cpu
  1129. # other commands can refer to the "network.cpu" target.
  1130. $_TARGETNAME configure .... events for this CPU..
  1131. # Chip #2: PXA270 for video side, little endian
  1132. set CHIPNAME video
  1133. set ENDIAN little
  1134. source [find target/pxa270.cfg]
  1135. # on return: _TARGETNAME = video.cpu
  1136. # other commands can refer to the "video.cpu" target.
  1137. $_TARGETNAME configure .... events for this CPU..
  1138. # Chip #3: Xilinx FPGA for glue logic
  1139. set CHIPNAME xilinx
  1140. unset ENDIAN
  1141. source [find target/spartan3.cfg]
  1142. @end example
  1143. That example is oversimplified because it doesn't show any flash memory,
  1144. or the @code{reset-init} event handlers to initialize external DRAM
  1145. or (assuming it needs it) load a configuration into the FPGA.
  1146. Such features are usually needed for low-level work with many boards,
  1147. where ``low level'' implies that the board initialization software may
  1148. not be working. (That's a common reason to need JTAG tools. Another
  1149. is to enable working with microcontroller-based systems, which often
  1150. have no debugging support except a JTAG connector.)
  1151. Target config files may also export utility functions to board and user
  1152. config files. Such functions should use name prefixes, to help avoid
  1153. naming collisions.
  1154. Board files could also accept input variables from user config files.
  1155. For example, there might be a @code{J4_JUMPER} setting used to identify
  1156. what kind of flash memory a development board is using, or how to set
  1157. up other clocks and peripherals.
  1158. @subsection Variable Naming Convention
  1159. @cindex variable names
  1160. Most boards have only one instance of a chip.
  1161. However, it should be easy to create a board with more than
  1162. one such chip (as shown above).
  1163. Accordingly, we encourage these conventions for naming
  1164. variables associated with different @file{target.cfg} files,
  1165. to promote consistency and
  1166. so that board files can override target defaults.
  1167. Inputs to target config files include:
  1168. @itemize @bullet
  1169. @item @code{CHIPNAME} ...
  1170. This gives a name to the overall chip, and is used as part of
  1171. tap identifier dotted names.
  1172. While the default is normally provided by the chip manufacturer,
  1173. board files may need to distinguish between instances of a chip.
  1174. @item @code{ENDIAN} ...
  1175. By default @option{little} - although chips may hard-wire @option{big}.
  1176. Chips that can't change endianness don't need to use this variable.
  1177. @item @code{CPUTAPID} ...
  1178. When OpenOCD examines the JTAG chain, it can be told verify the
  1179. chips against the JTAG IDCODE register.
  1180. The target file will hold one or more defaults, but sometimes the
  1181. chip in a board will use a different ID (perhaps a newer revision).
  1182. @end itemize
  1183. Outputs from target config files include:
  1184. @itemize @bullet
  1185. @item @code{_TARGETNAME} ...
  1186. By convention, this variable is created by the target configuration
  1187. script. The board configuration file may make use of this variable to
  1188. configure things like a ``reset init'' script, or other things
  1189. specific to that board and that target.
  1190. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  1191. @code{_TARGETNAME1}, ... etc.
  1192. @end itemize
  1193. @subsection The reset-init Event Handler
  1194. @cindex event, reset-init
  1195. @cindex reset-init handler
  1196. Board config files run in the OpenOCD configuration stage;
  1197. they can't use TAPs or targets, since they haven't been
  1198. fully set up yet.
  1199. This means you can't write memory or access chip registers;
  1200. you can't even verify that a flash chip is present.
  1201. That's done later in event handlers, of which the target @code{reset-init}
  1202. handler is one of the most important.
  1203. Except on microcontrollers, the basic job of @code{reset-init} event
  1204. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1205. Microcontrollers rarely use boot loaders; they run right out of their
  1206. on-chip flash and SRAM memory. But they may want to use one of these
  1207. handlers too, if just for developer convenience.
  1208. @quotation Note
  1209. Because this is so very board-specific, and chip-specific, no examples
  1210. are included here.
  1211. Instead, look at the board config files distributed with OpenOCD.
  1212. If you have a boot loader, its source code will help; so will
  1213. configuration files for other JTAG tools
  1214. (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
  1215. @end quotation
  1216. Some of this code could probably be shared between different boards.
  1217. For example, setting up a DRAM controller often doesn't differ by
  1218. much except the bus width (16 bits or 32?) and memory timings, so a
  1219. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1220. those as parameters.
  1221. Similarly with oscillator, PLL, and clock setup;
  1222. and disabling the watchdog.
  1223. Structure the code cleanly, and provide comments to help
  1224. the next developer doing such work.
  1225. (@emph{You might be that next person} trying to reuse init code!)
  1226. The last thing normally done in a @code{reset-init} handler is probing
  1227. whatever flash memory was configured. For most chips that needs to be
  1228. done while the associated target is halted, either because JTAG memory
  1229. access uses the CPU or to prevent conflicting CPU access.
  1230. @subsection JTAG Clock Rate
  1231. Before your @code{reset-init} handler has set up
  1232. the PLLs and clocking, you may need to run with
  1233. a low JTAG clock rate.
  1234. @xref{jtagspeed,,JTAG Speed}.
  1235. Then you'd increase that rate after your handler has
  1236. made it possible to use the faster JTAG clock.
  1237. When the initial low speed is board-specific, for example
  1238. because it depends on a board-specific oscillator speed, then
  1239. you should probably set it up in the board config file;
  1240. if it's target-specific, it belongs in the target config file.
  1241. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1242. @uref{} gives details.}
  1243. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1244. Consult chip documentation to determine the peak JTAG clock rate,
  1245. which might be less than that.
  1246. @quotation Warning
  1247. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1248. software using a @option{wait for interrupt} operation blocks JTAG access.
  1249. Adaptive clocking provides a partial workaround, but a more complete
  1250. solution just avoids using that instruction with JTAG debuggers.
  1251. @end quotation
  1252. If both the chip and the board support adaptive clocking,
  1253. use the @command{jtag_rclk}
  1254. command, in case your board is used with JTAG adapter which
  1255. also supports it. Otherwise use @command{adapter_khz}.
  1256. Set the slow rate at the beginning of the reset sequence,
  1257. and the faster rate as soon as the clocks are at full speed.
  1258. @anchor{theinitboardprocedure}
  1259. @subsection The init_board procedure
  1260. @cindex init_board procedure
  1261. The concept of @code{init_board} procedure is very similar to @code{init_targets}
  1262. (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
  1263. configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
  1264. (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
  1265. separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
  1266. everything target specific (internal flash, internal RAM, etc.) and the second one to configure
  1267. everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
  1268. Additionally ``linear'' board config file will most likely fail when target config file uses
  1269. @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
  1270. so separating these two configuration stages is very convenient, as the easiest way to overcome this
  1271. problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
  1272. need to override @code{init_targets} defined in target config files when they only need to add some specifics.
  1273. Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
  1274. the original), allowing greater code reuse.
  1275. @example
  1276. ### board_file.cfg ###
  1277. # source target file that does most of the config in init_targets
  1278. source [find target/target.cfg]
  1279. proc enable_fast_clock @{@} @{
  1280. # enables fast on-board clock source
  1281. # configures the chip to use it
  1282. @}
  1283. # initialize only board specifics - reset, clock, adapter frequency
  1284. proc init_board @{@} @{
  1285. reset_config trst_and_srst trst_pulls_srst
  1286. $_TARGETNAME configure -event reset-init @{
  1287. adapter_khz 1
  1288. enable_fast_clock
  1289. adapter_khz 10000
  1290. @}
  1291. @}
  1292. @end example
  1293. @section Target Config Files
  1294. @cindex config file, target
  1295. @cindex target config file
  1296. Board config files communicate with target config files using
  1297. naming conventions as described above, and may source one or
  1298. more target config files like this:
  1299. @example
  1300. source [find target/FOOBAR.cfg]
  1301. @end example
  1302. The point of a target config file is to package everything
  1303. about a given chip that board config files need to know.
  1304. In summary the target files should contain
  1305. @enumerate
  1306. @item Set defaults
  1307. @item Add TAPs to the scan chain
  1308. @item Add CPU targets (includes GDB support)
  1309. @item CPU/Chip/CPU-Core specific features
  1310. @item On-Chip flash
  1311. @end enumerate
  1312. As a rule of thumb, a target file sets up only one chip.
  1313. For a microcontroller, that will often include a single TAP,
  1314. which is a CPU needing a GDB target, and its on-chip flash.
  1315. More complex chips may include multiple TAPs, and the target
  1316. config file may need to define them all before OpenOCD
  1317. can talk to the chip.
  1318. For example, some phone chips have JTAG scan chains that include
  1319. an ARM core for operating system use, a DSP,
  1320. another ARM core embedded in an image processing engine,
  1321. and other processing engines.
  1322. @subsection Default Value Boiler Plate Code
  1323. All target configuration files should start with code like this,
  1324. letting board config files express environment-specific
  1325. differences in how things should be set up.
  1326. @example
  1327. # Boards may override chip names, perhaps based on role,
  1328. # but the default should match what the vendor uses
  1329. if @{ [info exists CHIPNAME] @} @{
  1331. @} else @{
  1332. set _CHIPNAME sam7x256
  1333. @}
  1334. # ONLY use ENDIAN with targets that can change it.
  1335. if @{ [info exists ENDIAN] @} @{
  1336. set _ENDIAN $ENDIAN
  1337. @} else @{
  1338. set _ENDIAN little
  1339. @}
  1340. # TAP identifiers may change as chips mature, for example with
  1341. # new revision fields (the "3" here). Pick a good default; you
  1342. # can pass several such identifiers to the "jtag newtap" command.
  1343. if @{ [info exists CPUTAPID ] @} @{
  1345. @} else @{
  1346. set _CPUTAPID 0x3f0f0f0f
  1347. @}
  1348. @end example
  1349. @c but 0x3f0f0f0f is for an str73x part ...
  1350. @emph{Remember:} Board config files may include multiple target
  1351. config files, or the same target file multiple times
  1352. (changing at least @code{CHIPNAME}).
  1353. Likewise, the target configuration file should define
  1354. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1355. use it later on when defining debug targets:
  1356. @example
  1357. set _TARGETNAME $_CHIPNAME.cpu
  1358. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1359. @end example
  1360. @subsection Adding TAPs to the Scan Chain
  1361. After the ``defaults'' are set up,
  1362. add the TAPs on each chip to the JTAG scan chain.
  1363. @xref{TAP Declaration}, and the naming convention
  1364. for taps.
  1365. In the simplest case the chip has only one TAP,
  1366. probably for a CPU or FPGA.
  1367. The config file for the Atmel AT91SAM7X256
  1368. looks (in part) like this:
  1369. @example
  1370. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1371. @end example
  1372. A board with two such at91sam7 chips would be able
  1373. to source such a config file twice, with different
  1374. values for @code{CHIPNAME}, so
  1375. it adds a different TAP each time.
  1376. If there are nonzero @option{-expected-id} values,
  1377. OpenOCD attempts to verify the actual tap id against those values.
  1378. It will issue error messages if there is mismatch, which
  1379. can help to pinpoint problems in OpenOCD configurations.
  1380. @example
  1381. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1382. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1383. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1384. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1385. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1386. @end example
  1387. There are more complex examples too, with chips that have
  1388. multiple TAPs. Ones worth looking at include:
  1389. @itemize
  1390. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1391. plus a JRC to enable them
  1392. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1393. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1394. is not currently used)
  1395. @end itemize
  1396. @subsection Add CPU targets
  1397. After adding a TAP for a CPU, you should set it up so that
  1398. GDB and other commands can use it.
  1399. @xref{CPU Configuration}.
  1400. For the at91sam7 example above, the command can look like this;
  1401. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1402. to little endian, and this chip doesn't support changing that.
  1403. @example
  1404. set _TARGETNAME $_CHIPNAME.cpu
  1405. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1406. @end example
  1407. Work areas are small RAM areas associated with CPU targets.
  1408. They are used by OpenOCD to speed up downloads,
  1409. and to download small snippets of code to program flash chips.
  1410. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1411. a work area if you can.
  1412. Again using the at91sam7 as an example, this can look like:
  1413. @example
  1414. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1415. -work-area-size 0x4000 -work-area-backup 0
  1416. @end example
  1417. @anchor{definecputargetsworkinginsmp}
  1418. @subsection Define CPU targets working in SMP
  1419. @cindex SMP
  1420. After setting targets, you can define a list of targets working in SMP.
  1421. @example
  1422. set _TARGETNAME_1 $_CHIPNAME.cpu1
  1423. set _TARGETNAME_2 $_CHIPNAME.cpu2
  1424. target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
  1425. -coreid 0 -dbgbase $_DAP_DBG1
  1426. target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
  1427. -coreid 1 -dbgbase $_DAP_DBG2
  1428. #define 2 targets working in smp.
  1429. target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
  1430. @end example
  1431. In the above example on cortex_a, 2 cpus are working in SMP.
  1432. In SMP only one GDB instance is created and :
  1433. @itemize @bullet
  1434. @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
  1435. @item halt command triggers the halt of all targets in the list.
  1436. @item resume command triggers the write context and the restart of all targets in the list.
  1437. @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
  1438. @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
  1439. displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
  1440. @end itemize
  1441. The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
  1442. command have been implemented.
  1443. @itemize @bullet
  1444. @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
  1445. @item cortex_a smp_off : disable SMP mode, the current target is the one
  1446. displayed in the GDB session, only this target is now controlled by GDB
  1447. session. This behaviour is useful during system boot up.
  1448. @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
  1449. following example.
  1450. @end itemize
  1451. @example
  1452. >cortex_a smp_gdb
  1453. gdb coreid 0 -> -1
  1454. #0 : coreid 0 is displayed to GDB ,
  1455. #-> -1 : next resume triggers a real resume
  1456. > cortex_a smp_gdb 1
  1457. gdb coreid 0 -> 1
  1458. #0 :coreid 0 is displayed to GDB ,
  1459. #->1 : next resume displays coreid 1 to GDB
  1460. > resume
  1461. > cortex_a smp_gdb
  1462. gdb coreid 1 -> 1
  1463. #1 :coreid 1 is displayed to GDB ,
  1464. #->1 : next resume displays coreid 1 to GDB
  1465. > cortex_a smp_gdb -1
  1466. gdb coreid 1 -> -1
  1467. #1 :coreid 1 is displayed to GDB,
  1468. #->-1 : next resume triggers a real resume
  1469. @end example
  1470. @subsection Chip Reset Setup
  1471. As a rule, you should put the @command{reset_config} command
  1472. into the board file. Most things you think you know about a
  1473. chip can be tweaked by the board.
  1474. Some chips have specific ways the TRST and SRST signals are
  1475. managed. In the unusual case that these are @emph{chip specific}
  1476. and can never be changed by board wiring, they could go here.
  1477. For example, some chips can't support JTAG debugging without
  1478. both signals.
  1479. Provide a @code{reset-assert} event handler if you can.
  1480. Such a handler uses JTAG operations to reset the target,
  1481. letting this target config be used in systems which don't
  1482. provide the optional SRST signal, or on systems where you
  1483. don't want to reset all targets at once.
  1484. Such a handler might write to chip registers to force a reset,
  1485. use a JRC to do that (preferable -- the target may be wedged!),
  1486. or force a watchdog timer to trigger.
  1487. (For Cortex-M targets, this is not necessary. The target
  1488. driver knows how to use trigger an NVIC reset when SRST is
  1489. not available.)
  1490. Some chips need special attention during reset handling if
  1491. they're going to be used with JTAG.
  1492. An example might be needing to send some commands right
  1493. after the target's TAP has been reset, providing a
  1494. @code{reset-deassert-post} event handler that writes a chip
  1495. register to report that JTAG debugging is being done.
  1496. Another would be reconfiguring the watchdog so that it stops
  1497. counting while the core is halted in the debugger.
  1498. JTAG clocking constraints often change during reset, and in
  1499. some cases target config files (rather than board config files)
  1500. are the right places to handle some of those issues.
  1501. For example, immediately after reset most chips run using a
  1502. slower clock than they will use later.
  1503. That means that after reset (and potentially, as OpenOCD
  1504. first starts up) they must use a slower JTAG clock rate
  1505. than they will use later.
  1506. @xref{jtagspeed,,JTAG Speed}.
  1507. @quotation Important
  1508. When you are debugging code that runs right after chip
  1509. reset, getting these issues right is critical.
  1510. In particular, if you see intermittent failures when
  1511. OpenOCD verifies the scan chain after reset,
  1512. look at how you are setting up JTAG clocking.
  1513. @end quotation
  1514. @anchor{theinittargetsprocedure}
  1515. @subsection The init_targets procedure
  1516. @cindex init_targets procedure
  1517. Target config files can either be ``linear'' (script executed line-by-line when parsed in
  1518. configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
  1519. procedure called @code{init_targets}, which will be executed when entering run stage
  1520. (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
  1521. Such procedure can be overriden by ``next level'' script (which sources the original).
  1522. This concept faciliates code reuse when basic target config files provide generic configuration
  1523. procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
  1524. a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
  1525. because sourcing them executes every initialization commands they provide.
  1526. @example
  1527. ### generic_file.cfg ###
  1528. proc setup_my_chip @{chip_name flash_size ram_size@} @{
  1529. # basic initialization procedure ...
  1530. @}
  1531. proc init_targets @{@} @{
  1532. # initializes generic chip with 4kB of flash and 1kB of RAM
  1533. setup_my_chip MY_GENERIC_CHIP 4096 1024
  1534. @}
  1535. ### specific_file.cfg ###
  1536. source [find target/generic_file.cfg]
  1537. proc init_targets @{@} @{
  1538. # initializes specific chip with 128kB of flash and 64kB of RAM
  1539. setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
  1540. @}
  1541. @end example
  1542. The easiest way to convert ``linear'' config files to @code{init_targets} version is to
  1543. enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
  1544. For an example of this scheme see LPC2000 target config files.
  1545. The @code{init_boards} procedure is a similar concept concerning board config files
  1546. (@xref{theinitboardprocedure,,The init_board procedure}.)
  1547. @anchor{theinittargeteventsprocedure}
  1548. @subsection The init_target_events procedure
  1549. @cindex init_target_events procedure
  1550. A special procedure called @code{init_target_events} is run just after
  1551. @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
  1552. procedure}.) and before @code{init_board}
  1553. (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
  1554. to set up default target events for the targets that do not have those
  1555. events already assigned.
  1556. @subsection ARM Core Specific Hacks
  1557. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1558. special high speed download features - enable it.
  1559. If present, the MMU, the MPU and the CACHE should be disabled.
  1560. Some ARM cores are equipped with trace support, which permits
  1561. examination of the instruction and data bus activity. Trace
  1562. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1563. on one of the core's scan chains. The ETM emits voluminous data
  1564. through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
  1565. If you are using an external trace port,
  1566. configure it in your board config file.
  1567. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1568. configure it in your target config file.
  1569. @example
  1570. etm config $_TARGETNAME 16 normal full etb
  1571. etb config $_TARGETNAME $_CHIPNAME.etb
  1572. @end example
  1573. @subsection Internal Flash Configuration
  1574. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1575. @b{Never ever} in the ``target configuration file'' define any type of
  1576. flash that is external to the chip. (For example a BOOT flash on
  1577. Chip Select 0.) Such flash information goes in a board file - not
  1578. the TARGET (chip) file.
  1579. Examples:
  1580. @itemize @bullet
  1581. @item at91sam7x256 - has 256K flash YES enable it.
  1582. @item str912 - has flash internal YES enable it.
  1583. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1584. @item pxa270 - again - CS0 flash - it goes in the board file.
  1585. @end itemize
  1586. @anchor{translatingconfigurationfiles}
  1587. @section Translating Configuration Files
  1588. @cindex translation
  1589. If you have a configuration file for another hardware debugger
  1590. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1591. Lauterbach, Segger, Macraigor, etc.), translating
  1592. it into OpenOCD syntax is often quite straightforward. The most tricky
  1593. part of creating a configuration script is oftentimes the reset init
  1594. sequence where e.g. PLLs, DRAM and the like is set up.
  1595. One trick that you can use when translating is to write small
  1596. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1597. can avoid manual translation errors and make it easier to
  1598. convert other scripts later on.
  1599. Example of transforming quirky arguments to a simple search and
  1600. replace job:
  1601. @example
  1602. # Lauterbach syntax(?)
  1603. #
  1604. # Data.Set c15:0x042f %long 0x40000015
  1605. #
  1606. # OpenOCD syntax when using procedure below.
  1607. #
  1608. # setc15 0x01 0x00050078
  1609. proc setc15 @{regs value@} @{
  1610. global TARGETNAME
  1611. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1612. arm mcr 15 [expr ($regs>>12)&0x7] \
  1613. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1614. [expr ($regs>>8)&0x7] $value
  1615. @}
  1616. @end example
  1617. @node Daemon Configuration
  1618. @chapter Daemon Configuration
  1619. @cindex initialization
  1620. The commands here are commonly found in the openocd.cfg file and are
  1621. used to specify what TCP/IP ports are used, and how GDB should be
  1622. supported.
  1623. @anchor{configurationstage}
  1624. @section Configuration Stage
  1625. @cindex configuration stage
  1626. @cindex config command
  1627. When the OpenOCD server process starts up, it enters a
  1628. @emph{configuration stage} which is the only time that
  1629. certain commands, @emph{configuration commands}, may be issued.
  1630. Normally, configuration commands are only available
  1631. inside startup scripts.
  1632. In this manual, the definition of a configuration command is
  1633. presented as a @emph{Config Command}, not as a @emph{Command}
  1634. which may be issued interactively.
  1635. The runtime @command{help} command also highlights configuration
  1636. commands, and those which may be issued at any time.
  1637. Those configuration commands include declaration of TAPs,
  1638. flash banks,
  1639. the interface used for JTAG communication,
  1640. and other basic setup.
  1641. The server must leave the configuration stage before it
  1642. may access or activate TAPs.
  1643. After it leaves this stage, configuration commands may no
  1644. longer be issued.
  1645. @anchor{enteringtherunstage}
  1646. @section Entering the Run Stage
  1647. The first thing OpenOCD does after leaving the configuration
  1648. stage is to verify that it can talk to the scan chain
  1649. (list of TAPs) which has been configured.
  1650. It will warn if it doesn't find TAPs it expects to find,
  1651. or finds TAPs that aren't supposed to be there.
  1652. You should see no errors at this point.
  1653. If you see errors, resolve them by correcting the
  1654. commands you used to configure the server.
  1655. Common errors include using an initial JTAG speed that's too
  1656. fast, and not providing the right IDCODE values for the TAPs
  1657. on the scan chain.
  1658. Once OpenOCD has entered the run stage, a number of commands
  1659. become available.
  1660. A number of these relate to the debug targets you may have declared.
  1661. For example, the @command{mww} command will not be available until
  1662. a target has been successfuly instantiated.
  1663. If you want to use those commands, you may need to force
  1664. entry to the run stage.
  1665. @deffn {Config Command} init
  1666. This command terminates the configuration stage and
  1667. enters the run stage. This helps when you need to have
  1668. the startup scripts manage tasks such as resetting the target,
  1669. programming flash, etc. To reset the CPU upon startup, add "init" and
  1670. "reset" at the end of the config script or at the end of the OpenOCD
  1671. command line using the @option{-c} command line switch.
  1672. If this command does not appear in any startup/configuration file
  1673. OpenOCD executes the command for you after processing all
  1674. configuration files and/or command line options.
  1675. @b{NOTE:} This command normally occurs at or near the end of your
  1676. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1677. targets ready. For example: If your openocd.cfg file needs to
  1678. read/write memory on your target, @command{init} must occur before
  1679. the memory read/write commands. This includes @command{nand probe}.
  1680. @end deffn
  1681. @deffn {Overridable Procedure} jtag_init
  1682. This is invoked at server startup to verify that it can talk
  1683. to the scan chain (list of TAPs) which has been configured.
  1684. The default implementation first tries @command{jtag arp_init},
  1685. which uses only a lightweight JTAG reset before examining the
  1686. scan chain.
  1687. If that fails, it tries again, using a harder reset
  1688. from the overridable procedure @command{init_reset}.
  1689. Implementations must have verified the JTAG scan chain before
  1690. they return.
  1691. This is done by calling @command{jtag arp_init}
  1692. (or @command{jtag arp_init-reset}).
  1693. @end deffn
  1694. @anchor{tcpipports}
  1695. @section TCP/IP Ports
  1696. @cindex TCP port
  1697. @cindex server
  1698. @cindex port
  1699. @cindex security
  1700. The OpenOCD server accepts remote commands in several syntaxes.
  1701. Each syntax uses a different TCP/IP port, which you may specify
  1702. only during configuration (before those ports are opened).
  1703. For reasons including security, you may wish to prevent remote
  1704. access using one or more of these ports.
  1705. In such cases, just specify the relevant port number as zero.
  1706. If you disable all access through TCP/IP, you will need to
  1707. use the command line @option{-pipe} option.
  1708. @deffn {Command} gdb_port [number]
  1709. @cindex GDB server
  1710. Normally gdb listens to a TCP/IP port, but GDB can also
  1711. communicate via pipes(stdin/out or named pipes). The name
  1712. "gdb_port" stuck because it covers probably more than 90% of
  1713. the normal use cases.
  1714. No arguments reports GDB port. "pipe" means listen to stdin
  1715. output to stdout, an integer is base port number, "disable"
  1716. disables the gdb server.
  1717. When using "pipe", also use log_output to redirect the log
  1718. output to a file so as not to flood the stdin/out pipes.
  1719. The -p/--pipe option is deprecated and a warning is printed
  1720. as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
  1721. Any other string is interpreted as named pipe to listen to.
  1722. Output pipe is the same name as input pipe, but with 'o' appended,
  1723. e.g. /var/gdb, /var/gdbo.
  1724. The GDB port for the first target will be the base port, the
  1725. second target will listen on gdb_port + 1, and so on.
  1726. When not specified during the configuration stage,
  1727. the port @var{number} defaults to 3333.
  1728. @end deffn
  1729. @deffn {Command} tcl_port [number]
  1730. Specify or query the port used for a simplified RPC
  1731. connection that can be used by clients to issue TCL commands and get the
  1732. output from the Tcl engine.
  1733. Intended as a machine interface.
  1734. When not specified during the configuration stage,
  1735. the port @var{number} defaults to 6666.
  1736. @end deffn
  1737. @deffn {Command} telnet_port [number]
  1738. Specify or query the
  1739. port on which to listen for incoming telnet connections.
  1740. This port is intended for interaction with one human through TCL commands.
  1741. When not specified during the configuration stage,
  1742. the port @var{number} defaults to 4444.
  1743. When specified as zero, this port is not activated.
  1744. @end deffn
  1745. @anchor{gdbconfiguration}
  1746. @section GDB Configuration
  1747. @cindex GDB
  1748. @cindex GDB configuration
  1749. You can reconfigure some GDB behaviors if needed.
  1750. The ones listed here are static and global.
  1751. @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
  1752. @xref{targetevents,,Target Events}, about configuring target-specific event handling.
  1753. @anchor{gdbbreakpointoverride}
  1754. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1755. Force breakpoint type for gdb @command{break} commands.
  1756. This option supports GDB GUIs which don't
  1757. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1758. GDB behaviour is not sufficient. GDB normally uses hardware
  1759. breakpoints if the memory map has been set up for flash regions.
  1760. @end deffn
  1761. @anchor{gdbflashprogram}
  1762. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1763. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1764. vFlash packet is received.
  1765. The default behaviour is @option{enable}.
  1766. @end deffn
  1767. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1768. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1769. requested. GDB will then know when to set hardware breakpoints, and program flash
  1770. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1771. for flash programming to work.
  1772. Default behaviour is @option{enable}.
  1773. @xref{gdbflashprogram,,gdb_flash_program}.
  1774. @end deffn
  1775. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1776. Specifies whether data aborts cause an error to be reported
  1777. by GDB memory read packets.
  1778. The default behaviour is @option{disable};
  1779. use @option{enable} see these errors reported.
  1780. @end deffn
  1781. @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
  1782. Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
  1783. The default behaviour is @option{enable}.
  1784. @end deffn
  1785. @deffn {Command} gdb_save_tdesc
  1786. Saves the target descripton file to the local file system.
  1787. The file name is @i{target_name}.xml.
  1788. @end deffn
  1789. @anchor{eventpolling}
  1790. @section Event Polling
  1791. Hardware debuggers are parts of asynchronous systems,
  1792. where significant events can happen at any time.
  1793. The OpenOCD server needs to detect some of these events,
  1794. so it can report them to through TCL command line
  1795. or to GDB.
  1796. Examples of such events include:
  1797. @itemize
  1798. @item One of the targets can stop running ... maybe it triggers
  1799. a code breakpoint or data watchpoint, or halts itself.
  1800. @item Messages may be sent over ``debug message'' channels ... many
  1801. targets support such messages sent over JTAG,
  1802. for receipt by the person debugging or tools.
  1803. @item Loss of power ... some adapters can detect these events.
  1804. @item Resets not issued through JTAG ... such reset sources
  1805. can include button presses or other system hardware, sometimes
  1806. including the target itself (perhaps through a watchdog).
  1807. @item Debug instrumentation sometimes supports event triggering
  1808. such as ``trace buffer full'' (so it can quickly be emptied)
  1809. or other signals (to correlate with code behavior).
  1810. @end itemize
  1811. None of those events are signaled through standard JTAG signals.
  1812. However, most conventions for JTAG connectors include voltage
  1813. level and system reset (SRST) signal detection.
  1814. Some connectors also include instrumentation signals, which
  1815. can imply events when those signals are inputs.
  1816. In general, OpenOCD needs to periodically check for those events,
  1817. either by looking at the status of signals on the JTAG connector
  1818. or by sending synchronous ``tell me your status'' JTAG requests
  1819. to the various active targets.
  1820. There is a command to manage and monitor that polling,
  1821. which is normally done in the background.
  1822. @deffn Command poll [@option{on}|@option{off}]
  1823. Poll the current target for its current state.
  1824. (Also, @pxref{targetcurstate,,target curstate}.)
  1825. If that target is in debug mode, architecture
  1826. specific information about the current state is printed.
  1827. An optional parameter
  1828. allows background polling to be enabled and disabled.
  1829. You could use this from the TCL command shell, or
  1830. from GDB using @command{monitor poll} command.
  1831. Leave background polling enabled while you're using GDB.
  1832. @example
  1833. > poll
  1834. background polling: on
  1835. target state: halted
  1836. target halted in ARM state due to debug-request, \
  1837. current mode: Supervisor
  1838. cpsr: 0x800000d3 pc: 0x11081bfc
  1839. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1840. >
  1841. @end example
  1842. @end deffn
  1843. @node Debug Adapter Configuration
  1844. @chapter Debug Adapter Configuration
  1845. @cindex config file, interface
  1846. @cindex interface config file
  1847. Correctly installing OpenOCD includes making your operating system give
  1848. OpenOCD access to debug adapters. Once that has been done, Tcl commands
  1849. are used to select which one is used, and to configure how it is used.
  1850. @quotation Note
  1851. Because OpenOCD started out with a focus purely on JTAG, you may find
  1852. places where it wrongly presumes JTAG is the only transport protocol
  1853. in use. Be aware that recent versions of OpenOCD are removing that
  1854. limitation. JTAG remains more functional than most other transports.
  1855. Other transports do not support boundary scan operations, or may be
  1856. specific to a given chip vendor. Some might be usable only for
  1857. programming flash memory, instead of also for debugging.
  1858. @end quotation
  1859. Debug Adapters/Interfaces/Dongles are normally configured
  1860. through commands in an interface configuration
  1861. file which is sourced by your @file{openocd.cfg} file, or
  1862. through a command line @option{-f interface/....cfg} option.
  1863. @example
  1864. source [find interface/olimex-jtag-tiny.cfg]
  1865. @end example
  1866. These commands tell
  1867. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1868. A few cases are so simple that you only need to say what driver to use:
  1869. @example
  1870. # jlink interface
  1871. interface jlink
  1872. @end example
  1873. Most adapters need a bit more configuration than that.
  1874. @section Interface Configuration
  1875. The interface command tells OpenOCD what type of debug adapter you are
  1876. using. Depending on the type of adapter, you may need to use one or
  1877. more additional commands to further identify or configure the adapter.
  1878. @deffn {Config Command} {interface} name
  1879. Use the interface driver @var{name} to connect to the
  1880. target.
  1881. @end deffn
  1882. @deffn Command {interface_list}
  1883. List the debug adapter drivers that have been built into
  1884. the running copy of OpenOCD.
  1885. @end deffn
  1886. @deffn Command {interface transports} transport_name+
  1887. Specifies the transports supported by this debug adapter.
  1888. The adapter driver builds-in similar knowledge; use this only
  1889. when external configuration (such as jumpering) changes what
  1890. the hardware can support.
  1891. @end deffn
  1892. @deffn Command {adapter_name}
  1893. Returns the name of the debug adapter driver being used.
  1894. @end deffn
  1895. @section Interface Drivers
  1896. Each of the interface drivers listed here must be explicitly
  1897. enabled when OpenOCD is configured, in order to be made
  1898. available at run time.
  1899. @deffn {Interface Driver} {amt_jtagaccel}
  1900. Amontec Chameleon in its JTAG Accelerator configuration,
  1901. connected to a PC's EPP mode parallel port.
  1902. This defines some driver-specific commands:
  1903. @deffn {Config Command} {parport_port} number
  1904. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1905. the number of the @file{/dev/parport} device.
  1906. @end deffn
  1907. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  1908. Displays status of RTCK option.
  1909. Optionally sets that option first.
  1910. @end deffn
  1911. @end deffn
  1912. @deffn {Interface Driver} {arm-jtag-ew}
  1913. Olimex ARM-JTAG-EW USB adapter
  1914. This has one driver-specific command:
  1915. @deffn Command {armjtagew_info}
  1916. Logs some status
  1917. @end deffn
  1918. @end deffn
  1919. @deffn {Interface Driver} {at91rm9200}
  1920. Supports bitbanged JTAG from the local system,
  1921. presuming that system is an Atmel AT91rm9200
  1922. and a specific set of GPIOs is used.
  1923. @c command: at91rm9200_device NAME
  1924. @c chooses among list of bit configs ... only one option
  1925. @end deffn
  1926. @deffn {Interface Driver} {cmsis-dap}
  1927. ARM CMSIS-DAP compliant based adapter.
  1928. @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
  1929. The vendor ID and product ID of the CMSIS-DAP device. If not specified
  1930. the driver will attempt to auto detect the CMSIS-DAP device.
  1931. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1932. @example
  1933. cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
  1934. @end example
  1935. @end deffn
  1936. @deffn {Config Command} {cmsis_dap_serial} [serial]
  1937. Specifies the @var{serial} of the CMSIS-DAP device to use.
  1938. If not specified, serial numbers are not considered.
  1939. @end deffn
  1940. @deffn {Command} {cmsis-dap info}
  1941. Display various device information, like hardware version, firmware version, current bus status.
  1942. @end deffn
  1943. @end deffn
  1944. @deffn {Interface Driver} {dummy}
  1945. A dummy software-only driver for debugging.
  1946. @end deffn
  1947. @deffn {Interface Driver} {ep93xx}
  1948. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1949. @end deffn
  1950. @deffn {Interface Driver} {ft2232}
  1951. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  1952. Note that this driver has several flaws and the @command{ftdi} driver is
  1953. recommended as its replacement.
  1954. These interfaces have several commands, used to configure the driver
  1955. before initializing the JTAG scan chain:
  1956. @deffn {Config Command} {ft2232_device_desc} description
  1957. Provides the USB device description (the @emph{iProduct string})
  1958. of the FTDI FT2232 device. If not
  1959. specified, the FTDI default value is used. This setting is only valid
  1960. if compiled with FTD2XX support.
  1961. @end deffn
  1962. @deffn {Config Command} {ft2232_serial} serial-number
  1963. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  1964. in case the vendor provides unique IDs and more than one FT2232 device
  1965. is connected to the host.
  1966. If not specified, serial numbers are not considered.
  1967. (Note that USB serial numbers can be arbitrary Unicode strings,
  1968. and are not restricted to containing only decimal digits.)
  1969. @end deffn
  1970. @deffn {Config Command} {ft2232_layout} name
  1971. Each vendor's FT2232 device can use different GPIO signals
  1972. to control output-enables, reset signals, and LEDs.
  1973. Currently valid layout @var{name} values include:
  1974. @itemize @minus
  1975. @item @b{axm0432_jtag} Axiom AXM-0432
  1976. @item @b{comstick} Hitex STR9 comstick
  1977. @item @b{cortino} Hitex Cortino JTAG interface
  1978. @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
  1979. either for the local Cortex-M3 (SRST only)
  1980. or in a passthrough mode (neither SRST nor TRST)
  1981. This layout can not support the SWO trace mechanism, and should be
  1982. used only for older boards (before rev C).
  1983. @item @b{luminary_icdi} This layout should be used with most TI/Luminary
  1984. eval boards, including Rev C LM3S811 eval boards and the eponymous
  1985. ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
  1986. to debug some other target. It can support the SWO trace mechanism.
  1987. @item @b{flyswatter} Tin Can Tools Flyswatter
  1988. @item @b{icebear} ICEbear JTAG adapter from Section 5
  1989. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  1990. @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
  1991. @item @b{m5960} American Microsystems M5960
  1992. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  1993. @item @b{oocdlink} OOCDLink
  1994. @c oocdlink ~= jtagkey_prototype_v1
  1995. @item @b{redbee-econotag} Integrated with a Redbee development board.
  1996. @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
  1997. @item @b{sheevaplug} Marvell Sheevaplug development kit
  1998. @item @b{signalyzer} Xverve Signalyzer
  1999. @item @b{stm32stick} Hitex STM32 Performance Stick
  2000. @item @b{turtelizer2} egnite Software turtelizer2
  2001. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  2002. @end itemize
  2003. @end deffn
  2004. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  2005. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  2006. default values are used.
  2007. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2008. @example
  2009. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2010. @end example
  2011. @end deffn
  2012. @deffn {Config Command} {ft2232_latency} ms
  2013. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  2014. ft2232_read() fails to return the expected number of bytes. This can be caused by
  2015. USB communication delays and has proved hard to reproduce and debug. Setting the
  2016. FT2232 latency timer to a larger value increases delays for short USB packets but it
  2017. also reduces the risk of timeouts before receiving the expected number of bytes.
  2018. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  2019. @end deffn
  2020. @deffn {Config Command} {ft2232_channel} channel
  2021. Used to select the channel of the ft2232 chip to use (between 1 and 4).
  2022. The default value is 1.
  2023. @end deffn
  2024. For example, the interface config file for a
  2025. Turtelizer JTAG Adapter looks something like this:
  2026. @example
  2027. interface ft2232
  2028. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  2029. ft2232_layout turtelizer2
  2030. ft2232_vid_pid 0x0403 0xbdc8
  2031. @end example
  2032. @end deffn
  2033. @deffn {Interface Driver} {ftdi}
  2034. This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
  2035. Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
  2036. It is a complete rewrite to address a large number of problems with the ft2232
  2037. interface driver.
  2038. The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
  2039. bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
  2040. consistently faster than the ft2232 driver, sometimes several times faster.
  2041. A major improvement of this driver is that support for new FTDI based adapters
  2042. can be added competely through configuration files, without the need to patch
  2043. and rebuild OpenOCD.
  2044. The driver uses a signal abstraction to enable Tcl configuration files to
  2045. define outputs for one or several FTDI GPIO. These outputs can then be
  2046. controlled using the @command{ftdi_set_signal} command. Special signal names
  2047. are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
  2048. will be used for their customary purpose.
  2049. Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
  2050. be controlled differently. In order to support tristateable signals such as
  2051. nSRST, both a data GPIO and an output-enable GPIO can be specified for each
  2052. signal. The following output buffer configurations are supported:
  2053. @itemize @minus
  2054. @item Push-pull with one FTDI output as (non-)inverted data line
  2055. @item Open drain with one FTDI output as (non-)inverted output-enable
  2056. @item Tristate with one FTDI output as (non-)inverted data line and another
  2057. FTDI output as (non-)inverted output-enable
  2058. @item Unbuffered, using the FTDI GPIO as a tristate output directly by
  2059. switching data and direction as necessary
  2060. @end itemize
  2061. These interfaces have several commands, used to configure the driver
  2062. before initializing the JTAG scan chain:
  2063. @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
  2064. The vendor ID and product ID of the adapter. If not specified, the FTDI
  2065. default values are used.
  2066. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2067. @example
  2068. ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2069. @end example
  2070. @end deffn
  2071. @deffn {Config Command} {ftdi_device_desc} description
  2072. Provides the USB device description (the @emph{iProduct string})
  2073. of the adapter. If not specified, the device description is ignored
  2074. during device selection.
  2075. @end deffn
  2076. @deffn {Config Command} {ftdi_serial} serial-number
  2077. Specifies the @var{serial-number} of the adapter to use,
  2078. in case the vendor provides unique IDs and more than one adapter
  2079. is connected to the host.
  2080. If not specified, serial numbers are not considered.
  2081. (Note that USB serial numbers can be arbitrary Unicode strings,
  2082. and are not restricted to containing only decimal digits.)
  2083. @end deffn
  2084. @deffn {Config Command} {ftdi_channel} channel
  2085. Selects the channel of the FTDI device to use for MPSSE operations. Most
  2086. adapters use the default, channel 0, but there are exceptions.
  2087. @end deffn
  2088. @deffn {Config Command} {ftdi_layout_init} data direction
  2089. Specifies the initial values of the FTDI GPIO data and direction registers.
  2090. Each value is a 16-bit number corresponding to the concatenation of the high
  2091. and low FTDI GPIO registers. The values should be selected based on the
  2092. schematics of the adapter, such that all signals are set to safe levels with
  2093. minimal impact on the target system. Avoid floating inputs, conflicting outputs
  2094. and initially asserted reset signals.
  2095. @end deffn
  2096. @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
  2097. Creates a signal with the specified @var{name}, controlled by one or more FTDI
  2098. GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
  2099. register bitmasks to tell the driver the connection and type of the output
  2100. buffer driving the respective signal. @var{data_mask} is the bitmask for the
  2101. pin(s) connected to the data input of the output buffer. @option{-ndata} is
  2102. used with inverting data inputs and @option{-data} with non-inverting inputs.
  2103. The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
  2104. not-output-enable) input to the output buffer is connected.
  2105. Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
  2106. simple open-collector transistor driver would be specified with @option{-oe}
  2107. only. In that case the signal can only be set to drive low or to Hi-Z and the
  2108. driver will complain if the signal is set to drive high. Which means that if
  2109. it's a reset signal, @command{reset_config} must be specified as
  2110. @option{srst_open_drain}, not @option{srst_push_pull}.
  2111. A special case is provided when @option{-data} and @option{-oe} is set to the
  2112. same bitmask. Then the FTDI pin is considered being connected straight to the
  2113. target without any buffer. The FTDI pin is then switched between output and
  2114. input as necessary to provide the full set of low, high and Hi-Z
  2115. characteristics. In all other cases, the pins specified in a signal definition
  2116. are always driven by the FTDI.
  2117. If @option{-alias} or @option{-nalias} is used, the signal is created
  2118. identical (or with data inverted) to an already specified signal
  2119. @var{name}.
  2120. @end deffn
  2121. @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
  2122. Set a previously defined signal to the specified level.
  2123. @itemize @minus
  2124. @item @option{0}, drive low
  2125. @item @option{1}, drive high
  2126. @item @option{z}, set to high-impedance
  2127. @end itemize
  2128. @end deffn
  2129. For example adapter definitions, see the configuration files shipped in the
  2130. @file{interface/ftdi} directory.
  2131. @end deffn
  2132. @deffn {Interface Driver} {remote_bitbang}
  2133. Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
  2134. with a remote process and sends ASCII encoded bitbang requests to that process
  2135. instead of directly driving JTAG.
  2136. The remote_bitbang driver is useful for debugging software running on
  2137. processors which are being simulated.
  2138. @deffn {Config Command} {remote_bitbang_port} number
  2139. Specifies the TCP port of the remote process to connect to or 0 to use UNIX
  2140. sockets instead of TCP.
  2141. @end deffn
  2142. @deffn {Config Command} {remote_bitbang_host} hostname
  2143. Specifies the hostname of the remote process to connect to using TCP, or the
  2144. name of the UNIX socket to use if remote_bitbang_port is 0.
  2145. @end deffn
  2146. For example, to connect remotely via TCP to the host foobar you might have
  2147. something like:
  2148. @example
  2149. interface remote_bitbang
  2150. remote_bitbang_port 3335
  2151. remote_bitbang_host foobar
  2152. @end example
  2153. To connect to another process running locally via UNIX sockets with socket
  2154. named mysocket:
  2155. @example
  2156. interface remote_bitbang
  2157. remote_bitbang_port 0
  2158. remote_bitbang_host mysocket
  2159. @end example
  2160. @end deffn
  2161. @deffn {Interface Driver} {usb_blaster}
  2162. USB JTAG/USB-Blaster compatibles over one of the userspace libraries
  2163. for FTDI chips. These interfaces have several commands, used to
  2164. configure the driver before initializing the JTAG scan chain:
  2165. @deffn {Config Command} {usb_blaster_device_desc} description
  2166. Provides the USB device description (the @emph{iProduct string})
  2167. of the FTDI FT245 device. If not
  2168. specified, the FTDI default value is used. This setting is only valid
  2169. if compiled with FTD2XX support.
  2170. @end deffn
  2171. @deffn {Config Command} {usb_blaster_vid_pid} vid pid
  2172. The vendor ID and product ID of the FTDI FT245 device. If not specified,
  2173. default values are used.
  2174. Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
  2175. Altera USB-Blaster (default):
  2176. @example
  2177. usb_blaster_vid_pid 0x09FB 0x6001
  2178. @end example
  2179. The following VID/PID is for Kolja Waschk's USB JTAG:
  2180. @example
  2181. usb_blaster_vid_pid 0x16C0 0x06AD
  2182. @end example
  2183. @end deffn
  2184. @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
  2185. Sets the state or function of the unused GPIO pins on USB-Blasters
  2186. (pins 6 and 8 on the female JTAG header). These pins can be used as
  2187. SRST and/or TRST provided the appropriate connections are made on the
  2188. target board.
  2189. For example, to use pin 6 as SRST:
  2190. @example
  2191. usb_blaster_pin pin6 s
  2192. reset_config srst_only
  2193. @end example
  2194. @end deffn
  2195. @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ftd2xx}|@option{ublast2})
  2196. Chooses the low level access method for the adapter. If not specified,
  2197. @option{ftdi} is selected unless it wasn't enabled during the
  2198. configure stage. USB-Blaster II needs @option{ublast2}.
  2199. @end deffn
  2200. @deffn {Command} {usb_blaster_firmware} @var{path}
  2201. This command specifies @var{path} to access USB-Blaster II firmware
  2202. image. To be used with USB-Blaster II only.
  2203. @end deffn
  2204. @end deffn
  2205. @deffn {Interface Driver} {gw16012}
  2206. Gateworks GW16012 JTAG programmer.
  2207. This has one driver-specific command:
  2208. @deffn {Config Command} {parport_port} [port_number]
  2209. Display either the address of the I/O port
  2210. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2211. If a parameter is provided, first switch to use that port.
  2212. This is a write-once setting.
  2213. @end deffn
  2214. @end deffn
  2215. @deffn {Interface Driver} {jlink}
  2216. Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
  2217. @quotation Compatibility Note
  2218. Segger released many firmware versions for the many harware versions they
  2219. produced. OpenOCD was extensively tested and intended to run on all of them,
  2220. but some combinations were reported as incompatible. As a general
  2221. recommendation, it is advisable to use the latest firmware version
  2222. available for each hardware version. However the current V8 is a moving
  2223. target, and Segger firmware versions released after the OpenOCD was
  2224. released may not be compatible. In such cases it is recommended to
  2225. revert to the last known functional version. For 0.5.0, this is from
  2226. "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
  2227. version is from "May 3 2012 18:36:22", packed with 4.46f.
  2228. @end quotation
  2229. @deffn {Command} {jlink caps}
  2230. Display the device firmware capabilities.
  2231. @end deffn
  2232. @deffn {Command} {jlink info}
  2233. Display various device information, like hardware version, firmware version, current bus status.
  2234. @end deffn
  2235. @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
  2236. Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
  2237. @end deffn
  2238. @deffn {Command} {jlink config}
  2239. Display the J-Link configuration.
  2240. @end deffn
  2241. @deffn {Command} {jlink config kickstart} [val]
  2242. Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
  2243. @end deffn
  2244. @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
  2245. Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
  2246. @end deffn
  2247. @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
  2248. Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
  2249. E the bit of the subnet mask and
  2250. F.G.H.I the subnet mask. Without arguments, show the IP configuration.
  2251. @end deffn
  2252. @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
  2253. Set the USB address; this will also change the product id. Without argument, show the USB address.
  2254. @end deffn
  2255. @deffn {Command} {jlink config reset}
  2256. Reset the current configuration.
  2257. @end deffn
  2258. @deffn {Command} {jlink config save}
  2259. Save the current configuration to the internal persistent storage.
  2260. @end deffn
  2261. @deffn {Config} {jlink pid} val
  2262. Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
  2263. @end deffn
  2264. @deffn {Config} {jlink serial} serial-number
  2265. Set the @var{serial-number} of the interface, in case more than one adapter is connected to the host.
  2266. If not specified, serial numbers are not considered.
  2267. Note that there may be leading zeros in the @var{serial-number} string
  2268. that will not show in the Segger software, but must be specified here.
  2269. Debug level 3 output contains serial numbers if there is a mismatch.
  2270. As a configuration command, it can be used only before 'init'.
  2271. @end deffn
  2272. @end deffn
  2273. @deffn {Interface Driver} {parport}
  2274. Supports PC parallel port bit-banging cables:
  2275. Wigglers, PLD download cable, and more.
  2276. These interfaces have several commands, used to configure the driver
  2277. before initializing the JTAG scan chain:
  2278. @deffn {Config Command} {parport_cable} name
  2279. Set the layout of the parallel port cable used to connect to the target.
  2280. This is a write-once setting.
  2281. Currently valid cable @var{name} values include:
  2282. @itemize @minus
  2283. @item @b{altium} Altium Universal JTAG cable.
  2284. @item @b{arm-jtag} Same as original wiggler except SRST and
  2285. TRST connections reversed and TRST is also inverted.
  2286. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  2287. in configuration mode. This is only used to
  2288. program the Chameleon itself, not a connected target.
  2289. @item @b{dlc5} The Xilinx Parallel cable III.
  2290. @item @b{flashlink} The ST Parallel cable.
  2291. @item @b{lattice} Lattice ispDOWNLOAD Cable
  2292. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  2293. some versions of
  2294. Amontec's Chameleon Programmer. The new version available from
  2295. the website uses the original Wiggler layout ('@var{wiggler}')
  2296. @item @b{triton} The parallel port adapter found on the
  2297. ``Karo Triton 1 Development Board''.
  2298. This is also the layout used by the HollyGates design
  2299. (see @uref{}).
  2300. @item @b{wiggler} The original Wiggler layout, also supported by
  2301. several clones, such as the Olimex ARM-JTAG
  2302. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  2303. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  2304. @end itemize
  2305. @end deffn
  2306. @deffn {Config Command} {parport_port} [port_number]
  2307. Display either the address of the I/O port
  2308. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2309. If a parameter is provided, first switch to use that port.
  2310. This is a write-once setting.
  2311. When using PPDEV to access the parallel port, use the number of the parallel port:
  2312. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  2313. you may encounter a problem.
  2314. @end deffn
  2315. @deffn Command {parport_toggling_time} [nanoseconds]
  2316. Displays how many nanoseconds the hardware needs to toggle TCK;
  2317. the parport driver uses this value to obey the
  2318. @command{adapter_khz} configuration.
  2319. When the optional @var{nanoseconds} parameter is given,
  2320. that setting is changed before displaying the current value.
  2321. The default setting should work reasonably well on commodity PC hardware.
  2322. However, you may want to calibrate for your specific hardware.
  2323. @quotation Tip
  2324. To measure the toggling time with a logic analyzer or a digital storage
  2325. oscilloscope, follow the procedure below:
  2326. @example
  2327. > parport_toggling_time 1000
  2328. > adapter_khz 500
  2329. @end example
  2330. This sets the maximum JTAG clock speed of the hardware, but
  2331. the actual speed probably deviates from the requested 500 kHz.
  2332. Now, measure the time between the two closest spaced TCK transitions.
  2333. You can use @command{runtest 1000} or something similar to generate a
  2334. large set of samples.
  2335. Update the setting to match your measurement:
  2336. @example
  2337. > parport_toggling_time <measured nanoseconds>
  2338. @end example
  2339. Now the clock speed will be a better match for @command{adapter_khz rate}
  2340. commands given in OpenOCD scripts and event handlers.
  2341. You can do something similar with many digital multimeters, but note
  2342. that you'll probably need to run the clock continuously for several
  2343. seconds before it decides what clock rate to show. Adjust the
  2344. toggling time up or down until the measured clock rate is a good
  2345. match for the adapter_khz rate you specified; be conservative.
  2346. @end quotation
  2347. @end deffn
  2348. @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
  2349. This will configure the parallel driver to write a known
  2350. cable-specific value to the parallel interface on exiting OpenOCD.
  2351. @end deffn
  2352. For example, the interface configuration file for a
  2353. classic ``Wiggler'' cable on LPT2 might look something like this:
  2354. @example
  2355. interface parport
  2356. parport_port 0x278
  2357. parport_cable wiggler
  2358. @end example
  2359. @end deffn
  2360. @deffn {Interface Driver} {presto}
  2361. ASIX PRESTO USB JTAG programmer.
  2362. @deffn {Config Command} {presto_serial} serial_string
  2363. Configures the USB serial number of the Presto device to use.
  2364. @end deffn
  2365. @end deffn
  2366. @deffn {Interface Driver} {rlink}
  2367. Raisonance RLink USB adapter
  2368. @end deffn
  2369. @deffn {Interface Driver} {usbprog}
  2370. usbprog is a freely programmable USB adapter.
  2371. @end deffn
  2372. @deffn {Interface Driver} {vsllink}
  2373. vsllink is part of Versaloon which is a versatile USB programmer.
  2374. @quotation Note
  2375. This defines quite a few driver-specific commands,
  2376. which are not currently documented here.
  2377. @end quotation
  2378. @end deffn
  2379. @anchor{hla_interface}
  2380. @deffn {Interface Driver} {hla}
  2381. This is a driver that supports multiple High Level Adapters.
  2382. This type of adapter does not expose some of the lower level api's
  2383. that OpenOCD would normally use to access the target.
  2384. Currently supported adapters include the ST STLINK and TI ICDI.
  2385. STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
  2386. versions of firmware where serial number is reset after first use. Suggest
  2387. using ST firmware update utility to upgrade STLINK firmware even if current
  2388. version reported is V2.J21.S4.
  2389. @deffn {Config Command} {hla_device_desc} description
  2390. Currently Not Supported.
  2391. @end deffn
  2392. @deffn {Config Command} {hla_serial} serial
  2393. Specifies the serial number of the adapter.
  2394. @end deffn
  2395. @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
  2396. Specifies the adapter layout to use.
  2397. @end deffn
  2398. @deffn {Config Command} {hla_vid_pid} vid pid
  2399. The vendor ID and product ID of the device.
  2400. @end deffn
  2401. @deffn {Command} {hla_command} command
  2402. Execute a custom adapter-specific command. The @var{command} string is
  2403. passed as is to the underlying adapter layout handler.
  2404. @end deffn
  2405. @end deffn
  2406. @deffn {Interface Driver} {opendous}
  2407. opendous-jtag is a freely programmable USB adapter.
  2408. @end deffn
  2409. @deffn {Interface Driver} {ulink}
  2410. This is the Keil ULINK v1 JTAG debugger.
  2411. @end deffn
  2412. @deffn {Interface Driver} {ZY1000}
  2413. This is the Zylin ZY1000 JTAG debugger.
  2414. @end deffn
  2415. @quotation Note
  2416. This defines some driver-specific commands,
  2417. which are not currently documented here.
  2418. @end quotation
  2419. @deffn Command power [@option{on}|@option{off}]
  2420. Turn power switch to target on/off.
  2421. No arguments: print status.
  2422. @end deffn
  2423. @deffn {Interface Driver} {bcm2835gpio}
  2424. This SoC is present in Raspberry Pi which is a cheap single-board computer
  2425. exposing some GPIOs on its expansion header.
  2426. The driver accesses memory-mapped GPIO peripheral registers directly
  2427. for maximum performance, but the only possible race condition is for
  2428. the pins' modes/muxing (which is highly unlikely), so it should be
  2429. able to coexist nicely with both sysfs bitbanging and various
  2430. peripherals' kernel drivers. The driver restores the previous
  2431. configuration on exit.
  2432. See @file{interface/raspberrypi-native.cfg} for a sample config and
  2433. pinout.
  2434. @end deffn
  2435. @section Transport Configuration
  2436. @cindex Transport
  2437. As noted earlier, depending on the version of OpenOCD you use,
  2438. and the debug adapter you are using,
  2439. several transports may be available to
  2440. communicate with debug targets (or perhaps to program flash memory).
  2441. @deffn Command {transport list}
  2442. displays the names of the transports supported by this
  2443. version of OpenOCD.
  2444. @end deffn
  2445. @deffn Command {transport select} @option{transport_name}
  2446. Select which of the supported transports to use in this OpenOCD session.
  2447. When invoked with @option{transport_name}, attempts to select the named
  2448. transport. The transport must be supported by the debug adapter
  2449. hardware and by the version of OpenOCD you are using (including the
  2450. adapter's driver).
  2451. If no transport has been selected and no @option{transport_name} is
  2452. provided, @command{transport select} auto-selects the first transport
  2453. supported by the debug adapter.
  2454. @command{transport select} always returns the name of the session's selected
  2455. transport, if any.
  2456. @end deffn
  2457. @subsection JTAG Transport
  2458. @cindex JTAG
  2459. JTAG is the original transport supported by OpenOCD, and most
  2460. of the OpenOCD commands support it.
  2461. JTAG transports expose a chain of one or more Test Access Points (TAPs),
  2462. each of which must be explicitly declared.
  2463. JTAG supports both debugging and boundary scan testing.
  2464. Flash programming support is built on top of debug support.
  2465. JTAG transport is selected with the command @command{transport select
  2466. jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
  2467. driver}, in which case the command is @command{transport select
  2468. hla_jtag}.
  2469. @subsection SWD Transport
  2470. @cindex SWD
  2471. @cindex Serial Wire Debug
  2472. SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
  2473. Debug Access Point (DAP, which must be explicitly declared.
  2474. (SWD uses fewer signal wires than JTAG.)
  2475. SWD is debug-oriented, and does not support boundary scan testing.
  2476. Flash programming support is built on top of debug support.
  2477. (Some processors support both JTAG and SWD.)
  2478. SWD transport is selected with the command @command{transport select
  2479. swd}. Unless your adapter uses @ref{hla_interface,the hla interface
  2480. driver}, in which case the command is @command{transport select
  2481. hla_swd}.
  2482. @deffn Command {swd newdap} ...
  2483. Declares a single DAP which uses SWD transport.
  2484. Parameters are currently the same as "jtag newtap" but this is
  2485. expected to change.
  2486. @end deffn
  2487. @deffn Command {swd wcr trn prescale}
  2488. Updates TRN (turnaraound delay) and prescaling.fields of the
  2489. Wire Control Register (WCR).
  2490. No parameters: displays current settings.
  2491. @end deffn
  2492. @subsection SPI Transport
  2493. @cindex SPI
  2494. @cindex Serial Peripheral Interface
  2495. The Serial Peripheral Interface (SPI) is a general purpose transport
  2496. which uses four wire signaling. Some processors use it as part of a
  2497. solution for flash programming.
  2498. @anchor{jtagspeed}
  2499. @section JTAG Speed
  2500. JTAG clock setup is part of system setup.
  2501. It @emph{does not belong with interface setup} since any interface
  2502. only knows a few of the constraints for the JTAG clock speed.
  2503. Sometimes the JTAG speed is
  2504. changed during the target initialization process: (1) slow at
  2505. reset, (2) program the CPU clocks, (3) run fast.
  2506. Both the "slow" and "fast" clock rates are functions of the
  2507. oscillators used, the chip, the board design, and sometimes
  2508. power management software that may be active.
  2509. The speed used during reset, and the scan chain verification which
  2510. follows reset, can be adjusted using a @code{reset-start}
  2511. target event handler.
  2512. It can then be reconfigured to a faster speed by a
  2513. @code{reset-init} target event handler after it reprograms those
  2514. CPU clocks, or manually (if something else, such as a boot loader,
  2515. sets up those clocks).
  2516. @xref{targetevents,,Target Events}.
  2517. When the initial low JTAG speed is a chip characteristic, perhaps
  2518. because of a required oscillator speed, provide such a handler
  2519. in the target config file.
  2520. When that speed is a function of a board-specific characteristic
  2521. such as which speed oscillator is used, it belongs in the board
  2522. config file instead.
  2523. In both cases it's safest to also set the initial JTAG clock rate
  2524. to that same slow speed, so that OpenOCD never starts up using a
  2525. clock speed that's faster than the scan chain can support.
  2526. @example
  2527. jtag_rclk 3000
  2528. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  2529. @end example
  2530. If your system supports adaptive clocking (RTCK), configuring
  2531. JTAG to use that is probably the most robust approach.
  2532. However, it introduces delays to synchronize clocks; so it
  2533. may not be the fastest solution.
  2534. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  2535. instead of @command{adapter_khz}, but only for (ARM) cores and boards
  2536. which support adaptive clocking.
  2537. @deffn {Command} adapter_khz max_speed_kHz
  2538. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  2539. JTAG interfaces usually support a limited number of
  2540. speeds. The speed actually used won't be faster
  2541. than the speed specified.
  2542. Chip data sheets generally include a top JTAG clock rate.
  2543. The actual rate is often a function of a CPU core clock,
  2544. and is normally less than that peak rate.
  2545. For example, most ARM cores accept at most one sixth of the CPU clock.
  2546. Speed 0 (khz) selects RTCK method.
  2547. @xref{faqrtck,,FAQ RTCK}.
  2548. If your system uses RTCK, you won't need to change the
  2549. JTAG clocking after setup.
  2550. Not all interfaces, boards, or targets support ``rtck''.
  2551. If the interface device can not
  2552. support it, an error is returned when you try to use RTCK.
  2553. @end deffn
  2554. @defun jtag_rclk fallback_speed_kHz
  2555. @cindex adaptive clocking
  2556. @cindex RTCK
  2557. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  2558. If that fails (maybe the interface, board, or target doesn't
  2559. support it), falls back to the specified frequency.
  2560. @example
  2561. # Fall back to 3mhz if RTCK is not supported
  2562. jtag_rclk 3000
  2563. @end example
  2564. @end defun
  2565. @node Reset Configuration
  2566. @chapter Reset Configuration
  2567. @cindex Reset Configuration
  2568. Every system configuration may require a different reset
  2569. configuration. This can also be quite confusing.
  2570. Resets also interact with @var{reset-init} event handlers,
  2571. which do things like setting up clocks and DRAM, and
  2572. JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
  2573. They can also interact with JTAG routers.
  2574. Please see the various board files for examples.
  2575. @quotation Note
  2576. To maintainers and integrators:
  2577. Reset configuration touches several things at once.
  2578. Normally the board configuration file
  2579. should define it and assume that the JTAG adapter supports
  2580. everything that's wired up to the board's JTAG connector.
  2581. However, the target configuration file could also make note
  2582. of something the silicon vendor has done inside the chip,
  2583. which will be true for most (or all) boards using that chip.
  2584. And when the JTAG adapter doesn't support everything, the
  2585. user configuration file will need to override parts of
  2586. the reset configuration provided by other files.
  2587. @end quotation
  2588. @section Types of Reset
  2589. There are many kinds of reset possible through JTAG, but
  2590. they may not all work with a given board and adapter.
  2591. That's part of why reset configuration can be error prone.
  2592. @itemize @bullet
  2593. @item
  2594. @emph{System Reset} ... the @emph{SRST} hardware signal
  2595. resets all chips connected to the JTAG adapter, such as processors,
  2596. power management chips, and I/O controllers. Normally resets triggered
  2597. with this signal behave exactly like pressing a RESET button.
  2598. @item
  2599. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  2600. just the TAP controllers connected to the JTAG adapter.
  2601. Such resets should not be visible to the rest of the system; resetting a
  2602. device's TAP controller just puts that controller into a known state.
  2603. @item
  2604. @emph{Emulation Reset} ... many devices can be reset through JTAG
  2605. commands. These resets are often distinguishable from system
  2606. resets, either explicitly (a "reset reason" register says so)
  2607. or implicitly (not all parts of the chip get reset).
  2608. @item
  2609. @emph{Other Resets} ... system-on-chip devices often support
  2610. several other types of reset.
  2611. You may need to arrange that a watchdog timer stops
  2612. while debugging, preventing a watchdog reset.
  2613. There may be individual module resets.
  2614. @end itemize
  2615. In the best case, OpenOCD can hold SRST, then reset
  2616. the TAPs via TRST and send commands through JTAG to halt the
  2617. CPU at the reset vector before the 1st instruction is executed.
  2618. Then when it finally releases the SRST signal, the system is
  2619. halted under debugger control before any code has executed.
  2620. This is the behavior required to support the @command{reset halt}
  2621. and @command{reset init} commands; after @command{reset init} a
  2622. board-specific script might do things like setting up DRAM.
  2623. (@xref{resetcommand,,Reset Command}.)
  2624. @anchor{srstandtrstissues}
  2625. @section SRST and TRST Issues
  2626. Because SRST and TRST are hardware signals, they can have a
  2627. variety of system-specific constraints. Some of the most
  2628. common issues are:
  2629. @itemize @bullet
  2630. @item @emph{Signal not available} ... Some boards don't wire
  2631. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  2632. support such signals even if they are wired up.
  2633. Use the @command{reset_config} @var{signals} options to say
  2634. when either of those signals is not connected.
  2635. When SRST is not available, your code might not be able to rely
  2636. on controllers having been fully reset during code startup.
  2637. Missing TRST is not a problem, since JTAG-level resets can
  2638. be triggered using with TMS signaling.
  2639. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  2640. adapter will connect SRST to TRST, instead of keeping them separate.
  2641. Use the @command{reset_config} @var{combination} options to say
  2642. when those signals aren't properly independent.
  2643. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  2644. delay circuit, reset supervisor, or on-chip features can extend
  2645. the effect of a JTAG adapter's reset for some time after the adapter
  2646. stops issuing the reset. For example, there may be chip or board
  2647. requirements that all reset pulses last for at least a
  2648. certain amount of time; and reset buttons commonly have
  2649. hardware debouncing.
  2650. Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
  2651. commands to say when extra delays are needed.
  2652. @item @emph{Drive type} ... Reset lines often have a pullup
  2653. resistor, letting the JTAG interface treat them as open-drain
  2654. signals. But that's not a requirement, so the adapter may need
  2655. to use push/pull output drivers.
  2656. Also, with weak pullups it may be advisable to drive
  2657. signals to both levels (push/pull) to minimize rise times.
  2658. Use the @command{reset_config} @var{trst_type} and
  2659. @var{srst_type} parameters to say how to drive reset signals.
  2660. @item @emph{Special initialization} ... Targets sometimes need
  2661. special JTAG initialization sequences to handle chip-specific
  2662. issues (not limited to errata).
  2663. For example, certain JTAG commands might need to be issued while
  2664. the system as a whole is in a reset state (SRST active)
  2665. but the JTAG scan chain is usable (TRST inactive).
  2666. Many systems treat combined assertion of SRST and TRST as a
  2667. trigger for a harder reset than SRST alone.
  2668. Such custom reset handling is discussed later in this chapter.
  2669. @end itemize
  2670. There can also be other issues.
  2671. Some devices don't fully conform to the JTAG specifications.
  2672. Trivial system-specific differences are common, such as
  2673. SRST and TRST using slightly different names.
  2674. There are also vendors who distribute key JTAG documentation for
  2675. their chips only to developers who have signed a Non-Disclosure
  2676. Agreement (NDA).
  2677. Sometimes there are chip-specific extensions like a requirement to use
  2678. the normally-optional TRST signal (precluding use of JTAG adapters which
  2679. don't pass TRST through), or needing extra steps to complete a TAP reset.
  2680. In short, SRST and especially TRST handling may be very finicky,
  2681. needing to cope with both architecture and board specific constraints.
  2682. @section Commands for Handling Resets
  2683. @deffn {Command} adapter_nsrst_assert_width milliseconds
  2684. Minimum amount of time (in milliseconds) OpenOCD should wait
  2685. after asserting nSRST (active-low system reset) before
  2686. allowing it to be deasserted.
  2687. @end deffn
  2688. @deffn {Command} adapter_nsrst_delay milliseconds
  2689. How long (in milliseconds) OpenOCD should wait after deasserting
  2690. nSRST (active-low system reset) before starting new JTAG operations.
  2691. When a board has a reset button connected to SRST line it will
  2692. probably have hardware debouncing, implying you should use this.
  2693. @end deffn
  2694. @deffn {Command} jtag_ntrst_assert_width milliseconds
  2695. Minimum amount of time (in milliseconds) OpenOCD should wait
  2696. after asserting nTRST (active-low JTAG TAP reset) before
  2697. allowing it to be deasserted.
  2698. @end deffn
  2699. @deffn {Command} jtag_ntrst_delay milliseconds
  2700. How long (in milliseconds) OpenOCD should wait after deasserting
  2701. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  2702. @end deffn
  2703. @deffn {Command} reset_config mode_flag ...
  2704. This command displays or modifies the reset configuration
  2705. of your combination of JTAG board and target in target
  2706. configuration scripts.
  2707. Information earlier in this section describes the kind of problems
  2708. the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
  2709. As a rule this command belongs only in board config files,
  2710. describing issues like @emph{board doesn't connect TRST};
  2711. or in user config files, addressing limitations derived
  2712. from a particular combination of interface and board.
  2713. (An unlikely example would be using a TRST-only adapter
  2714. with a board that only wires up SRST.)
  2715. The @var{mode_flag} options can be specified in any order, but only one
  2716. of each type -- @var{signals}, @var{combination}, @var{gates},
  2717. @var{trst_type}, @var{srst_type} and @var{connect_type}
  2718. -- may be specified at a time.
  2719. If you don't provide a new value for a given type, its previous
  2720. value (perhaps the default) is unchanged.
  2721. For example, this means that you don't need to say anything at all about
  2722. TRST just to declare that if the JTAG adapter should want to drive SRST,
  2723. it must explicitly be driven high (@option{srst_push_pull}).
  2724. @itemize
  2725. @item
  2726. @var{signals} can specify which of the reset signals are connected.
  2727. For example, If the JTAG interface provides SRST, but the board doesn't
  2728. connect that signal properly, then OpenOCD can't use it.
  2729. Possible values are @option{none} (the default), @option{trst_only},
  2730. @option{srst_only} and @option{trst_and_srst}.
  2731. @quotation Tip
  2732. If your board provides SRST and/or TRST through the JTAG connector,
  2733. you must declare that so those signals can be used.
  2734. @end quotation
  2735. @item
  2736. The @var{combination} is an optional value specifying broken reset
  2737. signal implementations.
  2738. The default behaviour if no option given is @option{separate},
  2739. indicating everything behaves normally.
  2740. @option{srst_pulls_trst} states that the
  2741. test logic is reset together with the reset of the system (e.g. NXP
  2742. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  2743. the system is reset together with the test logic (only hypothetical, I
  2744. haven't seen hardware with such a bug, and can be worked around).
  2745. @option{combined} implies both @option{srst_pulls_trst} and
  2746. @option{trst_pulls_srst}.
  2747. @item
  2748. The @var{gates} tokens control flags that describe some cases where
  2749. JTAG may be unvailable during reset.
  2750. @option{srst_gates_jtag} (default)
  2751. indicates that asserting SRST gates the
  2752. JTAG clock. This means that no communication can happen on JTAG
  2753. while SRST is asserted.
  2754. Its converse is @option{srst_nogate}, indicating that JTAG commands
  2755. can safely be issued while SRST is active.
  2756. @item
  2757. The @var{connect_type} tokens control flags that describe some cases where
  2758. SRST is asserted while connecting to the target. @option{srst_nogate}
  2759. is required to use this option.
  2760. @option{connect_deassert_srst} (default)
  2761. indicates that SRST will not be asserted while connecting to the target.
  2762. Its converse is @option{connect_assert_srst}, indicating that SRST will
  2763. be asserted before any target connection.
  2764. Only some targets support this feature, STM32 and STR9 are examples.
  2765. This feature is useful if you are unable to connect to your target due
  2766. to incorrect options byte config or illegal program execution.
  2767. @end itemize
  2768. The optional @var{trst_type} and @var{srst_type} parameters allow the
  2769. driver mode of each reset line to be specified. These values only affect
  2770. JTAG interfaces with support for different driver modes, like the Amontec
  2771. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  2772. relevant signal (TRST or SRST) is not connected.
  2773. @itemize
  2774. @item
  2775. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  2776. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  2777. Most boards connect this signal to a pulldown, so the JTAG TAPs
  2778. never leave reset unless they are hooked up to a JTAG adapter.
  2779. @item
  2780. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  2781. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  2782. Most boards connect this signal to a pullup, and allow the
  2783. signal to be pulled low by various events including system
  2784. powerup and pressing a reset button.
  2785. @end itemize
  2786. @end deffn
  2787. @section Custom Reset Handling
  2788. @cindex events
  2789. OpenOCD has several ways to help support the various reset
  2790. mechanisms provided by chip and board vendors.
  2791. The commands shown in the previous section give standard parameters.
  2792. There are also @emph{event handlers} associated with TAPs or Targets.
  2793. Those handlers are Tcl procedures you can provide, which are invoked
  2794. at particular points in the reset sequence.
  2795. @emph{When SRST is not an option} you must set
  2796. up a @code{reset-assert} event handler for your target.
  2797. For example, some JTAG adapters don't include the SRST signal;
  2798. and some boards have multiple targets, and you won't always
  2799. want to reset everything at once.
  2800. After configuring those mechanisms, you might still
  2801. find your board doesn't start up or reset correctly.
  2802. For example, maybe it needs a slightly different sequence
  2803. of SRST and/or TRST manipulations, because of quirks that
  2804. the @command{reset_config} mechanism doesn't address;
  2805. or asserting both might trigger a stronger reset, which
  2806. needs special attention.
  2807. Experiment with lower level operations, such as @command{jtag_reset}
  2808. and the @command{jtag arp_*} operations shown here,
  2809. to find a sequence of operations that works.
  2810. @xref{JTAG Commands}.
  2811. When you find a working sequence, it can be used to override
  2812. @command{jtag_init}, which fires during OpenOCD startup
  2813. (@pxref{configurationstage,,Configuration Stage});
  2814. or @command{init_reset}, which fires during reset processing.
  2815. You might also want to provide some project-specific reset
  2816. schemes. For example, on a multi-target board the standard
  2817. @command{reset} command would reset all targets, but you
  2818. may need the ability to reset only one target at time and
  2819. thus want to avoid using the board-wide SRST signal.
  2820. @deffn {Overridable Procedure} init_reset mode
  2821. This is invoked near the beginning of the @command{reset} command,
  2822. usually to provide as much of a cold (power-up) reset as practical.
  2823. By default it is also invoked from @command{jtag_init} if
  2824. the scan chain does not respond to pure JTAG operations.
  2825. The @var{mode} parameter is the parameter given to the
  2826. low level reset command (@option{halt},
  2827. @option{init}, or @option{run}), @option{setup},
  2828. or potentially some other value.
  2829. The default implementation just invokes @command{jtag arp_init-reset}.
  2830. Replacements will normally build on low level JTAG
  2831. operations such as @command{jtag_reset}.
  2832. Operations here must not address individual TAPs
  2833. (or their associated targets)
  2834. until the JTAG scan chain has first been verified to work.
  2835. Implementations must have verified the JTAG scan chain before
  2836. they return.
  2837. This is done by calling @command{jtag arp_init}
  2838. (or @command{jtag arp_init-reset}).
  2839. @end deffn
  2840. @deffn Command {jtag arp_init}
  2841. This validates the scan chain using just the four
  2842. standard JTAG signals (TMS, TCK, TDI, TDO).
  2843. It starts by issuing a JTAG-only reset.
  2844. Then it performs checks to verify that the scan chain configuration
  2845. matches the TAPs it can observe.
  2846. Those checks include checking IDCODE values for each active TAP,
  2847. and verifying the length of their instruction registers using
  2848. TAP @code{-ircapture} and @code{-irmask} values.
  2849. If these tests all pass, TAP @code{setup} events are
  2850. issued to all TAPs with handlers for that event.
  2851. @end deffn
  2852. @deffn Command {jtag arp_init-reset}
  2853. This uses TRST and SRST to try resetting
  2854. everything on the JTAG scan chain
  2855. (and anything else connected to SRST).
  2856. It then invokes the logic of @command{jtag arp_init}.
  2857. @end deffn
  2858. @node TAP Declaration
  2859. @chapter TAP Declaration
  2860. @cindex TAP declaration
  2861. @cindex TAP configuration
  2862. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  2863. TAPs serve many roles, including:
  2864. @itemize @bullet
  2865. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
  2866. @item @b{Flash Programming} Some chips program the flash directly via JTAG.
  2867. Others do it indirectly, making a CPU do it.
  2868. @item @b{Program Download} Using the same CPU support GDB uses,
  2869. you can initialize a DRAM controller, download code to DRAM, and then
  2870. start running that code.
  2871. @item @b{Boundary Scan} Most chips support boundary scan, which
  2872. helps test for board assembly problems like solder bridges
  2873. and missing connections.
  2874. @end itemize
  2875. OpenOCD must know about the active TAPs on your board(s).
  2876. Setting up the TAPs is the core task of your configuration files.
  2877. Once those TAPs are set up, you can pass their names to code
  2878. which sets up CPUs and exports them as GDB targets,
  2879. probes flash memory, performs low-level JTAG operations, and more.
  2880. @section Scan Chains
  2881. @cindex scan chain
  2882. TAPs are part of a hardware @dfn{scan chain},
  2883. which is a daisy chain of TAPs.
  2884. They also need to be added to
  2885. OpenOCD's software mirror of that hardware list,
  2886. giving each member a name and associating other data with it.
  2887. Simple scan chains, with a single TAP, are common in
  2888. systems with a single microcontroller or microprocessor.
  2889. More complex chips may have several TAPs internally.
  2890. Very complex scan chains might have a dozen or more TAPs:
  2891. several in one chip, more in the next, and connecting
  2892. to other boards with their own chips and TAPs.
  2893. You can display the list with the @command{scan_chain} command.
  2894. (Don't confuse this with the list displayed by the @command{targets}
  2895. command, presented in the next chapter.
  2896. That only displays TAPs for CPUs which are configured as
  2897. debugging targets.)
  2898. Here's what the scan chain might look like for a chip more than one TAP:
  2899. @verbatim
  2900. TapName Enabled IdCode Expected IrLen IrCap IrMask
  2901. -- ------------------ ------- ---------- ---------- ----- ----- ------
  2902. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  2903. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  2904. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  2905. @end verbatim
  2906. OpenOCD can detect some of that information, but not all
  2907. of it. @xref{autoprobing,,Autoprobing}.
  2908. Unfortunately, those TAPs can't always be autoconfigured,
  2909. because not all devices provide good support for that.
  2910. JTAG doesn't require supporting IDCODE instructions, and
  2911. chips with JTAG routers may not link TAPs into the chain
  2912. until they are told to do so.
  2913. The configuration mechanism currently supported by OpenOCD
  2914. requires explicit configuration of all TAP devices using
  2915. @command{jtag newtap} commands, as detailed later in this chapter.
  2916. A command like this would declare one tap and name it @code{chip1.cpu}:
  2917. @example
  2918. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  2919. @end example
  2920. Each target configuration file lists the TAPs provided
  2921. by a given chip.
  2922. Board configuration files combine all the targets on a board,
  2923. and so forth.
  2924. Note that @emph{the order in which TAPs are declared is very important.}
  2925. That declaration order must match the order in the JTAG scan chain,
  2926. both inside a single chip and between them.
  2927. @xref{faqtaporder,,FAQ TAP Order}.
  2928. For example, the ST Microsystems STR912 chip has
  2929. three separate TAPs@footnote{See the ST
  2930. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  2931. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  2932. @url{}}.
  2933. To configure those taps, @file{target/str912.cfg}
  2934. includes commands something like this:
  2935. @example
  2936. jtag newtap str912 flash ... params ...
  2937. jtag newtap str912 cpu ... params ...
  2938. jtag newtap str912 bs ... params ...
  2939. @end example
  2940. Actual config files typically use a variable such as @code{$_CHIPNAME}
  2941. instead of literals like @option{str912}, to support more than one chip
  2942. of each type. @xref{Config File Guidelines}.
  2943. @deffn Command {jtag names}
  2944. Returns the names of all current TAPs in the scan chain.
  2945. Use @command{jtag cget} or @command{jtag tapisenabled}
  2946. to examine attributes and state of each TAP.
  2947. @example
  2948. foreach t [jtag names] @{
  2949. puts [format "TAP: %s\n" $t]
  2950. @}
  2951. @end example
  2952. @end deffn
  2953. @deffn Command {scan_chain}
  2954. Displays the TAPs in the scan chain configuration,
  2955. and their status.
  2956. The set of TAPs listed by this command is fixed by
  2957. exiting the OpenOCD configuration stage,
  2958. but systems with a JTAG router can
  2959. enable or disable TAPs dynamically.
  2960. @end deffn
  2961. @c FIXME! "jtag cget" should be able to return all TAP
  2962. @c attributes, like "$target_name cget" does for targets.
  2963. @c Probably want "jtag eventlist", and a "tap-reset" event
  2964. @c (on entry to RESET state).
  2965. @section TAP Names
  2966. @cindex dotted name
  2967. When TAP objects are declared with @command{jtag newtap},
  2968. a @dfn{} is created for the TAP, combining the
  2969. name of a module (usually a chip) and a label for the TAP.
  2970. For example: @code{xilinx.tap}, @code{str912.flash},
  2971. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  2972. Many other commands use that to manipulate or
  2973. refer to the TAP. For example, CPU configuration uses the
  2974. name, as does declaration of NAND or NOR flash banks.
  2975. The components of a dotted name should follow ``C'' symbol
  2976. name rules: start with an alphabetic character, then numbers
  2977. and underscores are OK; while others (including dots!) are not.
  2978. @section TAP Declaration Commands
  2979. @c shouldn't this be(come) a {Config Command}?
  2980. @deffn Command {jtag newtap} chipname tapname configparams...
  2981. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  2982. and configured according to the various @var{configparams}.
  2983. The @var{chipname} is a symbolic name for the chip.
  2984. Conventionally target config files use @code{$_CHIPNAME},
  2985. defaulting to the model name given by the chip vendor but
  2986. overridable.
  2987. @cindex TAP naming convention
  2988. The @var{tapname} reflects the role of that TAP,
  2989. and should follow this convention:
  2990. @itemize @bullet
  2991. @item @code{bs} -- For boundary scan if this is a separate TAP;
  2992. @item @code{cpu} -- The main CPU of the chip, alternatively
  2993. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  2994. @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
  2995. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  2996. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  2997. @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
  2998. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  2999. @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
  3000. with a single TAP;
  3001. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  3002. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  3003. For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
  3004. a JTAG TAP; that TAP should be named @code{sdma}.
  3005. @end itemize
  3006. Every TAP requires at least the following @var{configparams}:
  3007. @itemize @bullet
  3008. @item @code{-irlen} @var{NUMBER}
  3009. @*The length in bits of the
  3010. instruction register, such as 4 or 5 bits.
  3011. @end itemize
  3012. A TAP may also provide optional @var{configparams}:
  3013. @itemize @bullet
  3014. @item @code{-disable} (or @code{-enable})
  3015. @*Use the @code{-disable} parameter to flag a TAP which is not
  3016. linked into the scan chain after a reset using either TRST
  3017. or the JTAG state machine's @sc{reset} state.
  3018. You may use @code{-enable} to highlight the default state
  3019. (the TAP is linked in).
  3020. @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
  3021. @item @code{-expected-id} @var{NUMBER}
  3022. @*A non-zero @var{number} represents a 32-bit IDCODE
  3023. which you expect to find when the scan chain is examined.
  3024. These codes are not required by all JTAG devices.
  3025. @emph{Repeat the option} as many times as required if more than one
  3026. ID code could appear (for example, multiple versions).
  3027. Specify @var{number} as zero to suppress warnings about IDCODE
  3028. values that were found but not included in the list.
  3029. Provide this value if at all possible, since it lets OpenOCD
  3030. tell when the scan chain it sees isn't right. These values
  3031. are provided in vendors' chip documentation, usually a technical
  3032. reference manual. Sometimes you may need to probe the JTAG
  3033. hardware to find these values.
  3034. @xref{autoprobing,,Autoprobing}.
  3035. @item @code{-ignore-version}
  3036. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  3037. option. When vendors put out multiple versions of a chip, or use the same
  3038. JTAG-level ID for several largely-compatible chips, it may be more practical
  3039. to ignore the version field than to update config files to handle all of
  3040. the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
  3041. @item @code{-ircapture} @var{NUMBER}
  3042. @*The bit pattern loaded by the TAP into the JTAG shift register
  3043. on entry to the @sc{ircapture} state, such as 0x01.
  3044. JTAG requires the two LSBs of this value to be 01.
  3045. By default, @code{-ircapture} and @code{-irmask} are set
  3046. up to verify that two-bit value. You may provide
  3047. additional bits if you know them, or indicate that
  3048. a TAP doesn't conform to the JTAG specification.
  3049. @item @code{-irmask} @var{NUMBER}
  3050. @*A mask used with @code{-ircapture}
  3051. to verify that instruction scans work correctly.
  3052. Such scans are not used by OpenOCD except to verify that
  3053. there seems to be no problems with JTAG scan chain operations.
  3054. @end itemize
  3055. @end deffn
  3056. @section Other TAP commands
  3057. @deffn Command {jtag cget} @option{-event} event_name
  3058. @deffnx Command {jtag configure} @option{-event} event_name handler
  3059. At this writing this TAP attribute
  3060. mechanism is used only for event handling.
  3061. (It is not a direct analogue of the @code{cget}/@code{configure}
  3062. mechanism for debugger targets.)
  3063. See the next section for information about the available events.
  3064. The @code{configure} subcommand assigns an event handler,
  3065. a TCL string which is evaluated when the event is triggered.
  3066. The @code{cget} subcommand returns that handler.
  3067. @end deffn
  3068. @section TAP Events
  3069. @cindex events
  3070. @cindex TAP events
  3071. OpenOCD includes two event mechanisms.
  3072. The one presented here applies to all JTAG TAPs.
  3073. The other applies to debugger targets,
  3074. which are associated with certain TAPs.
  3075. The TAP events currently defined are:
  3076. @itemize @bullet
  3077. @item @b{post-reset}
  3078. @* The TAP has just completed a JTAG reset.
  3079. The tap may still be in the JTAG @sc{reset} state.
  3080. Handlers for these events might perform initialization sequences
  3081. such as issuing TCK cycles, TMS sequences to ensure
  3082. exit from the ARM SWD mode, and more.
  3083. Because the scan chain has not yet been verified, handlers for these events
  3084. @emph{should not issue commands which scan the JTAG IR or DR registers}
  3085. of any particular target.
  3086. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  3087. @item @b{setup}
  3088. @* The scan chain has been reset and verified.
  3089. This handler may enable TAPs as needed.
  3090. @item @b{tap-disable}
  3091. @* The TAP needs to be disabled. This handler should
  3092. implement @command{jtag tapdisable}
  3093. by issuing the relevant JTAG commands.
  3094. @item @b{tap-enable}
  3095. @* The TAP needs to be enabled. This handler should
  3096. implement @command{jtag tapenable}
  3097. by issuing the relevant JTAG commands.
  3098. @end itemize
  3099. If you need some action after each JTAG reset which isn't actually
  3100. specific to any TAP (since you can't yet trust the scan chain's
  3101. contents to be accurate), you might:
  3102. @example
  3103. jtag configure CHIP.jrc -event post-reset @{
  3104. echo "JTAG Reset done"
  3105. ... non-scan jtag operations to be done after reset
  3106. @}
  3107. @end example
  3108. @anchor{enablinganddisablingtaps}
  3109. @section Enabling and Disabling TAPs
  3110. @cindex JTAG Route Controller
  3111. @cindex jrc
  3112. In some systems, a @dfn{JTAG Route Controller} (JRC)
  3113. is used to enable and/or disable specific JTAG TAPs.
  3114. Many ARM-based chips from Texas Instruments include
  3115. an ``ICEPick'' module, which is a JRC.
  3116. Such chips include DaVinci and OMAP3 processors.
  3117. A given TAP may not be visible until the JRC has been
  3118. told to link it into the scan chain; and if the JRC
  3119. has been told to unlink that TAP, it will no longer
  3120. be visible.
  3121. Such routers address problems that JTAG ``bypass mode''
  3122. ignores, such as:
  3123. @itemize
  3124. @item The scan chain can only go as fast as its slowest TAP.
  3125. @item Having many TAPs slows instruction scans, since all
  3126. TAPs receive new instructions.
  3127. @item TAPs in the scan chain must be powered up, which wastes
  3128. power and prevents debugging some power management mechanisms.
  3129. @end itemize
  3130. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  3131. as implied by the existence of JTAG routers.
  3132. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  3133. does include a kind of JTAG router functionality.
  3134. @c (a) currently the event handlers don't seem to be able to
  3135. @c fail in a way that could lead to no-change-of-state.
  3136. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  3137. shown below, and is implemented using TAP event handlers.
  3138. So for example, when defining a TAP for a CPU connected to
  3139. a JTAG router, your @file{target.cfg} file
  3140. should define TAP event handlers using
  3141. code that looks something like this:
  3142. @example
  3143. jtag configure CHIP.cpu -event tap-enable @{
  3144. ... jtag operations using CHIP.jrc
  3145. @}
  3146. jtag configure CHIP.cpu -event tap-disable @{
  3147. ... jtag operations using CHIP.jrc
  3148. @}
  3149. @end example
  3150. Then you might want that CPU's TAP enabled almost all the time:
  3151. @example
  3152. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  3153. @end example
  3154. Note how that particular setup event handler declaration
  3155. uses quotes to evaluate @code{$CHIP} when the event is configured.
  3156. Using brackets @{ @} would cause it to be evaluated later,
  3157. at runtime, when it might have a different value.
  3158. @deffn Command {jtag tapdisable}
  3159. If necessary, disables the tap
  3160. by sending it a @option{tap-disable} event.
  3161. Returns the string "1" if the tap
  3162. specified by @var{} is enabled,
  3163. and "0" if it is disabled.
  3164. @end deffn
  3165. @deffn Command {jtag tapenable}
  3166. If necessary, enables the tap
  3167. by sending it a @option{tap-enable} event.
  3168. Returns the string "1" if the tap
  3169. specified by @var{} is enabled,
  3170. and "0" if it is disabled.
  3171. @end deffn
  3172. @deffn Command {jtag tapisenabled}
  3173. Returns the string "1" if the tap
  3174. specified by @var{} is enabled,
  3175. and "0" if it is disabled.
  3176. @quotation Note
  3177. Humans will find the @command{scan_chain} command more helpful
  3178. for querying the state of the JTAG taps.
  3179. @end quotation
  3180. @end deffn
  3181. @anchor{autoprobing}
  3182. @section Autoprobing
  3183. @cindex autoprobe
  3184. @cindex JTAG autoprobe
  3185. TAP configuration is the first thing that needs to be done
  3186. after interface and reset configuration. Sometimes it's
  3187. hard finding out what TAPs exist, or how they are identified.
  3188. Vendor documentation is not always easy to find and use.
  3189. To help you get past such problems, OpenOCD has a limited
  3190. @emph{autoprobing} ability to look at the scan chain, doing
  3191. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  3192. To use this mechanism, start the OpenOCD server with only data
  3193. that configures your JTAG interface, and arranges to come up
  3194. with a slow clock (many devices don't support fast JTAG clocks
  3195. right when they come out of reset).
  3196. For example, your @file{openocd.cfg} file might have:
  3197. @example
  3198. source [find interface/olimex-arm-usb-tiny-h.cfg]
  3199. reset_config trst_and_srst
  3200. jtag_rclk 8
  3201. @end example
  3202. When you start the server without any TAPs configured, it will
  3203. attempt to autoconfigure the TAPs. There are two parts to this:
  3204. @enumerate
  3205. @item @emph{TAP discovery} ...
  3206. After a JTAG reset (sometimes a system reset may be needed too),
  3207. each TAP's data registers will hold the contents of either the
  3208. IDCODE or BYPASS register.
  3209. If JTAG communication is working, OpenOCD will see each TAP,
  3210. and report what @option{-expected-id} to use with it.
  3211. @item @emph{IR Length discovery} ...
  3212. Unfortunately JTAG does not provide a reliable way to find out
  3213. the value of the @option{-irlen} parameter to use with a TAP
  3214. that is discovered.
  3215. If OpenOCD can discover the length of a TAP's instruction
  3216. register, it will report it.
  3217. Otherwise you may need to consult vendor documentation, such
  3218. as chip data sheets or BSDL files.
  3219. @end enumerate
  3220. In many cases your board will have a simple scan chain with just
  3221. a single device. Here's what OpenOCD reported with one board
  3222. that's a bit more complex:
  3223. @example
  3224. clock speed 8 kHz
  3225. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  3226. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  3227. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  3228. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  3229. AUTO auto0.tap - use "... -irlen 4"
  3230. AUTO auto1.tap - use "... -irlen 4"
  3231. AUTO auto2.tap - use "... -irlen 6"
  3232. no gdb ports allocated as no target has been specified
  3233. @end example
  3234. Given that information, you should be able to either find some existing
  3235. config files to use, or create your own. If you create your own, you
  3236. would configure from the bottom up: first a @file{target.cfg} file
  3237. with these TAPs, any targets associated with them, and any on-chip
  3238. resources; then a @file{board.cfg} with off-chip resources, clocking,
  3239. and so forth.
  3240. @node CPU Configuration
  3241. @chapter CPU Configuration
  3242. @cindex GDB target
  3243. This chapter discusses how to set up GDB debug targets for CPUs.
  3244. You can also access these targets without GDB
  3245. (@pxref{Architecture and Core Commands},
  3246. and @ref{targetstatehandling,,Target State handling}) and
  3247. through various kinds of NAND and NOR flash commands.
  3248. If you have multiple CPUs you can have multiple such targets.
  3249. We'll start by looking at how to examine the targets you have,
  3250. then look at how to add one more target and how to configure it.
  3251. @section Target List
  3252. @cindex target, current
  3253. @cindex target, list
  3254. All targets that have been set up are part of a list,
  3255. where each member has a name.
  3256. That name should normally be the same as the TAP name.
  3257. You can display the list with the @command{targets}
  3258. (plural!) command.
  3259. This display often has only one CPU; here's what it might
  3260. look like with more than one:
  3261. @verbatim
  3262. TargetName Type Endian TapName State
  3263. -- ------------------ ---------- ------ ------------------ ------------
  3264. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  3265. 1 MyTarget cortex_m little tap-disabled
  3266. @end verbatim
  3267. One member of that list is the @dfn{current target}, which
  3268. is implicitly referenced by many commands.
  3269. It's the one marked with a @code{*} near the target name.
  3270. In particular, memory addresses often refer to the address
  3271. space seen by that current target.
  3272. Commands like @command{mdw} (memory display words)
  3273. and @command{flash erase_address} (erase NOR flash blocks)
  3274. are examples; and there are many more.
  3275. Several commands let you examine the list of targets:
  3276. @deffn Command {target current}
  3277. Returns the name of the current target.
  3278. @end deffn
  3279. @deffn Command {target names}
  3280. Lists the names of all current targets in the list.
  3281. @example
  3282. foreach t [target names] @{
  3283. puts [format "Target: %s\n" $t]
  3284. @}
  3285. @end example
  3286. @end deffn
  3287. @c yep, "target list" would have been better.
  3288. @c plus maybe "target setdefault".
  3289. @deffn Command targets [name]
  3290. @emph{Note: the name of this command is plural. Other target
  3291. command names are singular.}
  3292. With no parameter, this command displays a table of all known
  3293. targets in a user friendly form.
  3294. With a parameter, this command sets the current target to
  3295. the given target with the given @var{name}; this is
  3296. only relevant on boards which have more than one target.
  3297. @end deffn
  3298. @section Target CPU Types
  3299. @cindex target type
  3300. @cindex CPU type
  3301. Each target has a @dfn{CPU type}, as shown in the output of
  3302. the @command{targets} command. You need to specify that type
  3303. when calling @command{target create}.
  3304. The CPU type indicates more than just the instruction set.
  3305. It also indicates how that instruction set is implemented,
  3306. what kind of debug support it integrates,
  3307. whether it has an MMU (and if so, what kind),
  3308. what core-specific commands may be available
  3309. (@pxref{Architecture and Core Commands}),
  3310. and more.
  3311. It's easy to see what target types are supported,
  3312. since there's a command to list them.
  3313. @anchor{targettypes}
  3314. @deffn Command {target types}
  3315. Lists all supported target types.
  3316. At this writing, the supported CPU types are:
  3317. @itemize @bullet
  3318. @item @code{arm11} -- this is a generation of ARMv6 cores
  3319. @item @code{arm720t} -- this is an ARMv4 core with an MMU
  3320. @item @code{arm7tdmi} -- this is an ARMv4 core
  3321. @item @code{arm920t} -- this is an ARMv4 core with an MMU
  3322. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
  3323. @item @code{arm966e} -- this is an ARMv5 core
  3324. @item @code{arm9tdmi} -- this is an ARMv4 core
  3325. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  3326. (Support for this is preliminary and incomplete.)
  3327. @item @code{cortex_a} -- this is an ARMv7 core with an MMU
  3328. @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
  3329. compact Thumb2 instruction set.
  3330. @item @code{dragonite} -- resembles arm966e
  3331. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  3332. (Support for this is still incomplete.)
  3333. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  3334. @item @code{feroceon} -- resembles arm926
  3335. @item @code{mips_m4k} -- a MIPS core
  3336. @item @code{xscale} -- this is actually an architecture,
  3337. not a CPU type. It is based on the ARMv5 architecture.
  3338. @item @code{openrisc} -- this is an OpenRISC 1000 core.
  3339. The current implementation supports three JTAG TAP cores:
  3340. @itemize @minus
  3341. @item @code{OpenCores TAP} (See: @url{,jtag})
  3342. @item @code{Altera Virtual JTAG TAP} (See: @url{})
  3343. @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{})
  3344. @end itemize
  3345. And two debug interfaces cores:
  3346. @itemize @minus
  3347. @item @code{Advanced debug interface} (See: @url{,adv_debug_sys})
  3348. @item @code{SoC Debug Interface} (See: @url{,dbg_interface})
  3349. @end itemize
  3350. @end itemize
  3351. @end deffn
  3352. To avoid being confused by the variety of ARM based cores, remember
  3353. this key point: @emph{ARM is a technology licencing company}.
  3354. (See: @url{}.)
  3355. The CPU name used by OpenOCD will reflect the CPU design that was
  3356. licenced, not a vendor brand which incorporates that design.
  3357. Name prefixes like arm7, arm9, arm11, and cortex
  3358. reflect design generations;
  3359. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  3360. reflect an architecture version implemented by a CPU design.
  3361. @anchor{targetconfiguration}
  3362. @section Target Configuration
  3363. Before creating a ``target'', you must have added its TAP to the scan chain.
  3364. When you've added that TAP, you will have a @code{}
  3365. which is used to set up the CPU support.
  3366. The chip-specific configuration file will normally configure its CPU(s)
  3367. right after it adds all of the chip's TAPs to the scan chain.
  3368. Although you can set up a target in one step, it's often clearer if you
  3369. use shorter commands and do it in two steps: create it, then configure
  3370. optional parts.
  3371. All operations on the target after it's created will use a new
  3372. command, created as part of target creation.
  3373. The two main things to configure after target creation are
  3374. a work area, which usually has target-specific defaults even
  3375. if the board setup code overrides them later;
  3376. and event handlers (@pxref{targetevents,,Target Events}), which tend
  3377. to be much more board-specific.
  3378. The key steps you use might look something like this
  3379. @example
  3380. target create MyTarget cortex_m -chain-position mychip.cpu
  3381. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  3382. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  3383. $MyTarget configure -event reset-init @{ myboard_reinit @}
  3384. @end example
  3385. You should specify a working area if you can; typically it uses some
  3386. on-chip SRAM.
  3387. Such a working area can speed up many things, including bulk
  3388. writes to target memory;
  3389. flash operations like checking to see if memory needs to be erased;
  3390. GDB memory checksumming;
  3391. and more.
  3392. @quotation Warning
  3393. On more complex chips, the work area can become
  3394. inaccessible when application code
  3395. (such as an operating system)
  3396. enables or disables the MMU.
  3397. For example, the particular MMU context used to acess the virtual
  3398. address will probably matter ... and that context might not have
  3399. easy access to other addresses needed.
  3400. At this writing, OpenOCD doesn't have much MMU intelligence.
  3401. @end quotation
  3402. It's often very useful to define a @code{reset-init} event handler.
  3403. For systems that are normally used with a boot loader,
  3404. common tasks include updating clocks and initializing memory
  3405. controllers.
  3406. That may be needed to let you write the boot loader into flash,
  3407. in order to ``de-brick'' your board; or to load programs into
  3408. external DDR memory without having run the boot loader.
  3409. @deffn Command {target create} target_name type configparams...
  3410. This command creates a GDB debug target that refers to a specific JTAG tap.
  3411. It enters that target into a list, and creates a new
  3412. command (@command{@var{target_name}}) which is used for various
  3413. purposes including additional configuration.
  3414. @itemize @bullet
  3415. @item @var{target_name} ... is the name of the debug target.
  3416. By convention this should be the same as the @emph{}
  3417. of the TAP associated with this target, which must be specified here
  3418. using the @code{-chain-position @var{}} configparam.
  3419. This name is also used to create the target object command,
  3420. referred to here as @command{$target_name},
  3421. and in other places the target needs to be identified.
  3422. @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
  3423. @item @var{configparams} ... all parameters accepted by
  3424. @command{$target_name configure} are permitted.
  3425. If the target is big-endian, set it here with @code{-endian big}.
  3426. You @emph{must} set the @code{-chain-position @var{}} here.
  3427. @end itemize
  3428. @end deffn
  3429. @deffn Command {$target_name configure} configparams...
  3430. The options accepted by this command may also be
  3431. specified as parameters to @command{target create}.
  3432. Their values can later be queried one at a time by
  3433. using the @command{$target_name cget} command.
  3434. @emph{Warning:} changing some of these after setup is dangerous.
  3435. For example, moving a target from one TAP to another;
  3436. and changing its endianness.
  3437. @itemize @bullet
  3438. @item @code{-chain-position} @var{} -- names the TAP
  3439. used to access this target.
  3440. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  3441. whether the CPU uses big or little endian conventions
  3442. @item @code{-event} @var{event_name} @var{event_body} --
  3443. @xref{targetevents,,Target Events}.
  3444. Note that this updates a list of named event handlers.
  3445. Calling this twice with two different event names assigns
  3446. two different handlers, but calling it twice with the
  3447. same event name assigns only one handler.
  3448. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  3449. whether the work area gets backed up; by default,
  3450. @emph{it is not backed up.}
  3451. When possible, use a working_area that doesn't need to be backed up,
  3452. since performing a backup slows down operations.
  3453. For example, the beginning of an SRAM block is likely to
  3454. be used by most build systems, but the end is often unused.
  3455. @item @code{-work-area-size} @var{size} -- specify work are size,
  3456. in bytes. The same size applies regardless of whether its physical
  3457. or virtual address is being used.
  3458. @item @code{-work-area-phys} @var{address} -- set the work area
  3459. base @var{address} to be used when no MMU is active.
  3460. @item @code{-work-area-virt} @var{address} -- set the work area
  3461. base @var{address} to be used when an MMU is active.
  3462. @emph{Do not specify a value for this except on targets with an MMU.}
  3463. The value should normally correspond to a static mapping for the
  3464. @code{-work-area-phys} address, set up by the current operating system.
  3465. @anchor{rtostype}
  3466. @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
  3467. @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
  3468. @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}|@option{mqx}
  3469. @xref{gdbrtossupport,,RTOS Support}.
  3470. @end itemize
  3471. @end deffn
  3472. @section Other $target_name Commands
  3473. @cindex object command
  3474. The Tcl/Tk language has the concept of object commands,
  3475. and OpenOCD adopts that same model for targets.
  3476. A good Tk example is a on screen button.
  3477. Once a button is created a button
  3478. has a name (a path in Tk terms) and that name is useable as a first
  3479. class command. For example in Tk, one can create a button and later
  3480. configure it like this:
  3481. @example
  3482. # Create
  3483. button .foobar -background red -command @{ foo @}
  3484. # Modify
  3485. .foobar configure -foreground blue
  3486. # Query
  3487. set x [.foobar cget -background]
  3488. # Report
  3489. puts [format "The button is %s" $x]
  3490. @end example
  3491. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  3492. button, and its object commands are invoked the same way.
  3493. @example
  3494. str912.cpu mww 0x1234 0x42
  3495. omap3530.cpu mww 0x5555 123
  3496. @end example
  3497. The commands supported by OpenOCD target objects are:
  3498. @deffn Command {$target_name arp_examine}
  3499. @deffnx Command {$target_name arp_halt}
  3500. @deffnx Command {$target_name arp_poll}
  3501. @deffnx Command {$target_name arp_reset}
  3502. @deffnx Command {$target_name arp_waitstate}
  3503. Internal OpenOCD scripts (most notably @file{startup.tcl})
  3504. use these to deal with specific reset cases.
  3505. They are not otherwise documented here.
  3506. @end deffn
  3507. @deffn Command {$target_name array2mem} arrayname width address count
  3508. @deffnx Command {$target_name mem2array} arrayname width address count
  3509. These provide an efficient script-oriented interface to memory.
  3510. The @code{array2mem} primitive writes bytes, halfwords, or words;
  3511. while @code{mem2array} reads them.
  3512. In both cases, the TCL side uses an array, and
  3513. the target side uses raw memory.
  3514. The efficiency comes from enabling the use of
  3515. bulk JTAG data transfer operations.
  3516. The script orientation comes from working with data
  3517. values that are packaged for use by TCL scripts;
  3518. @command{mdw} type primitives only print data they retrieve,
  3519. and neither store nor return those values.
  3520. @itemize
  3521. @item @var{arrayname} ... is the name of an array variable
  3522. @item @var{width} ... is 8/16/32 - indicating the memory access size
  3523. @item @var{address} ... is the target memory address
  3524. @item @var{count} ... is the number of elements to process
  3525. @end itemize
  3526. @end deffn
  3527. @deffn Command {$target_name cget} queryparm
  3528. Each configuration parameter accepted by
  3529. @command{$target_name configure}
  3530. can be individually queried, to return its current value.
  3531. The @var{queryparm} is a parameter name
  3532. accepted by that command, such as @code{-work-area-phys}.
  3533. There are a few special cases:
  3534. @itemize @bullet
  3535. @item @code{-event} @var{event_name} -- returns the handler for the
  3536. event named @var{event_name}.
  3537. This is a special case because setting a handler requires
  3538. two parameters.
  3539. @item @code{-type} -- returns the target type.
  3540. This is a special case because this is set using
  3541. @command{target create} and can't be changed
  3542. using @command{$target_name configure}.
  3543. @end itemize
  3544. For example, if you wanted to summarize information about
  3545. all the targets you might use something like this:
  3546. @example
  3547. foreach name [target names] @{
  3548. set y [$name cget -endian]
  3549. set z [$name cget -type]
  3550. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  3551. $x $name $y $z]
  3552. @}
  3553. @end example
  3554. @end deffn
  3555. @anchor{targetcurstate}
  3556. @deffn Command {$target_name curstate}
  3557. Displays the current target state:
  3558. @code{debug-running},
  3559. @code{halted},
  3560. @code{reset},
  3561. @code{running}, or @code{unknown}.
  3562. (Also, @pxref{eventpolling,,Event Polling}.)
  3563. @end deffn
  3564. @deffn Command {$target_name eventlist}
  3565. Displays a table listing all event handlers
  3566. currently associated with this target.
  3567. @xref{targetevents,,Target Events}.
  3568. @end deffn
  3569. @deffn Command {$target_name invoke-event} event_name
  3570. Invokes the handler for the event named @var{event_name}.
  3571. (This is primarily intended for use by OpenOCD framework
  3572. code, for example by the reset code in @file{startup.tcl}.)
  3573. @end deffn
  3574. @deffn Command {$target_name mdw} addr [count]
  3575. @deffnx Command {$target_name mdh} addr [count]
  3576. @deffnx Command {$target_name mdb} addr [count]
  3577. Display contents of address @var{addr}, as
  3578. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  3579. or 8-bit bytes (@command{mdb}).
  3580. If @var{count} is specified, displays that many units.
  3581. (If you want to manipulate the data instead of displaying it,
  3582. see the @code{mem2array} primitives.)
  3583. @end deffn
  3584. @deffn Command {$target_name mww} addr word
  3585. @deffnx Command {$target_name mwh} addr halfword
  3586. @deffnx Command {$target_name mwb} addr byte
  3587. Writes the specified @var{word} (32 bits),
  3588. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3589. at the specified address @var{addr}.
  3590. @end deffn
  3591. @anchor{targetevents}
  3592. @section Target Events
  3593. @cindex target events
  3594. @cindex events
  3595. At various times, certain things can happen, or you want them to happen.
  3596. For example:
  3597. @itemize @bullet
  3598. @item What should happen when GDB connects? Should your target reset?
  3599. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  3600. @item Is using SRST appropriate (and possible) on your system?
  3601. Or instead of that, do you need to issue JTAG commands to trigger reset?
  3602. SRST usually resets everything on the scan chain, which can be inappropriate.
  3603. @item During reset, do you need to write to certain memory locations
  3604. to set up system clocks or
  3605. to reconfigure the SDRAM?
  3606. How about configuring the watchdog timer, or other peripherals,
  3607. to stop running while you hold the core stopped for debugging?
  3608. @end itemize
  3609. All of the above items can be addressed by target event handlers.
  3610. These are set up by @command{$target_name configure -event} or
  3611. @command{target create ... -event}.
  3612. The programmer's model matches the @code{-command} option used in Tcl/Tk
  3613. buttons and events. The two examples below act the same, but one creates
  3614. and invokes a small procedure while the other inlines it.
  3615. @example
  3616. proc my_attach_proc @{ @} @{
  3617. echo "Reset..."
  3618. reset halt
  3619. @}
  3620. mychip.cpu configure -event gdb-attach my_attach_proc
  3621. mychip.cpu configure -event gdb-attach @{
  3622. echo "Reset..."
  3623. # To make flash probe and gdb load to flash work
  3624. # we need a reset init.
  3625. reset init
  3626. @}
  3627. @end example
  3628. The following target events are defined:
  3629. @itemize @bullet
  3630. @item @b{debug-halted}
  3631. @* The target has halted for debug reasons (i.e.: breakpoint)
  3632. @item @b{debug-resumed}
  3633. @* The target has resumed (i.e.: gdb said run)
  3634. @item @b{early-halted}
  3635. @* Occurs early in the halt process
  3636. @item @b{examine-start}
  3637. @* Before target examine is called.
  3638. @item @b{examine-end}
  3639. @* After target examine is called with no errors.
  3640. @item @b{gdb-attach}
  3641. @* When GDB connects. This is before any communication with the target, so this
  3642. can be used to set up the target so it is possible to probe flash. Probing flash
  3643. is necessary during gdb connect if gdb load is to write the image to flash. Another
  3644. use of the flash memory map is for GDB to automatically hardware/software breakpoints
  3645. depending on whether the breakpoint is in RAM or read only memory.
  3646. @item @b{gdb-detach}
  3647. @* When GDB disconnects
  3648. @item @b{gdb-end}
  3649. @* When the target has halted and GDB is not doing anything (see early halt)
  3650. @item @b{gdb-flash-erase-start}
  3651. @* Before the GDB flash process tries to erase the flash (default is
  3652. @code{reset init})
  3653. @item @b{gdb-flash-erase-end}
  3654. @* After the GDB flash process has finished erasing the flash
  3655. @item @b{gdb-flash-write-start}
  3656. @* Before GDB writes to the flash
  3657. @item @b{gdb-flash-write-end}
  3658. @* After GDB writes to the flash (default is @code{reset halt})
  3659. @item @b{gdb-start}
  3660. @* Before the target steps, gdb is trying to start/resume the target
  3661. @item @b{halted}
  3662. @* The target has halted
  3663. @item @b{reset-assert-pre}
  3664. @* Issued as part of @command{reset} processing
  3665. after @command{reset_init} was triggered
  3666. but before either SRST alone is re-asserted on the scan chain,
  3667. or @code{reset-assert} is triggered.
  3668. @item @b{reset-assert}
  3669. @* Issued as part of @command{reset} processing
  3670. after @command{reset-assert-pre} was triggered.
  3671. When such a handler is present, cores which support this event will use
  3672. it instead of asserting SRST.
  3673. This support is essential for debugging with JTAG interfaces which
  3674. don't include an SRST line (JTAG doesn't require SRST), and for
  3675. selective reset on scan chains that have multiple targets.
  3676. @item @b{reset-assert-post}
  3677. @* Issued as part of @command{reset} processing
  3678. after @code{reset-assert} has been triggered.
  3679. or the target asserted SRST on the entire scan chain.
  3680. @item @b{reset-deassert-pre}
  3681. @* Issued as part of @command{reset} processing
  3682. after @code{reset-assert-post} has been triggered.
  3683. @item @b{reset-deassert-post}
  3684. @* Issued as part of @command{reset} processing
  3685. after @code{reset-deassert-pre} has been triggered
  3686. and (if the target is using it) after SRST has been
  3687. released on the scan chain.
  3688. @item @b{reset-end}
  3689. @* Issued as the final step in @command{reset} processing.
  3690. @ignore
  3691. @item @b{reset-halt-post}
  3692. @* Currently not used
  3693. @item @b{reset-halt-pre}
  3694. @* Currently not used
  3695. @end ignore
  3696. @item @b{reset-init}
  3697. @* Used by @b{reset init} command for board-specific initialization.
  3698. This event fires after @emph{reset-deassert-post}.
  3699. This is where you would configure PLLs and clocking, set up DRAM so
  3700. you can download programs that don't fit in on-chip SRAM, set up pin
  3701. multiplexing, and so on.
  3702. (You may be able to switch to a fast JTAG clock rate here, after
  3703. the target clocks are fully set up.)
  3704. @item @b{reset-start}
  3705. @* Issued as part of @command{reset} processing
  3706. before @command{reset_init} is called.
  3707. This is the most robust place to use @command{jtag_rclk}
  3708. or @command{adapter_khz} to switch to a low JTAG clock rate,
  3709. when reset disables PLLs needed to use a fast clock.
  3710. @ignore
  3711. @item @b{reset-wait-pos}
  3712. @* Currently not used
  3713. @item @b{reset-wait-pre}
  3714. @* Currently not used
  3715. @end ignore
  3716. @item @b{resume-start}
  3717. @* Before any target is resumed
  3718. @item @b{resume-end}
  3719. @* After all targets have resumed
  3720. @item @b{resumed}
  3721. @* Target has resumed
  3722. @item @b{trace-config}
  3723. @* After target hardware trace configuration was changed
  3724. @end itemize
  3725. @node Flash Commands
  3726. @chapter Flash Commands
  3727. OpenOCD has different commands for NOR and NAND flash;
  3728. the ``flash'' command works with NOR flash, while
  3729. the ``nand'' command works with NAND flash.
  3730. This partially reflects different hardware technologies:
  3731. NOR flash usually supports direct CPU instruction and data bus access,
  3732. while data from a NAND flash must be copied to memory before it can be
  3733. used. (SPI flash must also be copied to memory before use.)
  3734. However, the documentation also uses ``flash'' as a generic term;
  3735. for example, ``Put flash configuration in board-specific files''.
  3736. Flash Steps:
  3737. @enumerate
  3738. @item Configure via the command @command{flash bank}
  3739. @* Do this in a board-specific configuration file,
  3740. passing parameters as needed by the driver.
  3741. @item Operate on the flash via @command{flash subcommand}
  3742. @* Often commands to manipulate the flash are typed by a human, or run
  3743. via a script in some automated way. Common tasks include writing a
  3744. boot loader, operating system, or other data.
  3745. @item GDB Flashing
  3746. @* Flashing via GDB requires the flash be configured via ``flash
  3747. bank'', and the GDB flash features be enabled.
  3748. @xref{gdbconfiguration,,GDB Configuration}.
  3749. @end enumerate
  3750. Many CPUs have the ablity to ``boot'' from the first flash bank.
  3751. This means that misprogramming that bank can ``brick'' a system,
  3752. so that it can't boot.
  3753. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  3754. board by (re)installing working boot firmware.
  3755. @anchor{norconfiguration}
  3756. @section Flash Configuration Commands
  3757. @cindex flash configuration
  3758. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  3759. Configures a flash bank which provides persistent storage
  3760. for addresses from @math{base} to @math{base + size - 1}.
  3761. These banks will often be visible to GDB through the target's memory map.
  3762. In some cases, configuring a flash bank will activate extra commands;
  3763. see the driver-specific documentation.
  3764. @itemize @bullet
  3765. @item @var{name} ... may be used to reference the flash bank
  3766. in other flash commands. A number is also available.
  3767. @item @var{driver} ... identifies the controller driver
  3768. associated with the flash bank being declared.
  3769. This is usually @code{cfi} for external flash, or else
  3770. the name of a microcontroller with embedded flash memory.
  3771. @xref{flashdriverlist,,Flash Driver List}.
  3772. @item @var{base} ... Base address of the flash chip.
  3773. @item @var{size} ... Size of the chip, in bytes.
  3774. For some drivers, this value is detected from the hardware.
  3775. @item @var{chip_width} ... Width of the flash chip, in bytes;
  3776. ignored for most microcontroller drivers.
  3777. @item @var{bus_width} ... Width of the data bus used to access the
  3778. chip, in bytes; ignored for most microcontroller drivers.
  3779. @item @var{target} ... Names the target used to issue
  3780. commands to the flash controller.
  3781. @comment Actually, it's currently a controller-specific parameter...
  3782. @item @var{driver_options} ... drivers may support, or require,
  3783. additional parameters. See the driver-specific documentation
  3784. for more information.
  3785. @end itemize
  3786. @quotation Note
  3787. This command is not available after OpenOCD initialization has completed.
  3788. Use it in board specific configuration files, not interactively.
  3789. @end quotation
  3790. @end deffn
  3791. @comment the REAL name for this command is "ocd_flash_banks"
  3792. @comment less confusing would be: "flash list" (like "nand list")
  3793. @deffn Command {flash banks}
  3794. Prints a one-line summary of each device that was
  3795. declared using @command{flash bank}, numbered from zero.
  3796. Note that this is the @emph{plural} form;
  3797. the @emph{singular} form is a very different command.
  3798. @end deffn
  3799. @deffn Command {flash list}
  3800. Retrieves a list of associative arrays for each device that was
  3801. declared using @command{flash bank}, numbered from zero.
  3802. This returned list can be manipulated easily from within scripts.
  3803. @end deffn
  3804. @deffn Command {flash probe} num
  3805. Identify the flash, or validate the parameters of the configured flash. Operation
  3806. depends on the flash type.
  3807. The @var{num} parameter is a value shown by @command{flash banks}.
  3808. Most flash commands will implicitly @emph{autoprobe} the bank;
  3809. flash drivers can distinguish between probing and autoprobing,
  3810. but most don't bother.
  3811. @end deffn
  3812. @section Erasing, Reading, Writing to Flash
  3813. @cindex flash erasing
  3814. @cindex flash reading
  3815. @cindex flash writing
  3816. @cindex flash programming
  3817. @anchor{flashprogrammingcommands}
  3818. One feature distinguishing NOR flash from NAND or serial flash technologies
  3819. is that for read access, it acts exactly like any other addressible memory.
  3820. This means you can use normal memory read commands like @command{mdw} or
  3821. @command{dump_image} with it, with no special @command{flash} subcommands.
  3822. @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
  3823. Write access works differently. Flash memory normally needs to be erased
  3824. before it's written. Erasing a sector turns all of its bits to ones, and
  3825. writing can turn ones into zeroes. This is why there are special commands
  3826. for interactive erasing and writing, and why GDB needs to know which parts
  3827. of the address space hold NOR flash memory.
  3828. @quotation Note
  3829. Most of these erase and write commands leverage the fact that NOR flash
  3830. chips consume target address space. They implicitly refer to the current
  3831. JTAG target, and map from an address in that target's address space
  3832. back to a flash bank.
  3833. @comment In May 2009, those mappings may fail if any bank associated
  3834. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  3835. A few commands use abstract addressing based on bank and sector numbers,
  3836. and don't depend on searching the current target and its address space.
  3837. Avoid confusing the two command models.
  3838. @end quotation
  3839. Some flash chips implement software protection against accidental writes,
  3840. since such buggy writes could in some cases ``brick'' a system.
  3841. For such systems, erasing and writing may require sector protection to be
  3842. disabled first.
  3843. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  3844. and AT91SAM7 on-chip flash.
  3845. @xref{flashprotect,,flash protect}.
  3846. @deffn Command {flash erase_sector} num first last
  3847. Erase sectors in bank @var{num}, starting at sector @var{first}
  3848. up to and including @var{last}.
  3849. Sector numbering starts at 0.
  3850. Providing a @var{last} sector of @option{last}
  3851. specifies "to the end of the flash bank".
  3852. The @var{num} parameter is a value shown by @command{flash banks}.
  3853. @end deffn
  3854. @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
  3855. Erase sectors starting at @var{address} for @var{length} bytes.
  3856. Unless @option{pad} is specified, @math{address} must begin a
  3857. flash sector, and @math{address + length - 1} must end a sector.
  3858. Specifying @option{pad} erases extra data at the beginning and/or
  3859. end of the specified region, as needed to erase only full sectors.
  3860. The flash bank to use is inferred from the @var{address}, and
  3861. the specified length must stay within that bank.
  3862. As a special case, when @var{length} is zero and @var{address} is
  3863. the start of the bank, the whole flash is erased.
  3864. If @option{unlock} is specified, then the flash is unprotected
  3865. before erase starts.
  3866. @end deffn
  3867. @deffn Command {flash fillw} address word length
  3868. @deffnx Command {flash fillh} address halfword length
  3869. @deffnx Command {flash fillb} address byte length
  3870. Fills flash memory with the specified @var{word} (32 bits),
  3871. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3872. starting at @var{address} and continuing
  3873. for @var{length} units (word/halfword/byte).
  3874. No erasure is done before writing; when needed, that must be done
  3875. before issuing this command.
  3876. Writes are done in blocks of up to 1024 bytes, and each write is
  3877. verified by reading back the data and comparing it to what was written.
  3878. The flash bank to use is inferred from the @var{address} of
  3879. each block, and the specified length must stay within that bank.
  3880. @end deffn
  3881. @comment no current checks for errors if fill blocks touch multiple banks!
  3882. @deffn Command {flash write_bank} num filename offset
  3883. Write the binary @file{filename} to flash bank @var{num},
  3884. starting at @var{offset} bytes from the beginning of the bank.
  3885. The @var{num} parameter is a value shown by @command{flash banks}.
  3886. @end deffn
  3887. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  3888. Write the image @file{filename} to the current target's flash bank(s).
  3889. Only loadable sections from the image are written.
  3890. A relocation @var{offset} may be specified, in which case it is added
  3891. to the base address for each section in the image.
  3892. The file [@var{type}] can be specified
  3893. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  3894. @option{elf} (ELF file), @option{s19} (Motorola s19).
  3895. @option{mem}, or @option{builder}.
  3896. The relevant flash sectors will be erased prior to programming
  3897. if the @option{erase} parameter is given. If @option{unlock} is
  3898. provided, then the flash banks are unlocked before erase and
  3899. program. The flash bank to use is inferred from the address of
  3900. each image section.
  3901. @quotation Warning
  3902. Be careful using the @option{erase} flag when the flash is holding
  3903. data you want to preserve.
  3904. Portions of the flash outside those described in the image's
  3905. sections might be erased with no notice.
  3906. @itemize
  3907. @item
  3908. When a section of the image being written does not fill out all the
  3909. sectors it uses, the unwritten parts of those sectors are necessarily
  3910. also erased, because sectors can't be partially erased.
  3911. @item
  3912. Data stored in sector "holes" between image sections are also affected.
  3913. For example, "@command{flash write_image erase ...}" of an image with
  3914. one byte at the beginning of a flash bank and one byte at the end
  3915. erases the entire bank -- not just the two sectors being written.
  3916. @end itemize
  3917. Also, when flash protection is important, you must re-apply it after
  3918. it has been removed by the @option{unlock} flag.
  3919. @end quotation
  3920. @end deffn
  3921. @section Other Flash commands
  3922. @cindex flash protection
  3923. @deffn Command {flash erase_check} num
  3924. Check erase state of sectors in flash bank @var{num},
  3925. and display that status.
  3926. The @var{num} parameter is a value shown by @command{flash banks}.
  3927. @end deffn
  3928. @deffn Command {flash info} num
  3929. Print info about flash bank @var{num}
  3930. The @var{num} parameter is a value shown by @command{flash banks}.
  3931. This command will first query the hardware, it does not print cached
  3932. and possibly stale information.
  3933. @end deffn
  3934. @anchor{flashprotect}
  3935. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  3936. Enable (@option{on}) or disable (@option{off}) protection of flash sectors
  3937. in flash bank @var{num}, starting at sector @var{first}
  3938. and continuing up to and including @var{last}.
  3939. Providing a @var{last} sector of @option{last}
  3940. specifies "to the end of the flash bank".
  3941. The @var{num} parameter is a value shown by @command{flash banks}.
  3942. @end deffn
  3943. @deffn Command {flash padded_value} num value
  3944. Sets the default value used for padding any image sections, This should
  3945. normally match the flash bank erased value. If not specified by this
  3946. comamnd or the flash driver then it defaults to 0xff.
  3947. @end deffn
  3948. @anchor{program}
  3949. @deffn Command {program} filename [verify] [reset] [exit] [offset]
  3950. This is a helper script that simplifies using OpenOCD as a standalone
  3951. programmer. The only required parameter is @option{filename}, the others are optional.
  3952. @xref{Flash Programming}.
  3953. @end deffn
  3954. @anchor{flashdriverlist}
  3955. @section Flash Driver List
  3956. As noted above, the @command{flash bank} command requires a driver name,
  3957. and allows driver-specific options and behaviors.
  3958. Some drivers also activate driver-specific commands.
  3959. @deffn {Flash Driver} virtual
  3960. This is a special driver that maps a previously defined bank to another
  3961. address. All bank settings will be copied from the master physical bank.
  3962. The @var{virtual} driver defines one mandatory parameters,
  3963. @itemize
  3964. @item @var{master_bank} The bank that this virtual address refers to.
  3965. @end itemize
  3966. So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
  3967. the flash bank defined at address 0x1fc00000. Any cmds executed on
  3968. the virtual banks are actually performed on the physical banks.
  3969. @example
  3970. flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  3971. flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  3972. flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  3973. @end example
  3974. @end deffn
  3975. @subsection External Flash
  3976. @deffn {Flash Driver} cfi
  3977. @cindex Common Flash Interface
  3978. @cindex CFI
  3979. The ``Common Flash Interface'' (CFI) is the main standard for
  3980. external NOR flash chips, each of which connects to a
  3981. specific external chip select on the CPU.
  3982. Frequently the first such chip is used to boot the system.
  3983. Your board's @code{reset-init} handler might need to
  3984. configure additional chip selects using other commands (like: @command{mww} to
  3985. configure a bus and its timings), or
  3986. perhaps configure a GPIO pin that controls the ``write protect'' pin
  3987. on the flash chip.
  3988. The CFI driver can use a target-specific working area to significantly
  3989. speed up operation.
  3990. The CFI driver can accept the following optional parameters, in any order:
  3991. @itemize
  3992. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  3993. like AM29LV010 and similar types.
  3994. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  3995. @end itemize
  3996. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  3997. wide on a sixteen bit bus:
  3998. @example
  3999. flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  4000. flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  4001. @end example
  4002. To configure one bank of 32 MBytes
  4003. built from two sixteen bit (two byte) wide parts wired in parallel
  4004. to create a thirty-two bit (four byte) bus with doubled throughput:
  4005. @example
  4006. flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  4007. @end example
  4008. @c "cfi part_id" disabled
  4009. @end deffn
  4010. @deffn {Flash Driver} lpcspifi
  4011. @cindex NXP SPI Flash Interface
  4012. @cindex SPIFI
  4013. @cindex lpcspifi
  4014. NXP's LPC43xx and LPC18xx families include a proprietary SPI
  4015. Flash Interface (SPIFI) peripheral that can drive and provide
  4016. memory mapped access to external SPI flash devices.
  4017. The lpcspifi driver initializes this interface and provides
  4018. program and erase functionality for these serial flash devices.
  4019. Use of this driver @b{requires} a working area of at least 1kB
  4020. to be configured on the target device; more than this will
  4021. significantly reduce flash programming times.
  4022. The setup command only requires the @var{base} parameter. All
  4023. other parameters are ignored, and the flash size and layout
  4024. are configured by the driver.
  4025. @example
  4026. flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
  4027. @end example
  4028. @end deffn
  4029. @deffn {Flash Driver} stmsmi
  4030. @cindex STMicroelectronics Serial Memory Interface
  4031. @cindex SMI
  4032. @cindex stmsmi
  4033. Some devices form STMicroelectronics (e.g. STR75x MCU family,
  4034. SPEAr MPU family) include a proprietary
  4035. ``Serial Memory Interface'' (SMI) controller able to drive external
  4036. SPI flash devices.
  4037. Depending on specific device and board configuration, up to 4 external
  4038. flash devices can be connected.
  4039. SMI makes the flash content directly accessible in the CPU address
  4040. space; each external device is mapped in a memory bank.
  4041. CPU can directly read data, execute code and boot from SMI banks.
  4042. Normal OpenOCD commands like @command{mdw} can be used to display
  4043. the flash content.
  4044. The setup command only requires the @var{base} parameter in order
  4045. to identify the memory bank.
  4046. All other parameters are ignored. Additional information, like
  4047. flash size, are detected automatically.
  4048. @example
  4049. flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  4050. @end example
  4051. @end deffn
  4052. @deffn {Flash Driver} mrvlqspi
  4053. This driver supports QSPI flash controller of Marvell's Wireless
  4054. Microcontroller platform.
  4055. The flash size is autodetected based on the table of known JEDEC IDs
  4056. hardcoded in the OpenOCD sources.
  4057. @example
  4058. flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
  4059. @end example
  4060. @end deffn
  4061. @subsection Internal Flash (Microcontrollers)
  4062. @deffn {Flash Driver} aduc702x
  4063. The ADUC702x analog microcontrollers from Analog Devices
  4064. include internal flash and use ARM7TDMI cores.
  4065. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  4066. The setup command only requires the @var{target} argument
  4067. since all devices in this family have the same memory layout.
  4068. @example
  4069. flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
  4070. @end example
  4071. @end deffn
  4072. @anchor{at91samd}
  4073. @deffn {Flash Driver} at91samd
  4074. @cindex at91samd
  4075. @deffn Command {at91samd chip-erase}
  4076. Issues a complete Flash erase via the Device Service Unit (DSU). This can be
  4077. used to erase a chip back to its factory state and does not require the
  4078. processor to be halted.
  4079. @end deffn
  4080. @deffn Command {at91samd set-security}
  4081. Secures the Flash via the Set Security Bit (SSB) command. This prevents access
  4082. to the Flash and can only be undone by using the chip-erase command which
  4083. erases the Flash contents and turns off the security bit. Warning: at this
  4084. time, openocd will not be able to communicate with a secured chip and it is
  4085. therefore not possible to chip-erase it without using another tool.
  4086. @example
  4087. at91samd set-security enable
  4088. @end example
  4089. @end deffn
  4090. @deffn Command {at91samd eeprom}
  4091. Shows or sets the EEPROM emulation size configuration, stored in the User Row
  4092. of the Flash. When setting, the EEPROM size must be specified in bytes and it
  4093. must be one of the permitted sizes according to the datasheet. Settings are
  4094. written immediately but only take effect on MCU reset. EEPROM emulation
  4095. requires additional firmware support and the minumum EEPROM size may not be
  4096. the same as the minimum that the hardware supports. Set the EEPROM size to 0
  4097. in order to disable this feature.
  4098. @example
  4099. at91samd eeprom
  4100. at91samd eeprom 1024
  4101. @end example
  4102. @end deffn
  4103. @deffn Command {at91samd bootloader}
  4104. Shows or sets the bootloader size configuration, stored in the User Row of the
  4105. Flash. This is called the BOOTPROT region. When setting, the bootloader size
  4106. must be specified in bytes and it must be one of the permitted sizes according
  4107. to the datasheet. Settings are written immediately but only take effect on
  4108. MCU reset. Setting the bootloader size to 0 disables bootloader protection.
  4109. @example
  4110. at91samd bootloader
  4111. at91samd bootloader 16384
  4112. @end example
  4113. @end deffn
  4114. @end deffn
  4115. @anchor{at91sam3}
  4116. @deffn {Flash Driver} at91sam3
  4117. @cindex at91sam3
  4118. All members of the AT91SAM3 microcontroller family from
  4119. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  4120. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  4121. that the driver was orginaly developed and tested using the
  4122. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  4123. the family was cribbed from the data sheet. @emph{Note to future
  4124. readers/updaters: Please remove this worrysome comment after other
  4125. chips are confirmed.}
  4126. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  4127. have one flash bank. In all cases the flash banks are at
  4128. the following fixed locations:
  4129. @example
  4130. # Flash bank 0 - all chips
  4131. flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
  4132. # Flash bank 1 - only 256K chips
  4133. flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
  4134. @end example
  4135. Internally, the AT91SAM3 flash memory is organized as follows.
  4136. Unlike the AT91SAM7 chips, these are not used as parameters
  4137. to the @command{flash bank} command:
  4138. @itemize
  4139. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  4140. @item @emph{Bank Size:} 128K/64K Per flash bank
  4141. @item @emph{Sectors:} 16 or 8 per bank
  4142. @item @emph{SectorSize:} 8K Per Sector
  4143. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  4144. @end itemize
  4145. The AT91SAM3 driver adds some additional commands:
  4146. @deffn Command {at91sam3 gpnvm}
  4147. @deffnx Command {at91sam3 gpnvm clear} number
  4148. @deffnx Command {at91sam3 gpnvm set} number
  4149. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  4150. With no parameters, @command{show} or @command{show all},
  4151. shows the status of all GPNVM bits.
  4152. With @command{show} @var{number}, displays that bit.
  4153. With @command{set} @var{number} or @command{clear} @var{number},
  4154. modifies that GPNVM bit.
  4155. @end deffn
  4156. @deffn Command {at91sam3 info}
  4157. This command attempts to display information about the AT91SAM3
  4158. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  4159. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  4160. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  4161. various clock configuration registers and attempts to display how it
  4162. believes the chip is configured. By default, the SLOWCLK is assumed to
  4163. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  4164. @end deffn
  4165. @deffn Command {at91sam3 slowclk} [value]
  4166. This command shows/sets the slow clock frequency used in the
  4167. @command{at91sam3 info} command calculations above.
  4168. @end deffn
  4169. @end deffn
  4170. @deffn {Flash Driver} at91sam4
  4171. @cindex at91sam4
  4172. All members of the AT91SAM4 microcontroller family from
  4173. Atmel include internal flash and use ARM's Cortex-M4 core.
  4174. This driver uses the same cmd names/syntax as @xref{at91sam3}.
  4175. @end deffn
  4176. @deffn {Flash Driver} at91sam4l
  4177. @cindex at91sam4l
  4178. All members of the AT91SAM4L microcontroller family from
  4179. Atmel include internal flash and use ARM's Cortex-M4 core.
  4180. This driver uses the same cmd names/syntax as @xref{at91sam3}.
  4181. The AT91SAM4L driver adds some additional commands:
  4182. @deffn Command {at91sam4l smap_reset_deassert}
  4183. This command releases internal reset held by SMAP
  4184. and prepares reset vector catch in case of reset halt.
  4185. Command is used internally in event event reset-deassert-post.
  4186. @end deffn
  4187. @end deffn
  4188. @deffn {Flash Driver} at91sam7
  4189. All members of the AT91SAM7 microcontroller family from Atmel include
  4190. internal flash and use ARM7TDMI cores. The driver automatically
  4191. recognizes a number of these chips using the chip identification
  4192. register, and autoconfigures itself.
  4193. @example
  4194. flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
  4195. @end example
  4196. For chips which are not recognized by the controller driver, you must
  4197. provide additional parameters in the following order:
  4198. @itemize
  4199. @item @var{chip_model} ... label used with @command{flash info}
  4200. @item @var{banks}
  4201. @item @var{sectors_per_bank}
  4202. @item @var{pages_per_sector}
  4203. @item @var{pages_size}
  4204. @item @var{num_nvm_bits}
  4205. @item @var{freq_khz} ... required if an external clock is provided,
  4206. optional (but recommended) when the oscillator frequency is known
  4207. @end itemize
  4208. It is recommended that you provide zeroes for all of those values
  4209. except the clock frequency, so that everything except that frequency
  4210. will be autoconfigured.
  4211. Knowing the frequency helps ensure correct timings for flash access.
  4212. The flash controller handles erases automatically on a page (128/256 byte)
  4213. basis, so explicit erase commands are not necessary for flash programming.
  4214. However, there is an ``EraseAll`` command that can erase an entire flash
  4215. plane (of up to 256KB), and it will be used automatically when you issue
  4216. @command{flash erase_sector} or @command{flash erase_address} commands.
  4217. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  4218. Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
  4219. bit for the processor. Each processor has a number of such bits,
  4220. used for controlling features such as brownout detection (so they
  4221. are not truly general purpose).
  4222. @quotation Note
  4223. This assumes that the first flash bank (number 0) is associated with
  4224. the appropriate at91sam7 target.
  4225. @end quotation
  4226. @end deffn
  4227. @end deffn
  4228. @deffn {Flash Driver} avr
  4229. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  4230. @emph{The current implementation is incomplete.}
  4231. @comment - defines mass_erase ... pointless given flash_erase_address
  4232. @end deffn
  4233. @deffn {Flash Driver} efm32
  4234. All members of the EFM32 microcontroller family from Energy Micro include
  4235. internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
  4236. a number of these chips using the chip identification register, and
  4237. autoconfigures itself.
  4238. @example
  4239. flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
  4240. @end example
  4241. @emph{The current implementation is incomplete. Unprotecting flash pages is not
  4242. supported.}
  4243. @end deffn
  4244. @deffn {Flash Driver} lpc2000
  4245. This is the driver to support internal flash of all members of the
  4246. LPC11(x)00 and LPC1300 microcontroller families and most members of
  4247. the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
  4248. microcontroller families from NXP.
  4249. @quotation Note
  4250. There are LPC2000 devices which are not supported by the @var{lpc2000}
  4251. driver:
  4252. The LPC2888 is supported by the @var{lpc288x} driver.
  4253. The LPC29xx family is supported by the @var{lpc2900} driver.
  4254. @end quotation
  4255. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  4256. which must appear in the following order:
  4257. @itemize
  4258. @item @var{variant} ... required, may be
  4259. @option{lpc2000_v1} (older LPC21xx and LPC22xx)
  4260. @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  4261. @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
  4262. @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
  4263. LPC43x[2357])
  4264. @option{lpc800} (LPC8xx)
  4265. @option{lpc1100} (LPC11(x)xx and LPC13xx)
  4266. @option{lpc1500} (LPC15xx)
  4267. @option{lpc54100} (LPC541xx)
  4268. @option{lpc4000} (LPC40xx)
  4269. or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
  4270. LPC8xx, LPC13xx, LPC17xx and LPC40xx
  4271. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  4272. at which the core is running
  4273. @item @option{calc_checksum} ... optional (but you probably want to provide this!),
  4274. telling the driver to calculate a valid checksum for the exception vector table.
  4275. @quotation Note
  4276. If you don't provide @option{calc_checksum} when you're writing the vector
  4277. table, the boot ROM will almost certainly ignore your flash image.
  4278. However, if you do provide it,
  4279. with most tool chains @command{verify_image} will fail.
  4280. @end quotation
  4281. @end itemize
  4282. LPC flashes don't require the chip and bus width to be specified.
  4283. @example
  4284. flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  4285. lpc2000_v2 14765 calc_checksum
  4286. @end example
  4287. @deffn {Command} {lpc2000 part_id} bank
  4288. Displays the four byte part identifier associated with
  4289. the specified flash @var{bank}.
  4290. @end deffn
  4291. @end deffn
  4292. @deffn {Flash Driver} lpc288x
  4293. The LPC2888 microcontroller from NXP needs slightly different flash
  4294. support from its lpc2000 siblings.
  4295. The @var{lpc288x} driver defines one mandatory parameter,
  4296. the programming clock rate in Hz.
  4297. LPC flashes don't require the chip and bus width to be specified.
  4298. @example
  4299. flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
  4300. @end example
  4301. @end deffn
  4302. @deffn {Flash Driver} lpc2900
  4303. This driver supports the LPC29xx ARM968E based microcontroller family
  4304. from NXP.
  4305. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  4306. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  4307. sector layout are auto-configured by the driver.
  4308. The driver has one additional mandatory parameter: The CPU clock rate
  4309. (in kHz) at the time the flash operations will take place. Most of the time this
  4310. will not be the crystal frequency, but a higher PLL frequency. The
  4311. @code{reset-init} event handler in the board script is usually the place where
  4312. you start the PLL.
  4313. The driver rejects flashless devices (currently the LPC2930).
  4314. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  4315. It must be handled much more like NAND flash memory, and will therefore be
  4316. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  4317. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  4318. sector needs to be erased or programmed, it is automatically unprotected.
  4319. What is shown as protection status in the @code{flash info} command, is
  4320. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  4321. sector from ever being erased or programmed again. As this is an irreversible
  4322. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  4323. and not by the standard @code{flash protect} command.
  4324. Example for a 125 MHz clock frequency:
  4325. @example
  4326. flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
  4327. @end example
  4328. Some @code{lpc2900}-specific commands are defined. In the following command list,
  4329. the @var{bank} parameter is the bank number as obtained by the
  4330. @code{flash banks} command.
  4331. @deffn Command {lpc2900 signature} bank
  4332. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  4333. content. This is a hardware feature of the flash block, hence the calculation is
  4334. very fast. You may use this to verify the content of a programmed device against
  4335. a known signature.
  4336. Example:
  4337. @example
  4338. lpc2900 signature 0
  4339. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  4340. @end example
  4341. @end deffn
  4342. @deffn Command {lpc2900 read_custom} bank filename
  4343. Reads the 912 bytes of customer information from the flash index sector, and
  4344. saves it to a file in binary format.
  4345. Example:
  4346. @example
  4347. lpc2900 read_custom 0 /path_to/customer_info.bin
  4348. @end example
  4349. @end deffn
  4350. The index sector of the flash is a @emph{write-only} sector. It cannot be
  4351. erased! In order to guard against unintentional write access, all following
  4352. commands need to be preceeded by a successful call to the @code{password}
  4353. command:
  4354. @deffn Command {lpc2900 password} bank password
  4355. You need to use this command right before each of the following commands:
  4356. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  4357. @code{lpc2900 secure_jtag}.
  4358. The password string is fixed to "I_know_what_I_am_doing".
  4359. Example:
  4360. @example
  4361. lpc2900 password 0 I_know_what_I_am_doing
  4362. Potentially dangerous operation allowed in next command!
  4363. @end example
  4364. @end deffn
  4365. @deffn Command {lpc2900 write_custom} bank filename type
  4366. Writes the content of the file into the customer info space of the flash index
  4367. sector. The filetype can be specified with the @var{type} field. Possible values
  4368. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  4369. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  4370. contain a single section, and the contained data length must be exactly
  4371. 912 bytes.
  4372. @quotation Attention
  4373. This cannot be reverted! Be careful!
  4374. @end quotation
  4375. Example:
  4376. @example
  4377. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  4378. @end example
  4379. @end deffn
  4380. @deffn Command {lpc2900 secure_sector} bank first last
  4381. Secures the sector range from @var{first} to @var{last} (including) against
  4382. further program and erase operations. The sector security will be effective
  4383. after the next power cycle.
  4384. @quotation Attention
  4385. This cannot be reverted! Be careful!
  4386. @end quotation
  4387. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  4388. Example:
  4389. @example
  4390. lpc2900 secure_sector 0 1 1
  4391. flash info 0
  4392. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  4393. # 0: 0x00000000 (0x2000 8kB) not protected
  4394. # 1: 0x00002000 (0x2000 8kB) protected
  4395. # 2: 0x00004000 (0x2000 8kB) not protected
  4396. @end example
  4397. @end deffn
  4398. @deffn Command {lpc2900 secure_jtag} bank
  4399. Irreversibly disable the JTAG port. The new JTAG security setting will be
  4400. effective after the next power cycle.
  4401. @quotation Attention
  4402. This cannot be reverted! Be careful!
  4403. @end quotation
  4404. Examples:
  4405. @example
  4406. lpc2900 secure_jtag 0
  4407. @end example
  4408. @end deffn
  4409. @end deffn
  4410. @deffn {Flash Driver} ocl
  4411. This driver is an implementation of the ``on chip flash loader''
  4412. protocol proposed by Pavel Chromy.
  4413. It is a minimalistic command-response protocol intended to be used
  4414. over a DCC when communicating with an internal or external flash
  4415. loader running from RAM. An example implementation for AT91SAM7x is
  4416. available in @file{contrib/loaders/flash/at91sam7x/}.
  4417. @example
  4418. flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
  4419. @end example
  4420. @end deffn
  4421. @deffn {Flash Driver} pic32mx
  4422. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  4423. and integrate flash memory.
  4424. @example
  4425. flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4426. flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
  4427. @end example
  4428. @comment numerous *disabled* commands are defined:
  4429. @comment - chip_erase ... pointless given flash_erase_address
  4430. @comment - lock, unlock ... pointless given protect on/off (yes?)
  4431. @comment - pgm_word ... shouldn't bank be deduced from address??
  4432. Some pic32mx-specific commands are defined:
  4433. @deffn Command {pic32mx pgm_word} address value bank
  4434. Programs the specified 32-bit @var{value} at the given @var{address}
  4435. in the specified chip @var{bank}.
  4436. @end deffn
  4437. @deffn Command {pic32mx unlock} bank
  4438. Unlock and erase specified chip @var{bank}.
  4439. This will remove any Code Protection.
  4440. @end deffn
  4441. @end deffn
  4442. @deffn {Flash Driver} psoc4
  4443. All members of the PSoC 41xx/42xx microcontroller family from Cypress
  4444. include internal flash and use ARM Cortex M0 cores.
  4445. The driver automatically recognizes a number of these chips using
  4446. the chip identification register, and autoconfigures itself.
  4447. Note: Erased internal flash reads as 00.
  4448. System ROM of PSoC 4 does not implement erase of a flash sector.
  4449. @example
  4450. flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
  4451. @end example
  4452. psoc4-specific commands
  4453. @deffn Command {psoc4 flash_autoerase} num (on|off)
  4454. Enables or disables autoerase mode for a flash bank.
  4455. If flash_autoerase is off, use mass_erase before flash programming.
  4456. Flash erase command fails if region to erase is not whole flash memory.
  4457. If flash_autoerase is on, a sector is both erased and programmed in one
  4458. system ROM call. Flash erase command is ignored.
  4459. This mode is suitable for gdb load.
  4460. The @var{num} parameter is a value shown by @command{flash banks}.
  4461. @end deffn
  4462. @deffn Command {psoc4 mass_erase} num
  4463. Erases the contents of the flash memory, protection and security lock.
  4464. The @var{num} parameter is a value shown by @command{flash banks}.
  4465. @end deffn
  4466. @end deffn
  4467. @deffn {Flash Driver} stellaris
  4468. All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
  4469. families from Texas Instruments include internal flash. The driver
  4470. automatically recognizes a number of these chips using the chip
  4471. identification register, and autoconfigures itself.
  4472. @footnote{Currently there is a @command{stellaris mass_erase} command.
  4473. That seems pointless since the same effect can be had using the
  4474. standard @command{flash erase_address} command.}
  4475. @example
  4476. flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
  4477. @end example
  4478. @deffn Command {stellaris recover}
  4479. Performs the @emph{Recovering a "Locked" Device} procedure to restore
  4480. the flash and its associated nonvolatile registers to their factory
  4481. default values (erased). This is the only way to remove flash
  4482. protection or re-enable debugging if that capability has been
  4483. disabled.
  4484. Note that the final "power cycle the chip" step in this procedure
  4485. must be performed by hand, since OpenOCD can't do it.
  4486. @quotation Warning
  4487. if more than one Stellaris chip is connected, the procedure is
  4488. applied to all of them.
  4489. @end quotation
  4490. @end deffn
  4491. @end deffn
  4492. @deffn {Flash Driver} stm32f1x
  4493. All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
  4494. from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
  4495. The driver automatically recognizes a number of these chips using
  4496. the chip identification register, and autoconfigures itself.
  4497. @example
  4498. flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  4499. @end example
  4500. Note that some devices have been found that have a flash size register that contains
  4501. an invalid value, to workaround this issue you can override the probed value used by
  4502. the flash driver.
  4503. @example
  4504. flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
  4505. @end example
  4506. If you have a target with dual flash banks then define the second bank
  4507. as per the following example.
  4508. @example
  4509. flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
  4510. @end example
  4511. Some stm32f1x-specific commands
  4512. @footnote{Currently there is a @command{stm32f1x mass_erase} command.
  4513. That seems pointless since the same effect can be had using the
  4514. standard @command{flash erase_address} command.}
  4515. are defined:
  4516. @deffn Command {stm32f1x lock} num
  4517. Locks the entire stm32 device.
  4518. The @var{num} parameter is a value shown by @command{flash banks}.
  4519. @end deffn
  4520. @deffn Command {stm32f1x unlock} num
  4521. Unlocks the entire stm32 device.
  4522. The @var{num} parameter is a value shown by @command{flash banks}.
  4523. @end deffn
  4524. @deffn Command {stm32f1x options_read} num
  4525. Read and display the stm32 option bytes written by
  4526. the @command{stm32f1x options_write} command.
  4527. The @var{num} parameter is a value shown by @command{flash banks}.
  4528. @end deffn
  4529. @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  4530. Writes the stm32 option byte with the specified values.
  4531. The @var{num} parameter is a value shown by @command{flash banks}.
  4532. @end deffn
  4533. @end deffn
  4534. @deffn {Flash Driver} stm32f2x
  4535. All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
  4536. include internal flash and use ARM Cortex-M3/M4 cores.
  4537. The driver automatically recognizes a number of these chips using
  4538. the chip identification register, and autoconfigures itself.
  4539. Note that some devices have been found that have a flash size register that contains
  4540. an invalid value, to workaround this issue you can override the probed value used by
  4541. the flash driver.
  4542. @example
  4543. flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
  4544. @end example
  4545. Some stm32f2x-specific commands are defined:
  4546. @deffn Command {stm32f2x lock} num
  4547. Locks the entire stm32 device.
  4548. The @var{num} parameter is a value shown by @command{flash banks}.
  4549. @end deffn
  4550. @deffn Command {stm32f2x unlock} num
  4551. Unlocks the entire stm32 device.
  4552. The @var{num} parameter is a value shown by @command{flash banks}.
  4553. @end deffn
  4554. @end deffn
  4555. @deffn {Flash Driver} stm32lx
  4556. All members of the STM32L microcontroller families from ST Microelectronics
  4557. include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
  4558. The driver automatically recognizes a number of these chips using
  4559. the chip identification register, and autoconfigures itself.
  4560. Note that some devices have been found that have a flash size register that contains
  4561. an invalid value, to workaround this issue you can override the probed value used by
  4562. the flash driver. If you use 0 as the bank base address, it tells the
  4563. driver to autodetect the bank location assuming you're configuring the
  4564. second bank.
  4565. @example
  4566. flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
  4567. @end example
  4568. Some stm32lx-specific commands are defined:
  4569. @deffn Command {stm32lx mass_erase} num
  4570. Mass erases the entire stm32lx device (all flash banks and EEPROM
  4571. data). This is the only way to unlock a protected flash (unless RDP
  4572. Level is 2 which can't be unlocked at all).
  4573. The @var{num} parameter is a value shown by @command{flash banks}.
  4574. @end deffn
  4575. @end deffn
  4576. @deffn {Flash Driver} str7x
  4577. All members of the STR7 microcontroller family from ST Microelectronics
  4578. include internal flash and use ARM7TDMI cores.
  4579. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  4580. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  4581. @example
  4582. flash bank $_FLASHNAME str7x \
  4583. 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  4584. @end example
  4585. @deffn Command {str7x disable_jtag} bank
  4586. Activate the Debug/Readout protection mechanism
  4587. for the specified flash bank.
  4588. @end deffn
  4589. @end deffn
  4590. @deffn {Flash Driver} str9x
  4591. Most members of the STR9 microcontroller family from ST Microelectronics
  4592. include internal flash and use ARM966E cores.
  4593. The str9 needs the flash controller to be configured using
  4594. the @command{str9x flash_config} command prior to Flash programming.
  4595. @example
  4596. flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  4597. str9x flash_config 0 4 2 0 0x80000
  4598. @end example
  4599. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  4600. Configures the str9 flash controller.
  4601. The @var{num} parameter is a value shown by @command{flash banks}.
  4602. @itemize @bullet
  4603. @item @var{bbsr} - Boot Bank Size register
  4604. @item @var{nbbsr} - Non Boot Bank Size register
  4605. @item @var{bbadr} - Boot Bank Start Address register
  4606. @item @var{nbbadr} - Boot Bank Start Address register
  4607. @end itemize
  4608. @end deffn
  4609. @end deffn
  4610. @deffn {Flash Driver} str9xpec
  4611. @cindex str9xpec
  4612. Only use this driver for locking/unlocking the device or configuring the option bytes.
  4613. Use the standard str9 driver for programming.
  4614. Before using the flash commands the turbo mode must be enabled using the
  4615. @command{str9xpec enable_turbo} command.
  4616. Here is some background info to help
  4617. you better understand how this driver works. OpenOCD has two flash drivers for
  4618. the str9:
  4619. @enumerate
  4620. @item
  4621. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  4622. flash programming as it is faster than the @option{str9xpec} driver.
  4623. @item
  4624. Direct programming @option{str9xpec} using the flash controller. This is an
  4625. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  4626. core does not need to be running to program using this flash driver. Typical use
  4627. for this driver is locking/unlocking the target and programming the option bytes.
  4628. @end enumerate
  4629. Before we run any commands using the @option{str9xpec} driver we must first disable
  4630. the str9 core. This example assumes the @option{str9xpec} driver has been
  4631. configured for flash bank 0.
  4632. @example
  4633. # assert srst, we do not want core running
  4634. # while accessing str9xpec flash driver
  4635. jtag_reset 0 1
  4636. # turn off target polling
  4637. poll off
  4638. # disable str9 core
  4639. str9xpec enable_turbo 0
  4640. # read option bytes
  4641. str9xpec options_read 0
  4642. # re-enable str9 core
  4643. str9xpec disable_turbo 0
  4644. poll on
  4645. reset halt
  4646. @end example
  4647. The above example will read the str9 option bytes.
  4648. When performing a unlock remember that you will not be able to halt the str9 - it
  4649. has been locked. Halting the core is not required for the @option{str9xpec} driver
  4650. as mentioned above, just issue the commands above manually or from a telnet prompt.
  4651. Several str9xpec-specific commands are defined:
  4652. @deffn Command {str9xpec disable_turbo} num
  4653. Restore the str9 into JTAG chain.
  4654. @end deffn
  4655. @deffn Command {str9xpec enable_turbo} num
  4656. Enable turbo mode, will simply remove the str9 from the chain and talk
  4657. directly to the embedded flash controller.
  4658. @end deffn
  4659. @deffn Command {str9xpec lock} num
  4660. Lock str9 device. The str9 will only respond to an unlock command that will
  4661. erase the device.
  4662. @end deffn
  4663. @deffn Command {str9xpec part_id} num
  4664. Prints the part identifier for bank @var{num}.
  4665. @end deffn
  4666. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  4667. Configure str9 boot bank.
  4668. @end deffn
  4669. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  4670. Configure str9 lvd source.
  4671. @end deffn
  4672. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  4673. Configure str9 lvd threshold.
  4674. @end deffn
  4675. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  4676. Configure str9 lvd reset warning source.
  4677. @end deffn
  4678. @deffn Command {str9xpec options_read} num
  4679. Read str9 option bytes.
  4680. @end deffn
  4681. @deffn Command {str9xpec options_write} num
  4682. Write str9 option bytes.
  4683. @end deffn
  4684. @deffn Command {str9xpec unlock} num
  4685. unlock str9 device.
  4686. @end deffn
  4687. @end deffn
  4688. @deffn {Flash Driver} tms470
  4689. Most members of the TMS470 microcontroller family from Texas Instruments
  4690. include internal flash and use ARM7TDMI cores.
  4691. This driver doesn't require the chip and bus width to be specified.
  4692. Some tms470-specific commands are defined:
  4693. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  4694. Saves programming keys in a register, to enable flash erase and write commands.
  4695. @end deffn
  4696. @deffn Command {tms470 osc_mhz} clock_mhz
  4697. Reports the clock speed, which is used to calculate timings.
  4698. @end deffn
  4699. @deffn Command {tms470 plldis} (0|1)
  4700. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  4701. the flash clock.
  4702. @end deffn
  4703. @end deffn
  4704. @deffn {Flash Driver} fm3
  4705. All members of the FM3 microcontroller family from Fujitsu
  4706. include internal flash and use ARM Cortex M3 cores.
  4707. The @var{fm3} driver uses the @var{target} parameter to select the
  4708. correct bank config, it can currently be one of the following:
  4709. @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
  4710. @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
  4711. @example
  4712. flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
  4713. @end example
  4714. @end deffn
  4715. @deffn {Flash Driver} sim3x
  4716. All members of the SiM3 microcontroller family from Silicon Laboratories
  4717. include internal flash and use ARM Cortex M3 cores. It supports both JTAG
  4718. and SWD interface.
  4719. The @var{sim3x} driver tries to probe the device to auto detect the MCU.
  4720. If this failes, it will use the @var{size} parameter as the size of flash bank.
  4721. @example
  4722. flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
  4723. @end example
  4724. There are 2 commands defined in the @var{sim3x} driver:
  4725. @deffn Command {sim3x mass_erase}
  4726. Erases the complete flash. This is used to unlock the flash.
  4727. And this command is only possible when using the SWD interface.
  4728. @end deffn
  4729. @deffn Command {sim3x lock}
  4730. Lock the flash. To unlock use the @command{sim3x mass_erase} command.
  4731. @end deffn
  4732. @end deffn
  4733. @deffn {Flash Driver} nrf51
  4734. All members of the nRF51 microcontroller families from Nordic Semiconductor
  4735. include internal flash and use ARM Cortex-M0 core.
  4736. @example
  4737. flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
  4738. @end example
  4739. Some nrf51-specific commands are defined:
  4740. @deffn Command {nrf51 mass_erase}
  4741. Erases the contents of the code memory and user information
  4742. configuration registers as well. It must be noted that this command
  4743. works only for chips that do not have factory pre-programmed region 0
  4744. code.
  4745. @end deffn
  4746. @end deffn
  4747. @deffn {Flash Driver} mdr
  4748. This drivers handles the integrated NOR flash on Milandr Cortex-M
  4749. based controllers. A known limitation is that the Info memory can't be
  4750. read or verified as it's not memory mapped.
  4751. @example
  4752. flash bank <name> mdr <base> <size> \
  4753. 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
  4754. @end example
  4755. @itemize @bullet
  4756. @item @var{type} - 0 for main memory, 1 for info memory
  4757. @item @var{page_count} - total number of pages
  4758. @item @var{sec_count} - number of sector per page count
  4759. @end itemize
  4760. Example usage:
  4761. @example
  4762. if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
  4763. flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
  4764. 0 0 $_TARGETNAME 1 1 4
  4765. @} else @{
  4766. flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
  4767. 0 0 $_TARGETNAME 0 32 4
  4768. @}
  4769. @end example
  4770. @end deffn
  4771. @section NAND Flash Commands
  4772. @cindex NAND
  4773. Compared to NOR or SPI flash, NAND devices are inexpensive
  4774. and high density. Today's NAND chips, and multi-chip modules,
  4775. commonly hold multiple GigaBytes of data.
  4776. NAND chips consist of a number of ``erase blocks'' of a given
  4777. size (such as 128 KBytes), each of which is divided into a
  4778. number of pages (of perhaps 512 or 2048 bytes each). Each
  4779. page of a NAND flash has an ``out of band'' (OOB) area to hold
  4780. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  4781. of OOB for every 512 bytes of page data.
  4782. One key characteristic of NAND flash is that its error rate
  4783. is higher than that of NOR flash. In normal operation, that
  4784. ECC is used to correct and detect errors. However, NAND
  4785. blocks can also wear out and become unusable; those blocks
  4786. are then marked "bad". NAND chips are even shipped from the
  4787. manufacturer with a few bad blocks. The highest density chips
  4788. use a technology (MLC) that wears out more quickly, so ECC
  4789. support is increasingly important as a way to detect blocks
  4790. that have begun to fail, and help to preserve data integrity
  4791. with techniques such as wear leveling.
  4792. Software is used to manage the ECC. Some controllers don't
  4793. support ECC directly; in those cases, software ECC is used.
  4794. Other controllers speed up the ECC calculations with hardware.
  4795. Single-bit error correction hardware is routine. Controllers
  4796. geared for newer MLC chips may correct 4 or more errors for
  4797. every 512 bytes of data.
  4798. You will need to make sure that any data you write using
  4799. OpenOCD includes the apppropriate kind of ECC. For example,
  4800. that may mean passing the @code{oob_softecc} flag when
  4801. writing NAND data, or ensuring that the correct hardware
  4802. ECC mode is used.
  4803. The basic steps for using NAND devices include:
  4804. @enumerate
  4805. @item Declare via the command @command{nand device}
  4806. @* Do this in a board-specific configuration file,
  4807. passing parameters as needed by the controller.
  4808. @item Configure each device using @command{nand probe}.
  4809. @* Do this only after the associated target is set up,
  4810. such as in its reset-init script or in procures defined
  4811. to access that device.
  4812. @item Operate on the flash via @command{nand subcommand}
  4813. @* Often commands to manipulate the flash are typed by a human, or run
  4814. via a script in some automated way. Common task include writing a
  4815. boot loader, operating system, or other data needed to initialize or
  4816. de-brick a board.
  4817. @end enumerate
  4818. @b{NOTE:} At the time this text was written, the largest NAND
  4819. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  4820. This is because the variables used to hold offsets and lengths
  4821. are only 32 bits wide.
  4822. (Larger chips may work in some cases, unless an offset or length
  4823. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  4824. Some larger devices will work, since they are actually multi-chip
  4825. modules with two smaller chips and individual chipselect lines.
  4826. @anchor{nandconfiguration}
  4827. @subsection NAND Configuration Commands
  4828. @cindex NAND configuration
  4829. NAND chips must be declared in configuration scripts,
  4830. plus some additional configuration that's done after
  4831. OpenOCD has initialized.
  4832. @deffn {Config Command} {nand device} name driver target [configparams...]
  4833. Declares a NAND device, which can be read and written to
  4834. after it has been configured through @command{nand probe}.
  4835. In OpenOCD, devices are single chips; this is unlike some
  4836. operating systems, which may manage multiple chips as if
  4837. they were a single (larger) device.
  4838. In some cases, configuring a device will activate extra
  4839. commands; see the controller-specific documentation.
  4840. @b{NOTE:} This command is not available after OpenOCD
  4841. initialization has completed. Use it in board specific
  4842. configuration files, not interactively.
  4843. @itemize @bullet
  4844. @item @var{name} ... may be used to reference the NAND bank
  4845. in most other NAND commands. A number is also available.
  4846. @item @var{driver} ... identifies the NAND controller driver
  4847. associated with the NAND device being declared.
  4848. @xref{nanddriverlist,,NAND Driver List}.
  4849. @item @var{target} ... names the target used when issuing
  4850. commands to the NAND controller.
  4851. @comment Actually, it's currently a controller-specific parameter...
  4852. @item @var{configparams} ... controllers may support, or require,
  4853. additional parameters. See the controller-specific documentation
  4854. for more information.
  4855. @end itemize
  4856. @end deffn
  4857. @deffn Command {nand list}
  4858. Prints a summary of each device declared
  4859. using @command{nand device}, numbered from zero.
  4860. Note that un-probed devices show no details.
  4861. @example
  4862. > nand list
  4863. #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4864. blocksize: 131072, blocks: 8192
  4865. #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4866. blocksize: 131072, blocks: 8192
  4867. >
  4868. @end example
  4869. @end deffn
  4870. @deffn Command {nand probe} num
  4871. Probes the specified device to determine key characteristics
  4872. like its page and block sizes, and how many blocks it has.
  4873. The @var{num} parameter is the value shown by @command{nand list}.
  4874. You must (successfully) probe a device before you can use
  4875. it with most other NAND commands.
  4876. @end deffn
  4877. @subsection Erasing, Reading, Writing to NAND Flash
  4878. @deffn Command {nand dump} num filename offset length [oob_option]
  4879. @cindex NAND reading
  4880. Reads binary data from the NAND device and writes it to the file,
  4881. starting at the specified offset.
  4882. The @var{num} parameter is the value shown by @command{nand list}.
  4883. Use a complete path name for @var{filename}, so you don't depend
  4884. on the directory used to start the OpenOCD server.
  4885. The @var{offset} and @var{length} must be exact multiples of the
  4886. device's page size. They describe a data region; the OOB data
  4887. associated with each such page may also be accessed.
  4888. @b{NOTE:} At the time this text was written, no error correction
  4889. was done on the data that's read, unless raw access was disabled
  4890. and the underlying NAND controller driver had a @code{read_page}
  4891. method which handled that error correction.
  4892. By default, only page data is saved to the specified file.
  4893. Use an @var{oob_option} parameter to save OOB data:
  4894. @itemize @bullet
  4895. @item no oob_* parameter
  4896. @*Output file holds only page data; OOB is discarded.
  4897. @item @code{oob_raw}
  4898. @*Output file interleaves page data and OOB data;
  4899. the file will be longer than "length" by the size of the
  4900. spare areas associated with each data page.
  4901. Note that this kind of "raw" access is different from
  4902. what's implied by @command{nand raw_access}, which just
  4903. controls whether a hardware-aware access method is used.
  4904. @item @code{oob_only}
  4905. @*Output file has only raw OOB data, and will
  4906. be smaller than "length" since it will contain only the
  4907. spare areas associated with each data page.
  4908. @end itemize
  4909. @end deffn
  4910. @deffn Command {nand erase} num [offset length]
  4911. @cindex NAND erasing
  4912. @cindex NAND programming
  4913. Erases blocks on the specified NAND device, starting at the
  4914. specified @var{offset} and continuing for @var{length} bytes.
  4915. Both of those values must be exact multiples of the device's
  4916. block size, and the region they specify must fit entirely in the chip.
  4917. If those parameters are not specified,
  4918. the whole NAND chip will be erased.
  4919. The @var{num} parameter is the value shown by @command{nand list}.
  4920. @b{NOTE:} This command will try to erase bad blocks, when told
  4921. to do so, which will probably invalidate the manufacturer's bad
  4922. block marker.
  4923. For the remainder of the current server session, @command{nand info}
  4924. will still report that the block ``is'' bad.
  4925. @end deffn
  4926. @deffn Command {nand write} num filename offset [option...]
  4927. @cindex NAND writing
  4928. @cindex NAND programming
  4929. Writes binary data from the file into the specified NAND device,
  4930. starting at the specified offset. Those pages should already
  4931. have been erased; you can't change zero bits to one bits.
  4932. The @var{num} parameter is the value shown by @command{nand list}.
  4933. Use a complete path name for @var{filename}, so you don't depend
  4934. on the directory used to start the OpenOCD server.
  4935. The @var{offset} must be an exact multiple of the device's page size.
  4936. All data in the file will be written, assuming it doesn't run
  4937. past the end of the device.
  4938. Only full pages are written, and any extra space in the last
  4939. page will be filled with 0xff bytes. (That includes OOB data,
  4940. if that's being written.)
  4941. @b{NOTE:} At the time this text was written, bad blocks are
  4942. ignored. That is, this routine will not skip bad blocks,
  4943. but will instead try to write them. This can cause problems.
  4944. Provide at most one @var{option} parameter. With some
  4945. NAND drivers, the meanings of these parameters may change
  4946. if @command{nand raw_access} was used to disable hardware ECC.
  4947. @itemize @bullet
  4948. @item no oob_* parameter
  4949. @*File has only page data, which is written.
  4950. If raw acccess is in use, the OOB area will not be written.
  4951. Otherwise, if the underlying NAND controller driver has
  4952. a @code{write_page} routine, that routine may write the OOB
  4953. with hardware-computed ECC data.
  4954. @item @code{oob_only}
  4955. @*File has only raw OOB data, which is written to the OOB area.
  4956. Each page's data area stays untouched. @i{This can be a dangerous
  4957. option}, since it can invalidate the ECC data.
  4958. You may need to force raw access to use this mode.
  4959. @item @code{oob_raw}
  4960. @*File interleaves data and OOB data, both of which are written
  4961. If raw access is enabled, the data is written first, then the
  4962. un-altered OOB.
  4963. Otherwise, if the underlying NAND controller driver has
  4964. a @code{write_page} routine, that routine may modify the OOB
  4965. before it's written, to include hardware-computed ECC data.
  4966. @item @code{oob_softecc}
  4967. @*File has only page data, which is written.
  4968. The OOB area is filled with 0xff, except for a standard 1-bit
  4969. software ECC code stored in conventional locations.
  4970. You might need to force raw access to use this mode, to prevent
  4971. the underlying driver from applying hardware ECC.
  4972. @item @code{oob_softecc_kw}
  4973. @*File has only page data, which is written.
  4974. The OOB area is filled with 0xff, except for a 4-bit software ECC
  4975. specific to the boot ROM in Marvell Kirkwood SoCs.
  4976. You might need to force raw access to use this mode, to prevent
  4977. the underlying driver from applying hardware ECC.
  4978. @end itemize
  4979. @end deffn
  4980. @deffn Command {nand verify} num filename offset [option...]
  4981. @cindex NAND verification
  4982. @cindex NAND programming
  4983. Verify the binary data in the file has been programmed to the
  4984. specified NAND device, starting at the specified offset.
  4985. The @var{num} parameter is the value shown by @command{nand list}.
  4986. Use a complete path name for @var{filename}, so you don't depend
  4987. on the directory used to start the OpenOCD server.
  4988. The @var{offset} must be an exact multiple of the device's page size.
  4989. All data in the file will be read and compared to the contents of the
  4990. flash, assuming it doesn't run past the end of the device.
  4991. As with @command{nand write}, only full pages are verified, so any extra
  4992. space in the last page will be filled with 0xff bytes.
  4993. The same @var{options} accepted by @command{nand write},
  4994. and the file will be processed similarly to produce the buffers that
  4995. can be compared against the contents produced from @command{nand dump}.
  4996. @b{NOTE:} This will not work when the underlying NAND controller
  4997. driver's @code{write_page} routine must update the OOB with a
  4998. hardward-computed ECC before the data is written. This limitation may
  4999. be removed in a future release.
  5000. @end deffn
  5001. @subsection Other NAND commands
  5002. @cindex NAND other commands
  5003. @deffn Command {nand check_bad_blocks} num [offset length]
  5004. Checks for manufacturer bad block markers on the specified NAND
  5005. device. If no parameters are provided, checks the whole
  5006. device; otherwise, starts at the specified @var{offset} and
  5007. continues for @var{length} bytes.
  5008. Both of those values must be exact multiples of the device's
  5009. block size, and the region they specify must fit entirely in the chip.
  5010. The @var{num} parameter is the value shown by @command{nand list}.
  5011. @b{NOTE:} Before using this command you should force raw access
  5012. with @command{nand raw_access enable} to ensure that the underlying
  5013. driver will not try to apply hardware ECC.
  5014. @end deffn
  5015. @deffn Command {nand info} num
  5016. The @var{num} parameter is the value shown by @command{nand list}.
  5017. This prints the one-line summary from "nand list", plus for
  5018. devices which have been probed this also prints any known
  5019. status for each block.
  5020. @end deffn
  5021. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  5022. Sets or clears an flag affecting how page I/O is done.
  5023. The @var{num} parameter is the value shown by @command{nand list}.
  5024. This flag is cleared (disabled) by default, but changing that
  5025. value won't affect all NAND devices. The key factor is whether
  5026. the underlying driver provides @code{read_page} or @code{write_page}
  5027. methods. If it doesn't provide those methods, the setting of
  5028. this flag is irrelevant; all access is effectively ``raw''.
  5029. When those methods exist, they are normally used when reading
  5030. data (@command{nand dump} or reading bad block markers) or
  5031. writing it (@command{nand write}). However, enabling
  5032. raw access (setting the flag) prevents use of those methods,
  5033. bypassing hardware ECC logic.
  5034. @i{This can be a dangerous option}, since writing blocks
  5035. with the wrong ECC data can cause them to be marked as bad.
  5036. @end deffn
  5037. @anchor{nanddriverlist}
  5038. @subsection NAND Driver List
  5039. As noted above, the @command{nand device} command allows
  5040. driver-specific options and behaviors.
  5041. Some controllers also activate controller-specific commands.
  5042. @deffn {NAND Driver} at91sam9
  5043. This driver handles the NAND controllers found on AT91SAM9 family chips from
  5044. Atmel. It takes two extra parameters: address of the NAND chip;
  5045. address of the ECC controller.
  5046. @example
  5047. nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
  5048. @end example
  5049. AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
  5050. @code{read_page} methods are used to utilize the ECC hardware unless they are
  5051. disabled by using the @command{nand raw_access} command. There are four
  5052. additional commands that are needed to fully configure the AT91SAM9 NAND
  5053. controller. Two are optional; most boards use the same wiring for ALE/CLE:
  5054. @deffn Command {at91sam9 cle} num addr_line
  5055. Configure the address line used for latching commands. The @var{num}
  5056. parameter is the value shown by @command{nand list}.
  5057. @end deffn
  5058. @deffn Command {at91sam9 ale} num addr_line
  5059. Configure the address line used for latching addresses. The @var{num}
  5060. parameter is the value shown by @command{nand list}.
  5061. @end deffn
  5062. For the next two commands, it is assumed that the pins have already been
  5063. properly configured for input or output.
  5064. @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
  5065. Configure the RDY/nBUSY input from the NAND device. The @var{num}
  5066. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  5067. is the base address of the PIO controller and @var{pin} is the pin number.
  5068. @end deffn
  5069. @deffn Command {at91sam9 ce} num pio_base_addr pin
  5070. Configure the chip enable input to the NAND device. The @var{num}
  5071. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  5072. is the base address of the PIO controller and @var{pin} is the pin number.
  5073. @end deffn
  5074. @end deffn
  5075. @deffn {NAND Driver} davinci
  5076. This driver handles the NAND controllers found on DaVinci family
  5077. chips from Texas Instruments.
  5078. It takes three extra parameters:
  5079. address of the NAND chip;
  5080. hardware ECC mode to use (@option{hwecc1},
  5081. @option{hwecc4}, @option{hwecc4_infix});
  5082. address of the AEMIF controller on this processor.
  5083. @example
  5084. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  5085. @end example
  5086. All DaVinci processors support the single-bit ECC hardware,
  5087. and newer ones also support the four-bit ECC hardware.
  5088. The @code{write_page} and @code{read_page} methods are used
  5089. to implement those ECC modes, unless they are disabled using
  5090. the @command{nand raw_access} command.
  5091. @end deffn
  5092. @deffn {NAND Driver} lpc3180
  5093. These controllers require an extra @command{nand device}
  5094. parameter: the clock rate used by the controller.
  5095. @deffn Command {lpc3180 select} num [mlc|slc]
  5096. Configures use of the MLC or SLC controller mode.
  5097. MLC implies use of hardware ECC.
  5098. The @var{num} parameter is the value shown by @command{nand list}.
  5099. @end deffn
  5100. At this writing, this driver includes @code{write_page}
  5101. and @code{read_page} methods. Using @command{nand raw_access}
  5102. to disable those methods will prevent use of hardware ECC
  5103. in the MLC controller mode, but won't change SLC behavior.
  5104. @end deffn
  5105. @comment current lpc3180 code won't issue 5-byte address cycles
  5106. @deffn {NAND Driver} mx3
  5107. This driver handles the NAND controller in i.MX31. The mxc driver
  5108. should work for this chip aswell.
  5109. @end deffn
  5110. @deffn {NAND Driver} mxc
  5111. This driver handles the NAND controller found in Freescale i.MX
  5112. chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
  5113. The driver takes 3 extra arguments, chip (@option{mx27},
  5114. @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
  5115. and optionally if bad block information should be swapped between
  5116. main area and spare area (@option{biswap}), defaults to off.
  5117. @example
  5118. nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
  5119. @end example
  5120. @deffn Command {mxc biswap} bank_num [enable|disable]
  5121. Turns on/off bad block information swaping from main area,
  5122. without parameter query status.
  5123. @end deffn
  5124. @end deffn
  5125. @deffn {NAND Driver} orion
  5126. These controllers require an extra @command{nand device}
  5127. parameter: the address of the controller.
  5128. @example
  5129. nand device orion 0xd8000000
  5130. @end example
  5131. These controllers don't define any specialized commands.
  5132. At this writing, their drivers don't include @code{write_page}
  5133. or @code{read_page} methods, so @command{nand raw_access} won't
  5134. change any behavior.
  5135. @end deffn
  5136. @deffn {NAND Driver} s3c2410
  5137. @deffnx {NAND Driver} s3c2412
  5138. @deffnx {NAND Driver} s3c2440
  5139. @deffnx {NAND Driver} s3c2443
  5140. @deffnx {NAND Driver} s3c6400
  5141. These S3C family controllers don't have any special
  5142. @command{nand device} options, and don't define any
  5143. specialized commands.
  5144. At this writing, their drivers don't include @code{write_page}
  5145. or @code{read_page} methods, so @command{nand raw_access} won't
  5146. change any behavior.
  5147. @end deffn
  5148. @section mFlash
  5149. @subsection mFlash Configuration
  5150. @cindex mFlash Configuration
  5151. @deffn {Config Command} {mflash bank} soc base RST_pin target
  5152. Configures a mflash for @var{soc} host bank at
  5153. address @var{base}.
  5154. The pin number format depends on the host GPIO naming convention.
  5155. Currently, the mflash driver supports s3c2440 and pxa270.
  5156. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  5157. @example
  5158. mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
  5159. @end example
  5160. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  5161. @example
  5162. mflash bank $_FLASHNAME pxa270 0x08000000 43 0
  5163. @end example
  5164. @end deffn
  5165. @subsection mFlash commands
  5166. @cindex mFlash commands
  5167. @deffn Command {mflash config pll} frequency
  5168. Configure mflash PLL.
  5169. The @var{frequency} is the mflash input frequency, in Hz.
  5170. Issuing this command will erase mflash's whole internal nand and write new pll.
  5171. After this command, mflash needs power-on-reset for normal operation.
  5172. If pll was newly configured, storage and boot(optional) info also need to be update.
  5173. @end deffn
  5174. @deffn Command {mflash config boot}
  5175. Configure bootable option.
  5176. If bootable option is set, mflash offer the first 8 sectors
  5177. (4kB) for boot.
  5178. @end deffn
  5179. @deffn Command {mflash config storage}
  5180. Configure storage information.
  5181. For the normal storage operation, this information must be
  5182. written.
  5183. @end deffn
  5184. @deffn Command {mflash dump} num filename offset size
  5185. Dump @var{size} bytes, starting at @var{offset} bytes from the
  5186. beginning of the bank @var{num}, to the file named @var{filename}.
  5187. @end deffn
  5188. @deffn Command {mflash probe}
  5189. Probe mflash.
  5190. @end deffn
  5191. @deffn Command {mflash write} num filename offset
  5192. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  5193. @var{offset} bytes from the beginning of the bank.
  5194. @end deffn
  5195. @node Flash Programming
  5196. @chapter Flash Programming
  5197. OpenOCD implements numerous ways to program the target flash, whether internal or external.
  5198. Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
  5199. or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
  5200. @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
  5201. OpenOCD will program/verify/reset the target and optionally shutdown.
  5202. The script is executed as follows and by default the following actions will be peformed.
  5203. @enumerate
  5204. @item 'init' is executed.
  5205. @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
  5206. @item @code{flash write_image} is called to erase and write any flash using the filename given.
  5207. @item @code{verify_image} is called if @option{verify} parameter is given.
  5208. @item @code{reset run} is called if @option{reset} parameter is given.
  5209. @item OpenOCD is shutdown if @option{exit} parameter is given.
  5210. @end enumerate
  5211. An example of usage is given below. @xref{program}.
  5212. @example
  5213. # program and verify using elf/hex/s19. verify and reset
  5214. # are optional parameters
  5215. openocd -f board/stm32f3discovery.cfg \
  5216. -c "program filename.elf verify reset exit"
  5217. # binary files need the flash address passing
  5218. openocd -f board/stm32f3discovery.cfg \
  5219. -c "program filename.bin exit 0x08000000"
  5220. @end example
  5221. @node PLD/FPGA Commands
  5222. @chapter PLD/FPGA Commands
  5223. @cindex PLD
  5224. @cindex FPGA
  5225. Programmable Logic Devices (PLDs) and the more flexible
  5226. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  5227. OpenOCD can support programming them.
  5228. Although PLDs are generally restrictive (cells are less functional, and
  5229. there are no special purpose cells for memory or computational tasks),
  5230. they share the same OpenOCD infrastructure.
  5231. Accordingly, both are called PLDs here.
  5232. @section PLD/FPGA Configuration and Commands
  5233. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  5234. OpenOCD maintains a list of PLDs available for use in various commands.
  5235. Also, each such PLD requires a driver.
  5236. They are referenced by the number shown by the @command{pld devices} command,
  5237. and new PLDs are defined by @command{pld device driver_name}.
  5238. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  5239. Defines a new PLD device, supported by driver @var{driver_name},
  5240. using the TAP named @var{tap_name}.
  5241. The driver may make use of any @var{driver_options} to configure its
  5242. behavior.
  5243. @end deffn
  5244. @deffn {Command} {pld devices}
  5245. Lists the PLDs and their numbers.
  5246. @end deffn
  5247. @deffn {Command} {pld load} num filename
  5248. Loads the file @file{filename} into the PLD identified by @var{num}.
  5249. The file format must be inferred by the driver.
  5250. @end deffn
  5251. @section PLD/FPGA Drivers, Options, and Commands
  5252. Drivers may support PLD-specific options to the @command{pld device}
  5253. definition command, and may also define commands usable only with
  5254. that particular type of PLD.
  5255. @deffn {FPGA Driver} virtex2
  5256. Virtex-II is a family of FPGAs sold by Xilinx.
  5257. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  5258. No driver-specific PLD definition options are used,
  5259. and one driver-specific command is defined.
  5260. @deffn {Command} {virtex2 read_stat} num
  5261. Reads and displays the Virtex-II status register (STAT)
  5262. for FPGA @var{num}.
  5263. @end deffn
  5264. @end deffn
  5265. @node General Commands
  5266. @chapter General Commands
  5267. @cindex commands
  5268. The commands documented in this chapter here are common commands that
  5269. you, as a human, may want to type and see the output of. Configuration type
  5270. commands are documented elsewhere.
  5271. Intent:
  5272. @itemize @bullet
  5273. @item @b{Source Of Commands}
  5274. @* OpenOCD commands can occur in a configuration script (discussed
  5275. elsewhere) or typed manually by a human or supplied programatically,
  5276. or via one of several TCP/IP Ports.
  5277. @item @b{From the human}
  5278. @* A human should interact with the telnet interface (default port: 4444)
  5279. or via GDB (default port 3333).
  5280. To issue commands from within a GDB session, use the @option{monitor}
  5281. command, e.g. use @option{monitor poll} to issue the @option{poll}
  5282. command. All output is relayed through the GDB session.
  5283. @item @b{Machine Interface}
  5284. The Tcl interface's intent is to be a machine interface. The default Tcl
  5285. port is 5555.
  5286. @end itemize
  5287. @section Daemon Commands
  5288. @deffn {Command} exit
  5289. Exits the current telnet session.
  5290. @end deffn
  5291. @deffn {Command} help [string]
  5292. With no parameters, prints help text for all commands.
  5293. Otherwise, prints each helptext containing @var{string}.
  5294. Not every command provides helptext.
  5295. Configuration commands, and commands valid at any time, are
  5296. explicitly noted in parenthesis.
  5297. In most cases, no such restriction is listed; this indicates commands
  5298. which are only available after the configuration stage has completed.
  5299. @end deffn
  5300. @deffn Command sleep msec [@option{busy}]
  5301. Wait for at least @var{msec} milliseconds before resuming.
  5302. If @option{busy} is passed, busy-wait instead of sleeping.
  5303. (This option is strongly discouraged.)
  5304. Useful in connection with script files
  5305. (@command{script} command and @command{target_name} configuration).
  5306. @end deffn
  5307. @deffn Command shutdown [@option{error}]
  5308. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet,
  5309. other). If option @option{error} is used, OpenOCD will return a
  5310. non-zero exit code to the parent process.
  5311. @end deffn
  5312. @anchor{debuglevel}
  5313. @deffn Command debug_level [n]
  5314. @cindex message level
  5315. Display debug level.
  5316. If @var{n} (from 0..3) is provided, then set it to that level.
  5317. This affects the kind of messages sent to the server log.
  5318. Level 0 is error messages only;
  5319. level 1 adds warnings;
  5320. level 2 adds informational messages;
  5321. and level 3 adds debugging messages.
  5322. The default is level 2, but that can be overridden on
  5323. the command line along with the location of that log
  5324. file (which is normally the server's standard output).
  5325. @xref{Running}.
  5326. @end deffn
  5327. @deffn Command echo [-n] message
  5328. Logs a message at "user" priority.
  5329. Output @var{message} to stdout.
  5330. Option "-n" suppresses trailing newline.
  5331. @example
  5332. echo "Downloading kernel -- please wait"
  5333. @end example
  5334. @end deffn
  5335. @deffn Command log_output [filename]
  5336. Redirect logging to @var{filename};
  5337. the initial log output channel is stderr.
  5338. @end deffn
  5339. @deffn Command add_script_search_dir [directory]
  5340. Add @var{directory} to the file/script search path.
  5341. @end deffn
  5342. @anchor{targetstatehandling}
  5343. @section Target State handling
  5344. @cindex reset
  5345. @cindex halt
  5346. @cindex target initialization
  5347. In this section ``target'' refers to a CPU configured as
  5348. shown earlier (@pxref{CPU Configuration}).
  5349. These commands, like many, implicitly refer to
  5350. a current target which is used to perform the
  5351. various operations. The current target may be changed
  5352. by using @command{targets} command with the name of the
  5353. target which should become current.
  5354. @deffn Command reg [(number|name) [(value|'force')]]
  5355. Access a single register by @var{number} or by its @var{name}.
  5356. The target must generally be halted before access to CPU core
  5357. registers is allowed. Depending on the hardware, some other
  5358. registers may be accessible while the target is running.
  5359. @emph{With no arguments}:
  5360. list all available registers for the current target,
  5361. showing number, name, size, value, and cache status.
  5362. For valid entries, a value is shown; valid entries
  5363. which are also dirty (and will be written back later)
  5364. are flagged as such.
  5365. @emph{With number/name}: display that register's value.
  5366. Use @var{force} argument to read directly from the target,
  5367. bypassing any internal cache.
  5368. @emph{With both number/name and value}: set register's value.
  5369. Writes may be held in a writeback cache internal to OpenOCD,
  5370. so that setting the value marks the register as dirty instead
  5371. of immediately flushing that value. Resuming CPU execution
  5372. (including by single stepping) or otherwise activating the
  5373. relevant module will flush such values.
  5374. Cores may have surprisingly many registers in their
  5375. Debug and trace infrastructure:
  5376. @example
  5377. > reg
  5378. ===== ARM registers
  5379. (0) r0 (/32): 0x0000D3C2 (dirty)
  5380. (1) r1 (/32): 0xFD61F31C
  5381. (2) r2 (/32)
  5382. ...
  5383. (164) ETM_contextid_comparator_mask (/32)
  5384. >
  5385. @end example
  5386. @end deffn
  5387. @deffn Command halt [ms]
  5388. @deffnx Command wait_halt [ms]
  5389. The @command{halt} command first sends a halt request to the target,
  5390. which @command{wait_halt} doesn't.
  5391. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  5392. or 5 seconds if there is no parameter, for the target to halt
  5393. (and enter debug mode).
  5394. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  5395. @quotation Warning
  5396. On ARM cores, software using the @emph{wait for interrupt} operation
  5397. often blocks the JTAG access needed by a @command{halt} command.
  5398. This is because that operation also puts the core into a low
  5399. power mode by gating the core clock;
  5400. but the core clock is needed to detect JTAG clock transitions.
  5401. One partial workaround uses adaptive clocking: when the core is
  5402. interrupted the operation completes, then JTAG clocks are accepted
  5403. at least until the interrupt handler completes.
  5404. However, this workaround is often unusable since the processor, board,
  5405. and JTAG adapter must all support adaptive JTAG clocking.
  5406. Also, it can't work until an interrupt is issued.
  5407. A more complete workaround is to not use that operation while you
  5408. work with a JTAG debugger.
  5409. Tasking environments generaly have idle loops where the body is the
  5410. @emph{wait for interrupt} operation.
  5411. (On older cores, it is a coprocessor action;
  5412. newer cores have a @option{wfi} instruction.)
  5413. Such loops can just remove that operation, at the cost of higher
  5414. power consumption (because the CPU is needlessly clocked).
  5415. @end quotation
  5416. @end deffn
  5417. @deffn Command resume [address]
  5418. Resume the target at its current code position,
  5419. or the optional @var{address} if it is provided.
  5420. OpenOCD will wait 5 seconds for the target to resume.
  5421. @end deffn
  5422. @deffn Command step [address]
  5423. Single-step the target at its current code position,
  5424. or the optional @var{address} if it is provided.
  5425. @end deffn
  5426. @anchor{resetcommand}
  5427. @deffn Command reset
  5428. @deffnx Command {reset run}
  5429. @deffnx Command {reset halt}
  5430. @deffnx Command {reset init}
  5431. Perform as hard a reset as possible, using SRST if possible.
  5432. @emph{All defined targets will be reset, and target
  5433. events will fire during the reset sequence.}
  5434. The optional parameter specifies what should
  5435. happen after the reset.
  5436. If there is no parameter, a @command{reset run} is executed.
  5437. The other options will not work on all systems.
  5438. @xref{Reset Configuration}.
  5439. @itemize @minus
  5440. @item @b{run} Let the target run
  5441. @item @b{halt} Immediately halt the target
  5442. @item @b{init} Immediately halt the target, and execute the reset-init script
  5443. @end itemize
  5444. @end deffn
  5445. @deffn Command soft_reset_halt
  5446. Requesting target halt and executing a soft reset. This is often used
  5447. when a target cannot be reset and halted. The target, after reset is
  5448. released begins to execute code. OpenOCD attempts to stop the CPU and
  5449. then sets the program counter back to the reset vector. Unfortunately
  5450. the code that was executed may have left the hardware in an unknown
  5451. state.
  5452. @end deffn
  5453. @section I/O Utilities
  5454. These commands are available when
  5455. OpenOCD is built with @option{--enable-ioutil}.
  5456. They are mainly useful on embedded targets,
  5457. notably the ZY1000.
  5458. Hosts with operating systems have complementary tools.
  5459. @emph{Note:} there are several more such commands.
  5460. @deffn Command append_file filename [string]*
  5461. Appends the @var{string} parameters to
  5462. the text file @file{filename}.
  5463. Each string except the last one is followed by one space.
  5464. The last string is followed by a newline.
  5465. @end deffn
  5466. @deffn Command cat filename
  5467. Reads and displays the text file @file{filename}.
  5468. @end deffn
  5469. @deffn Command cp src_filename dest_filename
  5470. Copies contents from the file @file{src_filename}
  5471. into @file{dest_filename}.
  5472. @end deffn
  5473. @deffn Command ip
  5474. @emph{No description provided.}
  5475. @end deffn
  5476. @deffn Command ls
  5477. @emph{No description provided.}
  5478. @end deffn
  5479. @deffn Command mac
  5480. @emph{No description provided.}
  5481. @end deffn
  5482. @deffn Command meminfo
  5483. Display available RAM memory on OpenOCD host.
  5484. Used in OpenOCD regression testing scripts.
  5485. @end deffn
  5486. @deffn Command peek
  5487. @emph{No description provided.}
  5488. @end deffn
  5489. @deffn Command poke
  5490. @emph{No description provided.}
  5491. @end deffn
  5492. @deffn Command rm filename
  5493. @c "rm" has both normal and Jim-level versions??
  5494. Unlinks the file @file{filename}.
  5495. @end deffn
  5496. @deffn Command trunc filename
  5497. Removes all data in the file @file{filename}.
  5498. @end deffn
  5499. @anchor{memoryaccess}
  5500. @section Memory access commands
  5501. @cindex memory access
  5502. These commands allow accesses of a specific size to the memory
  5503. system. Often these are used to configure the current target in some
  5504. special way. For example - one may need to write certain values to the
  5505. SDRAM controller to enable SDRAM.
  5506. @enumerate
  5507. @item Use the @command{targets} (plural) command
  5508. to change the current target.
  5509. @item In system level scripts these commands are deprecated.
  5510. Please use their TARGET object siblings to avoid making assumptions
  5511. about what TAP is the current target, or about MMU configuration.
  5512. @end enumerate
  5513. @deffn Command mdw [phys] addr [count]
  5514. @deffnx Command mdh [phys] addr [count]
  5515. @deffnx Command mdb [phys] addr [count]
  5516. Display contents of address @var{addr}, as
  5517. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  5518. or 8-bit bytes (@command{mdb}).
  5519. When the current target has an MMU which is present and active,
  5520. @var{addr} is interpreted as a virtual address.
  5521. Otherwise, or if the optional @var{phys} flag is specified,
  5522. @var{addr} is interpreted as a physical address.
  5523. If @var{count} is specified, displays that many units.
  5524. (If you want to manipulate the data instead of displaying it,
  5525. see the @code{mem2array} primitives.)
  5526. @end deffn
  5527. @deffn Command mww [phys] addr word
  5528. @deffnx Command mwh [phys] addr halfword
  5529. @deffnx Command mwb [phys] addr byte
  5530. Writes the specified @var{word} (32 bits),
  5531. @var{halfword} (16 bits), or @var{byte} (8-bit) value,
  5532. at the specified address @var{addr}.
  5533. When the current target has an MMU which is present and active,
  5534. @var{addr} is interpreted as a virtual address.
  5535. Otherwise, or if the optional @var{phys} flag is specified,
  5536. @var{addr} is interpreted as a physical address.
  5537. @end deffn
  5538. @anchor{imageaccess}
  5539. @section Image loading commands
  5540. @cindex image loading
  5541. @cindex image dumping
  5542. @deffn Command {dump_image} filename address size
  5543. Dump @var{size} bytes of target memory starting at @var{address} to the
  5544. binary file named @var{filename}.
  5545. @end deffn
  5546. @deffn Command {fast_load}
  5547. Loads an image stored in memory by @command{fast_load_image} to the
  5548. current target. Must be preceeded by fast_load_image.
  5549. @end deffn
  5550. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
  5551. Normally you should be using @command{load_image} or GDB load. However, for
  5552. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  5553. host), storing the image in memory and uploading the image to the target
  5554. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  5555. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  5556. memory, i.e. does not affect target. This approach is also useful when profiling
  5557. target programming performance as I/O and target programming can easily be profiled
  5558. separately.
  5559. @end deffn
  5560. @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
  5561. Load image from file @var{filename} to target memory offset by @var{address} from its load address.
  5562. The file format may optionally be specified
  5563. (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
  5564. In addition the following arguments may be specifed:
  5565. @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
  5566. @var{max_length} - maximum number of bytes to load.
  5567. @example
  5568. proc load_image_bin @{fname foffset address length @} @{
  5569. # Load data from fname filename at foffset offset to
  5570. # target at address. Load at most length bytes.
  5571. load_image $fname [expr $address - $foffset] bin \
  5572. $address $length
  5573. @}
  5574. @end example
  5575. @end deffn
  5576. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  5577. Displays image section sizes and addresses
  5578. as if @var{filename} were loaded into target memory
  5579. starting at @var{address} (defaults to zero).
  5580. The file format may optionally be specified
  5581. (@option{bin}, @option{ihex}, or @option{elf})
  5582. @end deffn
  5583. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  5584. Verify @var{filename} against target memory starting at @var{address}.
  5585. The file format may optionally be specified
  5586. (@option{bin}, @option{ihex}, or @option{elf})
  5587. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  5588. @end deffn
  5589. @section Breakpoint and Watchpoint commands
  5590. @cindex breakpoint
  5591. @cindex watchpoint
  5592. CPUs often make debug modules accessible through JTAG, with
  5593. hardware support for a handful of code breakpoints and data
  5594. watchpoints.
  5595. In addition, CPUs almost always support software breakpoints.
  5596. @deffn Command {bp} [address len [@option{hw}]]
  5597. With no parameters, lists all active breakpoints.
  5598. Else sets a breakpoint on code execution starting
  5599. at @var{address} for @var{length} bytes.
  5600. This is a software breakpoint, unless @option{hw} is specified
  5601. in which case it will be a hardware breakpoint.
  5602. (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
  5603. for similar mechanisms that do not consume hardware breakpoints.)
  5604. @end deffn
  5605. @deffn Command {rbp} address
  5606. Remove the breakpoint at @var{address}.
  5607. @end deffn
  5608. @deffn Command {rwp} address
  5609. Remove data watchpoint on @var{address}
  5610. @end deffn
  5611. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  5612. With no parameters, lists all active watchpoints.
  5613. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  5614. The watch point is an "access" watchpoint unless
  5615. the @option{r} or @option{w} parameter is provided,
  5616. defining it as respectively a read or write watchpoint.
  5617. If a @var{value} is provided, that value is used when determining if
  5618. the watchpoint should trigger. The value may be first be masked
  5619. using @var{mask} to mark ``don't care'' fields.
  5620. @end deffn
  5621. @section Misc Commands
  5622. @cindex profiling
  5623. @deffn Command {profile} seconds filename [start end]
  5624. Profiling samples the CPU's program counter as quickly as possible,
  5625. which is useful for non-intrusive stochastic profiling.
  5626. Saves up to 10000 samples in @file{filename} using ``gmon.out''
  5627. format. Optional @option{start} and @option{end} parameters allow to
  5628. limit the address range.
  5629. @end deffn
  5630. @deffn Command {version}
  5631. Displays a string identifying the version of this OpenOCD server.
  5632. @end deffn
  5633. @deffn Command {virt2phys} virtual_address
  5634. Requests the current target to map the specified @var{virtual_address}
  5635. to its corresponding physical address, and displays the result.
  5636. @end deffn
  5637. @node Architecture and Core Commands
  5638. @chapter Architecture and Core Commands
  5639. @cindex Architecture Specific Commands
  5640. @cindex Core Specific Commands
  5641. Most CPUs have specialized JTAG operations to support debugging.
  5642. OpenOCD packages most such operations in its standard command framework.
  5643. Some of those operations don't fit well in that framework, so they are
  5644. exposed here as architecture or implementation (core) specific commands.
  5645. @anchor{armhardwaretracing}
  5646. @section ARM Hardware Tracing
  5647. @cindex tracing
  5648. @cindex ETM
  5649. @cindex ETB
  5650. CPUs based on ARM cores may include standard tracing interfaces,
  5651. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  5652. address and data bus trace records to a ``Trace Port''.
  5653. @itemize
  5654. @item
  5655. Development-oriented boards will sometimes provide a high speed
  5656. trace connector for collecting that data, when the particular CPU
  5657. supports such an interface.
  5658. (The standard connector is a 38-pin Mictor, with both JTAG
  5659. and trace port support.)
  5660. Those trace connectors are supported by higher end JTAG adapters
  5661. and some logic analyzer modules; frequently those modules can
  5662. buffer several megabytes of trace data.
  5663. Configuring an ETM coupled to such an external trace port belongs
  5664. in the board-specific configuration file.
  5665. @item
  5666. If the CPU doesn't provide an external interface, it probably
  5667. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  5668. dedicated SRAM. 4KBytes is one common ETB size.
  5669. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  5670. (target) configuration file, since it works the same on all boards.
  5671. @end itemize
  5672. ETM support in OpenOCD doesn't seem to be widely used yet.
  5673. @quotation Issues
  5674. ETM support may be buggy, and at least some @command{etm config}
  5675. parameters should be detected by asking the ETM for them.
  5676. ETM trigger events could also implement a kind of complex
  5677. hardware breakpoint, much more powerful than the simple
  5678. watchpoint hardware exported by EmbeddedICE modules.
  5679. @emph{Such breakpoints can be triggered even when using the
  5680. dummy trace port driver}.
  5681. It seems like a GDB hookup should be possible,
  5682. as well as tracing only during specific states
  5683. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  5684. There should be GUI tools to manipulate saved trace data and help
  5685. analyse it in conjunction with the source code.
  5686. It's unclear how much of a common interface is shared
  5687. with the current XScale trace support, or should be
  5688. shared with eventual Nexus-style trace module support.
  5689. At this writing (November 2009) only ARM7, ARM9, and ARM11 support
  5690. for ETM modules is available. The code should be able to
  5691. work with some newer cores; but not all of them support
  5692. this original style of JTAG access.
  5693. @end quotation
  5694. @subsection ETM Configuration
  5695. ETM setup is coupled with the trace port driver configuration.
  5696. @deffn {Config Command} {etm config} target width mode clocking driver
  5697. Declares the ETM associated with @var{target}, and associates it
  5698. with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
  5699. Several of the parameters must reflect the trace port capabilities,
  5700. which are a function of silicon capabilties (exposed later
  5701. using @command{etm info}) and of what hardware is connected to
  5702. that port (such as an external pod, or ETB).
  5703. The @var{width} must be either 4, 8, or 16,
  5704. except with ETMv3.0 and newer modules which may also
  5705. support 1, 2, 24, 32, 48, and 64 bit widths.
  5706. (With those versions, @command{etm info} also shows whether
  5707. the selected port width and mode are supported.)
  5708. The @var{mode} must be @option{normal}, @option{multiplexed},
  5709. or @option{demultiplexed}.
  5710. The @var{clocking} must be @option{half} or @option{full}.
  5711. @quotation Warning
  5712. With ETMv3.0 and newer, the bits set with the @var{mode} and
  5713. @var{clocking} parameters both control the mode.
  5714. This modified mode does not map to the values supported by
  5715. previous ETM modules, so this syntax is subject to change.
  5716. @end quotation
  5717. @quotation Note
  5718. You can see the ETM registers using the @command{reg} command.
  5719. Not all possible registers are present in every ETM.
  5720. Most of the registers are write-only, and are used to configure
  5721. what CPU activities are traced.
  5722. @end quotation
  5723. @end deffn
  5724. @deffn Command {etm info}
  5725. Displays information about the current target's ETM.
  5726. This includes resource counts from the @code{ETM_CONFIG} register,
  5727. as well as silicon capabilities (except on rather old modules).
  5728. from the @code{ETM_SYS_CONFIG} register.
  5729. @end deffn
  5730. @deffn Command {etm status}
  5731. Displays status of the current target's ETM and trace port driver:
  5732. is the ETM idle, or is it collecting data?
  5733. Did trace data overflow?
  5734. Was it triggered?
  5735. @end deffn
  5736. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  5737. Displays what data that ETM will collect.
  5738. If arguments are provided, first configures that data.
  5739. When the configuration changes, tracing is stopped
  5740. and any buffered trace data is invalidated.
  5741. @itemize
  5742. @item @var{type} ... describing how data accesses are traced,
  5743. when they pass any ViewData filtering that that was set up.
  5744. The value is one of
  5745. @option{none} (save nothing),
  5746. @option{data} (save data),
  5747. @option{address} (save addresses),
  5748. @option{all} (save data and addresses)
  5749. @item @var{context_id_bits} ... 0, 8, 16, or 32
  5750. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  5751. cycle-accurate instruction tracing.
  5752. Before ETMv3, enabling this causes much extra data to be recorded.
  5753. @item @var{branch_output} ... @option{enable} or @option{disable}.
  5754. Disable this unless you need to try reconstructing the instruction
  5755. trace stream without an image of the code.
  5756. @end itemize
  5757. @end deffn
  5758. @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
  5759. Displays whether ETM triggering debug entry (like a breakpoint) is
  5760. enabled or disabled, after optionally modifying that configuration.
  5761. The default behaviour is @option{disable}.
  5762. Any change takes effect after the next @command{etm start}.
  5763. By using script commands to configure ETM registers, you can make the
  5764. processor enter debug state automatically when certain conditions,
  5765. more complex than supported by the breakpoint hardware, happen.
  5766. @end deffn
  5767. @subsection ETM Trace Operation
  5768. After setting up the ETM, you can use it to collect data.
  5769. That data can be exported to files for later analysis.
  5770. It can also be parsed with OpenOCD, for basic sanity checking.
  5771. To configure what is being traced, you will need to write
  5772. various trace registers using @command{reg ETM_*} commands.
  5773. For the definitions of these registers, read ARM publication
  5774. @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
  5775. Be aware that most of the relevant registers are write-only,
  5776. and that ETM resources are limited. There are only a handful
  5777. of address comparators, data comparators, counters, and so on.
  5778. Examples of scenarios you might arrange to trace include:
  5779. @itemize
  5780. @item Code flow within a function, @emph{excluding} subroutines
  5781. it calls. Use address range comparators to enable tracing
  5782. for instruction access within that function's body.
  5783. @item Code flow within a function, @emph{including} subroutines
  5784. it calls. Use the sequencer and address comparators to activate
  5785. tracing on an ``entered function'' state, then deactivate it by
  5786. exiting that state when the function's exit code is invoked.
  5787. @item Code flow starting at the fifth invocation of a function,
  5788. combining one of the above models with a counter.
  5789. @item CPU data accesses to the registers for a particular device,
  5790. using address range comparators and the ViewData logic.
  5791. @item Such data accesses only during IRQ handling, combining the above
  5792. model with sequencer triggers which on entry and exit to the IRQ handler.
  5793. @item @emph{... more}
  5794. @end itemize
  5795. At this writing, September 2009, there are no Tcl utility
  5796. procedures to help set up any common tracing scenarios.
  5797. @deffn Command {etm analyze}
  5798. Reads trace data into memory, if it wasn't already present.
  5799. Decodes and prints the data that was collected.
  5800. @end deffn
  5801. @deffn Command {etm dump} filename
  5802. Stores the captured trace data in @file{filename}.
  5803. @end deffn
  5804. @deffn Command {etm image} filename [base_address] [type]
  5805. Opens an image file.
  5806. @end deffn
  5807. @deffn Command {etm load} filename
  5808. Loads captured trace data from @file{filename}.
  5809. @end deffn
  5810. @deffn Command {etm start}
  5811. Starts trace data collection.
  5812. @end deffn
  5813. @deffn Command {etm stop}
  5814. Stops trace data collection.
  5815. @end deffn
  5816. @anchor{traceportdrivers}
  5817. @subsection Trace Port Drivers
  5818. To use an ETM trace port it must be associated with a driver.
  5819. @deffn {Trace Port Driver} dummy
  5820. Use the @option{dummy} driver if you are configuring an ETM that's
  5821. not connected to anything (on-chip ETB or off-chip trace connector).
  5822. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  5823. any trace data collection.}
  5824. @deffn {Config Command} {etm_dummy config} target
  5825. Associates the ETM for @var{target} with a dummy driver.
  5826. @end deffn
  5827. @end deffn
  5828. @deffn {Trace Port Driver} etb
  5829. Use the @option{etb} driver if you are configuring an ETM
  5830. to use on-chip ETB memory.
  5831. @deffn {Config Command} {etb config} target etb_tap
  5832. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  5833. You can see the ETB registers using the @command{reg} command.
  5834. @end deffn
  5835. @deffn Command {etb trigger_percent} [percent]
  5836. This displays, or optionally changes, ETB behavior after the
  5837. ETM's configured @emph{trigger} event fires.
  5838. It controls how much more trace data is saved after the (single)
  5839. trace trigger becomes active.
  5840. @itemize
  5841. @item The default corresponds to @emph{trace around} usage,
  5842. recording 50 percent data before the event and the rest
  5843. afterwards.
  5844. @item The minimum value of @var{percent} is 2 percent,
  5845. recording almost exclusively data before the trigger.
  5846. Such extreme @emph{trace before} usage can help figure out
  5847. what caused that event to happen.
  5848. @item The maximum value of @var{percent} is 100 percent,
  5849. recording data almost exclusively after the event.
  5850. This extreme @emph{trace after} usage might help sort out
  5851. how the event caused trouble.
  5852. @end itemize
  5853. @c REVISIT allow "break" too -- enter debug mode.
  5854. @end deffn
  5855. @end deffn
  5856. @deffn {Trace Port Driver} oocd_trace
  5857. This driver isn't available unless OpenOCD was explicitly configured
  5858. with the @option{--enable-oocd_trace} option. You probably don't want
  5859. to configure it unless you've built the appropriate prototype hardware;
  5860. it's @emph{proof-of-concept} software.
  5861. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  5862. connected to an off-chip trace connector.
  5863. @deffn {Config Command} {oocd_trace config} target tty
  5864. Associates the ETM for @var{target} with a trace driver which
  5865. collects data through the serial port @var{tty}.
  5866. @end deffn
  5867. @deffn Command {oocd_trace resync}
  5868. Re-synchronizes with the capture clock.
  5869. @end deffn
  5870. @deffn Command {oocd_trace status}
  5871. Reports whether the capture clock is locked or not.
  5872. @end deffn
  5873. @end deffn
  5874. @section Generic ARM
  5875. @cindex ARM
  5876. These commands should be available on all ARM processors.
  5877. They are available in addition to other core-specific
  5878. commands that may be available.
  5879. @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
  5880. Displays the core_state, optionally changing it to process
  5881. either @option{arm} or @option{thumb} instructions.
  5882. The target may later be resumed in the currently set core_state.
  5883. (Processors may also support the Jazelle state, but
  5884. that is not currently supported in OpenOCD.)
  5885. @end deffn
  5886. @deffn Command {arm disassemble} address [count [@option{thumb}]]
  5887. @cindex disassemble
  5888. Disassembles @var{count} instructions starting at @var{address}.
  5889. If @var{count} is not specified, a single instruction is disassembled.
  5890. If @option{thumb} is specified, or the low bit of the address is set,
  5891. Thumb2 (mixed 16/32-bit) instructions are used;
  5892. else ARM (32-bit) instructions are used.
  5893. (Processors may also support the Jazelle state, but
  5894. those instructions are not currently understood by OpenOCD.)
  5895. Note that all Thumb instructions are Thumb2 instructions,
  5896. so older processors (without Thumb2 support) will still
  5897. see correct disassembly of Thumb code.
  5898. Also, ThumbEE opcodes are the same as Thumb2,
  5899. with a handful of exceptions.
  5900. ThumbEE disassembly currently has no explicit support.
  5901. @end deffn
  5902. @deffn Command {arm mcr} pX op1 CRn CRm op2 value
  5903. Write @var{value} to a coprocessor @var{pX} register
  5904. passing parameters @var{CRn},
  5905. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5906. and using the MCR instruction.
  5907. (Parameter sequence matches the ARM instruction, but omits
  5908. an ARM register.)
  5909. @end deffn
  5910. @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
  5911. Read a coprocessor @var{pX} register passing parameters @var{CRn},
  5912. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5913. and the MRC instruction.
  5914. Returns the result so it can be manipulated by Jim scripts.
  5915. (Parameter sequence matches the ARM instruction, but omits
  5916. an ARM register.)
  5917. @end deffn
  5918. @deffn Command {arm reg}
  5919. Display a table of all banked core registers, fetching the current value from every
  5920. core mode if necessary.
  5921. @end deffn
  5922. @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
  5923. @cindex ARM semihosting
  5924. Display status of semihosting, after optionally changing that status.
  5925. Semihosting allows for code executing on an ARM target to use the
  5926. I/O facilities on the host computer i.e. the system where OpenOCD
  5927. is running. The target application must be linked against a library
  5928. implementing the ARM semihosting convention that forwards operation
  5929. requests by using a special SVC instruction that is trapped at the
  5930. Supervisor Call vector by OpenOCD.
  5931. @end deffn
  5932. @section ARMv4 and ARMv5 Architecture
  5933. @cindex ARMv4
  5934. @cindex ARMv5
  5935. The ARMv4 and ARMv5 architectures are widely used in embedded systems,
  5936. and introduced core parts of the instruction set in use today.
  5937. That includes the Thumb instruction set, introduced in the ARMv4T
  5938. variant.
  5939. @subsection ARM7 and ARM9 specific commands
  5940. @cindex ARM7
  5941. @cindex ARM9
  5942. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  5943. ARM9TDMI, ARM920T or ARM926EJ-S.
  5944. They are available in addition to the ARM commands,
  5945. and any other core-specific commands that may be available.
  5946. @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
  5947. Displays the value of the flag controlling use of the
  5948. the EmbeddedIce DBGRQ signal to force entry into debug mode,
  5949. instead of breakpoints.
  5950. If a boolean parameter is provided, first assigns that flag.
  5951. This should be
  5952. safe for all but ARM7TDMI-S cores (like NXP LPC).
  5953. This feature is enabled by default on most ARM9 cores,
  5954. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  5955. @end deffn
  5956. @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
  5957. @cindex DCC
  5958. Displays the value of the flag controlling use of the debug communications
  5959. channel (DCC) to write larger (>128 byte) amounts of memory.
  5960. If a boolean parameter is provided, first assigns that flag.
  5961. DCC downloads offer a huge speed increase, but might be
  5962. unsafe, especially with targets running at very low speeds. This command was introduced
  5963. with OpenOCD rev. 60, and requires a few bytes of working area.
  5964. @end deffn
  5965. @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
  5966. Displays the value of the flag controlling use of memory writes and reads
  5967. that don't check completion of the operation.
  5968. If a boolean parameter is provided, first assigns that flag.
  5969. This provides a huge speed increase, especially with USB JTAG
  5970. cables (FT2232), but might be unsafe if used with targets running at very low
  5971. speeds, like the 32kHz startup clock of an AT91RM9200.
  5972. @end deffn
  5973. @subsection ARM720T specific commands
  5974. @cindex ARM720T
  5975. These commands are available to ARM720T based CPUs,
  5976. which are implementations of the ARMv4T architecture
  5977. based on the ARM7TDMI-S integer core.
  5978. They are available in addition to the ARM and ARM7/ARM9 commands.
  5979. @deffn Command {arm720t cp15} opcode [value]
  5980. @emph{DEPRECATED -- avoid using this.
  5981. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  5982. Display cp15 register returned by the ARM instruction @var{opcode};
  5983. else if a @var{value} is provided, that value is written to that register.
  5984. The @var{opcode} should be the value of either an MRC or MCR instruction.
  5985. @end deffn
  5986. @subsection ARM9 specific commands
  5987. @cindex ARM9
  5988. ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
  5989. integer processors.
  5990. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  5991. @c 9-june-2009: tried this on arm920t, it didn't work.
  5992. @c no-params always lists nothing caught, and that's how it acts.
  5993. @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
  5994. @c versions have different rules about when they commit writes.
  5995. @anchor{arm9vectorcatch}
  5996. @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
  5997. @cindex vector_catch
  5998. Vector Catch hardware provides a sort of dedicated breakpoint
  5999. for hardware events such as reset, interrupt, and abort.
  6000. You can use this to conserve normal breakpoint resources,
  6001. so long as you're not concerned with code that branches directly
  6002. to those hardware vectors.
  6003. This always finishes by listing the current configuration.
  6004. If parameters are provided, it first reconfigures the
  6005. vector catch hardware to intercept
  6006. @option{all} of the hardware vectors,
  6007. @option{none} of them,
  6008. or a list with one or more of the following:
  6009. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
  6010. @option{irq} @option{fiq}.
  6011. @end deffn
  6012. @subsection ARM920T specific commands
  6013. @cindex ARM920T
  6014. These commands are available to ARM920T based CPUs,
  6015. which are implementations of the ARMv4T architecture
  6016. built using the ARM9TDMI integer core.
  6017. They are available in addition to the ARM, ARM7/ARM9,
  6018. and ARM9 commands.
  6019. @deffn Command {arm920t cache_info}
  6020. Print information about the caches found. This allows to see whether your target
  6021. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  6022. @end deffn
  6023. @deffn Command {arm920t cp15} regnum [value]
  6024. Display cp15 register @var{regnum};
  6025. else if a @var{value} is provided, that value is written to that register.
  6026. This uses "physical access" and the register number is as
  6027. shown in bits 38..33 of table 9-9 in the ARM920T TRM.
  6028. (Not all registers can be written.)
  6029. @end deffn
  6030. @deffn Command {arm920t cp15i} opcode [value [address]]
  6031. @emph{DEPRECATED -- avoid using this.
  6032. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  6033. Interpreted access using ARM instruction @var{opcode}, which should
  6034. be the value of either an MRC or MCR instruction
  6035. (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
  6036. If no @var{value} is provided, the result is displayed.
  6037. Else if that value is written using the specified @var{address},
  6038. or using zero if no other address is provided.
  6039. @end deffn
  6040. @deffn Command {arm920t read_cache} filename
  6041. Dump the content of ICache and DCache to a file named @file{filename}.
  6042. @end deffn
  6043. @deffn Command {arm920t read_mmu} filename
  6044. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  6045. @end deffn
  6046. @subsection ARM926ej-s specific commands
  6047. @cindex ARM926ej-s
  6048. These commands are available to ARM926ej-s based CPUs,
  6049. which are implementations of the ARMv5TEJ architecture
  6050. based on the ARM9EJ-S integer core.
  6051. They are available in addition to the ARM, ARM7/ARM9,
  6052. and ARM9 commands.
  6053. The Feroceon cores also support these commands, although
  6054. they are not built from ARM926ej-s designs.
  6055. @deffn Command {arm926ejs cache_info}
  6056. Print information about the caches found.
  6057. @end deffn
  6058. @subsection ARM966E specific commands
  6059. @cindex ARM966E
  6060. These commands are available to ARM966 based CPUs,
  6061. which are implementations of the ARMv5TE architecture.
  6062. They are available in addition to the ARM, ARM7/ARM9,
  6063. and ARM9 commands.
  6064. @deffn Command {arm966e cp15} regnum [value]
  6065. Display cp15 register @var{regnum};
  6066. else if a @var{value} is provided, that value is written to that register.
  6067. The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
  6068. ARM966E-S TRM.
  6069. There is no current control over bits 31..30 from that table,
  6070. as required for BIST support.
  6071. @end deffn
  6072. @subsection XScale specific commands
  6073. @cindex XScale
  6074. Some notes about the debug implementation on the XScale CPUs:
  6075. The XScale CPU provides a special debug-only mini-instruction cache
  6076. (mini-IC) in which exception vectors and target-resident debug handler
  6077. code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
  6078. must point vector 0 (the reset vector) to the entry of the debug
  6079. handler. However, this means that the complete first cacheline in the
  6080. mini-IC is marked valid, which makes the CPU fetch all exception
  6081. handlers from the mini-IC, ignoring the code in RAM.
  6082. To address this situation, OpenOCD provides the @code{xscale
  6083. vector_table} command, which allows the user to explicity write
  6084. individual entries to either the high or low vector table stored in
  6085. the mini-IC.
  6086. It is recommended to place a pc-relative indirect branch in the vector
  6087. table, and put the branch destination somewhere in memory. Doing so
  6088. makes sure the code in the vector table stays constant regardless of
  6089. code layout in memory:
  6090. @example
  6091. _vectors:
  6092. ldr pc,[pc,#0x100-8]
  6093. ldr pc,[pc,#0x100-8]
  6094. ldr pc,[pc,#0x100-8]
  6095. ldr pc,[pc,#0x100-8]
  6096. ldr pc,[pc,#0x100-8]
  6097. ldr pc,[pc,#0x100-8]
  6098. ldr pc,[pc,#0x100-8]
  6099. ldr pc,[pc,#0x100-8]
  6100. .org 0x100
  6101. .long real_reset_vector
  6102. .long real_ui_handler
  6103. .long real_swi_handler
  6104. .long real_pf_abort
  6105. .long real_data_abort
  6106. .long 0 /* unused */
  6107. .long real_irq_handler
  6108. .long real_fiq_handler
  6109. @end example
  6110. Alternatively, you may choose to keep some or all of the mini-IC
  6111. vector table entries synced with those written to memory by your
  6112. system software. The mini-IC can not be modified while the processor
  6113. is executing, but for each vector table entry not previously defined
  6114. using the @code{xscale vector_table} command, OpenOCD will copy the
  6115. value from memory to the mini-IC every time execution resumes from a
  6116. halt. This is done for both high and low vector tables (although the
  6117. table not in use may not be mapped to valid memory, and in this case
  6118. that copy operation will silently fail). This means that you will
  6119. need to briefly halt execution at some strategic point during system
  6120. start-up; e.g., after the software has initialized the vector table,
  6121. but before exceptions are enabled. A breakpoint can be used to
  6122. accomplish this once the appropriate location in the start-up code has
  6123. been identified. A watchpoint over the vector table region is helpful
  6124. in finding the location if you're not sure. Note that the same
  6125. situation exists any time the vector table is modified by the system
  6126. software.
  6127. The debug handler must be placed somewhere in the address space using
  6128. the @code{xscale debug_handler} command. The allowed locations for the
  6129. debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
  6130. 0xfffff800). The default value is 0xfe000800.
  6131. XScale has resources to support two hardware breakpoints and two
  6132. watchpoints. However, the following restrictions on watchpoint
  6133. functionality apply: (1) the value and mask arguments to the @code{wp}
  6134. command are not supported, (2) the watchpoint length must be a
  6135. power of two and not less than four, and can not be greater than the
  6136. watchpoint address, and (3) a watchpoint with a length greater than
  6137. four consumes all the watchpoint hardware resources. This means that
  6138. at any one time, you can have enabled either two watchpoints with a
  6139. length of four, or one watchpoint with a length greater than four.
  6140. These commands are available to XScale based CPUs,
  6141. which are implementations of the ARMv5TE architecture.
  6142. @deffn Command {xscale analyze_trace}
  6143. Displays the contents of the trace buffer.
  6144. @end deffn
  6145. @deffn Command {xscale cache_clean_address} address
  6146. Changes the address used when cleaning the data cache.
  6147. @end deffn
  6148. @deffn Command {xscale cache_info}
  6149. Displays information about the CPU caches.
  6150. @end deffn
  6151. @deffn Command {xscale cp15} regnum [value]
  6152. Display cp15 register @var{regnum};
  6153. else if a @var{value} is provided, that value is written to that register.
  6154. @end deffn
  6155. @deffn Command {xscale debug_handler} target address
  6156. Changes the address used for the specified target's debug handler.
  6157. @end deffn
  6158. @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
  6159. Enables or disable the CPU's data cache.
  6160. @end deffn
  6161. @deffn Command {xscale dump_trace} filename
  6162. Dumps the raw contents of the trace buffer to @file{filename}.
  6163. @end deffn
  6164. @deffn Command {xscale icache} [@option{enable}|@option{disable}]
  6165. Enables or disable the CPU's instruction cache.
  6166. @end deffn
  6167. @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
  6168. Enables or disable the CPU's memory management unit.
  6169. @end deffn
  6170. @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
  6171. Displays the trace buffer status, after optionally
  6172. enabling or disabling the trace buffer
  6173. and modifying how it is emptied.
  6174. @end deffn
  6175. @deffn Command {xscale trace_image} filename [offset [type]]
  6176. Opens a trace image from @file{filename}, optionally rebasing
  6177. its segment addresses by @var{offset}.
  6178. The image @var{type} may be one of
  6179. @option{bin} (binary), @option{ihex} (Intel hex),
  6180. @option{elf} (ELF file), @option{s19} (Motorola s19),
  6181. @option{mem}, or @option{builder}.
  6182. @end deffn
  6183. @anchor{xscalevectorcatch}
  6184. @deffn Command {xscale vector_catch} [mask]
  6185. @cindex vector_catch
  6186. Display a bitmask showing the hardware vectors to catch.
  6187. If the optional parameter is provided, first set the bitmask to that value.
  6188. The mask bits correspond with bit 16..23 in the DCSR:
  6189. @example
  6190. 0x01 Trap Reset
  6191. 0x02 Trap Undefined Instructions
  6192. 0x04 Trap Software Interrupt
  6193. 0x08 Trap Prefetch Abort
  6194. 0x10 Trap Data Abort
  6195. 0x20 reserved
  6196. 0x40 Trap IRQ
  6197. 0x80 Trap FIQ
  6198. @end example
  6199. @end deffn
  6200. @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
  6201. @cindex vector_table
  6202. Set an entry in the mini-IC vector table. There are two tables: one for
  6203. low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
  6204. holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
  6205. points to the debug handler entry and can not be overwritten.
  6206. @var{value} holds the 32-bit opcode that is placed in the mini-IC.
  6207. Without arguments, the current settings are displayed.
  6208. @end deffn
  6209. @section ARMv6 Architecture
  6210. @cindex ARMv6
  6211. @subsection ARM11 specific commands
  6212. @cindex ARM11
  6213. @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
  6214. Displays the value of the memwrite burst-enable flag,
  6215. which is enabled by default.
  6216. If a boolean parameter is provided, first assigns that flag.
  6217. Burst writes are only used for memory writes larger than 1 word.
  6218. They improve performance by assuming that the CPU has read each data
  6219. word over JTAG and completed its write before the next word arrives,
  6220. instead of polling for a status flag to verify that completion.
  6221. This is usually safe, because JTAG runs much slower than the CPU.
  6222. @end deffn
  6223. @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
  6224. Displays the value of the memwrite error_fatal flag,
  6225. which is enabled by default.
  6226. If a boolean parameter is provided, first assigns that flag.
  6227. When set, certain memory write errors cause earlier transfer termination.
  6228. @end deffn
  6229. @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
  6230. Displays the value of the flag controlling whether
  6231. IRQs are enabled during single stepping;
  6232. they are disabled by default.
  6233. If a boolean parameter is provided, first assigns that.
  6234. @end deffn
  6235. @deffn Command {arm11 vcr} [value]
  6236. @cindex vector_catch
  6237. Displays the value of the @emph{Vector Catch Register (VCR)},
  6238. coprocessor 14 register 7.
  6239. If @var{value} is defined, first assigns that.
  6240. Vector Catch hardware provides dedicated breakpoints
  6241. for certain hardware events.
  6242. The specific bit values are core-specific (as in fact is using
  6243. coprocessor 14 register 7 itself) but all current ARM11
  6244. cores @emph{except the ARM1176} use the same six bits.
  6245. @end deffn
  6246. @section ARMv7 Architecture
  6247. @cindex ARMv7
  6248. @subsection ARMv7 Debug Access Port (DAP) specific commands
  6249. @cindex Debug Access Port
  6250. @cindex DAP
  6251. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  6252. included on Cortex-M and Cortex-A systems.
  6253. They are available in addition to other core-specific commands that may be available.
  6254. @deffn Command {dap apid} [num]
  6255. Displays ID register from AP @var{num},
  6256. defaulting to the currently selected AP.
  6257. @end deffn
  6258. @deffn Command {dap apsel} [num]
  6259. Select AP @var{num}, defaulting to 0.
  6260. @end deffn
  6261. @deffn Command {dap baseaddr} [num]
  6262. Displays debug base address from MEM-AP @var{num},
  6263. defaulting to the currently selected AP.
  6264. @end deffn
  6265. @deffn Command {dap info} [num]
  6266. Displays the ROM table for MEM-AP @var{num},
  6267. defaulting to the currently selected AP.
  6268. @end deffn
  6269. @deffn Command {dap memaccess} [value]
  6270. Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
  6271. memory bus access [0-255], giving additional time to respond to reads.
  6272. If @var{value} is defined, first assigns that.
  6273. @end deffn
  6274. @deffn Command {dap apcsw} [0 / 1]
  6275. fix CSW_SPROT from register AP_REG_CSW on selected dap.
  6276. Defaulting to 0.
  6277. @end deffn
  6278. @subsection ARMv7-M specific commands
  6279. @cindex tracing
  6280. @cindex SWO
  6281. @cindex SWV
  6282. @cindex TPIU
  6283. @cindex ITM
  6284. @cindex ETM
  6285. @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal @var{filename}}) @
  6286. (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
  6287. @var{TRACECLKIN_freq} [@var{trace_freq}]))
  6288. ARMv7-M architecture provides several modules to generate debugging
  6289. information internally (ITM, DWT and ETM). Their output is directed
  6290. through TPIU to be captured externally either on an SWO pin (this
  6291. configuration is called SWV) or on a synchronous parallel trace port.
  6292. This command configures the TPIU module of the target and, if internal
  6293. capture mode is selected, starts to capture trace output by using the
  6294. debugger adapter features.
  6295. Some targets require additional actions to be performed in the
  6296. @b{trace-config} handler for trace port to be activated.
  6297. Command options:
  6298. @itemize @minus
  6299. @item @option{disable} disable TPIU handling;
  6300. @item @option{external} configure TPIU to let user capture trace
  6301. output externally (with an additional UART or logic analyzer hardware);
  6302. @item @option{internal @var{filename}} configure TPIU and debug adapter to
  6303. gather trace data and append it to @var{filename} (which can be
  6304. either a regular file or a named pipe);
  6305. @item @option{sync @var{port_width}} use synchronous parallel trace output
  6306. mode, and set port width to @var{port_width};
  6307. @item @option{manchester} use asynchronous SWO mode with Manchester
  6308. coding;
  6309. @item @option{uart} use asynchronous SWO mode with NRZ (same as
  6310. regular UART 8N1) coding;
  6311. @item @var{formatter_enable} is @option{on} or @option{off} to enable
  6312. or disable TPIU formatter which needs to be used when both ITM and ETM
  6313. data is to be output via SWO;
  6314. @item @var{TRACECLKIN_freq} this should be specified to match target's
  6315. current TRACECLKIN frequency (usually the same as HCLK);
  6316. @item @var{trace_freq} trace port frequency. Can be omitted in
  6317. internal mode to let the adapter driver select the maximum supported
  6318. rate automatically.
  6319. @end itemize
  6320. Example usage:
  6321. @enumerate
  6322. @item STM32L152 board is programmed with an application that configures
  6323. PLL to provide core clock with 24MHz frequency; to use ITM output it's
  6324. enough to:
  6325. @example
  6326. #include <libopencm3/cm3/itm.h>
  6327. ...
  6328. ITM_STIM8(0) = c;
  6329. ...
  6330. @end example
  6331. (the most obvious way is to use the first stimulus port for printf,
  6332. for that this ITM_STIM8 assignment can be used inside _write(); to make it
  6333. blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
  6334. ITM_STIM_FIFOREADY));});
  6335. @item An FT2232H UART is connected to the SWO pin of the board;
  6336. @item Commands to configure UART for 12MHz baud rate:
  6337. @example
  6338. $ setserial /dev/ttyUSB1 spd_cust divisor 5
  6339. $ stty -F /dev/ttyUSB1 38400
  6340. @end example
  6341. (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
  6342. baud with our custom divisor to get 12MHz)
  6343. @item @code{itmdump -f /dev/ttyUSB1 -d1}
  6344. @item OpenOCD invocation line:
  6345. @example
  6346. openocd -f interface/stlink-v2-1.cfg \
  6347. -c "transport select hla_swd" \
  6348. -f target/stm32l1.cfg \
  6349. -c "tpiu config external uart off 24000000 12000000"
  6350. @end example
  6351. @end enumerate
  6352. @end deffn
  6353. @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
  6354. Enable or disable trace output for ITM stimulus @var{port} (counting
  6355. from 0). Port 0 is enabled on target creation automatically.
  6356. @end deffn
  6357. @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
  6358. Enable or disable trace output for all ITM stimulus ports.
  6359. @end deffn
  6360. @subsection Cortex-M specific commands
  6361. @cindex Cortex-M
  6362. @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
  6363. Control masking (disabling) interrupts during target step/resume.
  6364. The @option{auto} option handles interrupts during stepping a way they get
  6365. served but don't disturb the program flow. The step command first allows
  6366. pending interrupt handlers to execute, then disables interrupts and steps over
  6367. the next instruction where the core was halted. After the step interrupts
  6368. are enabled again. If the interrupt handlers don't complete within 500ms,
  6369. the step command leaves with the core running.
  6370. Note that a free breakpoint is required for the @option{auto} option. If no
  6371. breakpoint is available at the time of the step, then the step is taken
  6372. with interrupts enabled, i.e. the same way the @option{off} option does.
  6373. Default is @option{auto}.
  6374. @end deffn
  6375. @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
  6376. @cindex vector_catch
  6377. Vector Catch hardware provides dedicated breakpoints
  6378. for certain hardware events.
  6379. Parameters request interception of
  6380. @option{all} of these hardware event vectors,
  6381. @option{none} of them,
  6382. or one or more of the following:
  6383. @option{hard_err} for a HardFault exception;
  6384. @option{mm_err} for a MemManage exception;
  6385. @option{bus_err} for a BusFault exception;
  6386. @option{irq_err},
  6387. @option{state_err},
  6388. @option{chk_err}, or
  6389. @option{nocp_err} for various UsageFault exceptions; or
  6390. @option{reset}.
  6391. If NVIC setup code does not enable them,
  6392. MemManage, BusFault, and UsageFault exceptions
  6393. are mapped to HardFault.
  6394. UsageFault checks for
  6395. divide-by-zero and unaligned access
  6396. must also be explicitly enabled.
  6397. This finishes by listing the current vector catch configuration.
  6398. @end deffn
  6399. @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
  6400. Control reset handling. The default @option{srst} is to use srst if fitted,
  6401. otherwise fallback to @option{vectreset}.
  6402. @itemize @minus
  6403. @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
  6404. @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
  6405. @item @option{vectreset} use NVIC VECTRESET to reset system.
  6406. @end itemize
  6407. Using @option{vectreset} is a safe option for all current Cortex-M cores.
  6408. This however has the disadvantage of only resetting the core, all peripherals
  6409. are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
  6410. the peripherals.
  6411. @xref{targetevents,,Target Events}.
  6412. @end deffn
  6413. @section Intel Architecture
  6414. Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
  6415. (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
  6416. Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
  6417. software debug and the CLTAP is used for SoC level operations.
  6418. Useful docs are here:
  6419. @itemize
  6420. @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
  6421. @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
  6422. @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
  6423. @end itemize
  6424. @subsection x86 32-bit specific commands
  6425. The three main address spaces for x86 are memory, I/O and configuration space.
  6426. These commands allow a user to read and write to the 64Kbyte I/O address space.
  6427. @deffn Command {x86_32 idw} address
  6428. Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
  6429. @end deffn
  6430. @deffn Command {x86_32 idh} address
  6431. Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
  6432. @end deffn
  6433. @deffn Command {x86_32 idb} address
  6434. Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
  6435. @end deffn
  6436. @deffn Command {x86_32 iww} address
  6437. Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
  6438. @end deffn
  6439. @deffn Command {x86_32 iwh} address
  6440. Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
  6441. @end deffn
  6442. @deffn Command {x86_32 iwb} address
  6443. Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
  6444. @end deffn
  6445. @section OpenRISC Architecture
  6446. The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
  6447. configured with any of the TAP / Debug Unit available.
  6448. @subsection TAP and Debug Unit selection commands
  6449. @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
  6450. Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
  6451. @end deffn
  6452. @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
  6453. Select between the Advanced Debug Interface and the classic one.
  6454. An option can be passed as a second argument to the debug unit.
  6455. When using the Advanced Debug Interface, option = 1 means the RTL core is
  6456. configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
  6457. between bytes while doing read or write bursts.
  6458. @end deffn
  6459. @subsection Registers commands
  6460. @deffn Command {addreg} [name] [address] [feature] [reg_group]
  6461. Add a new register in the cpu register list. This register will be
  6462. included in the generated target descriptor file.
  6463. @strong{[feature]} must be "[0..10]".
  6464. @strong{[reg_group]} can be anything. The default register list defines "system",
  6465. "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
  6466. and "timer" groups.
  6467. @emph{example:}
  6468. @example
  6469. addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
  6470. @end example
  6471. @end deffn
  6472. @deffn Command {readgroup} (@option{group})
  6473. Display all registers in @emph{group}.
  6474. @emph{group} can be "system",
  6475. "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
  6476. "timer" or any new group created with addreg command.
  6477. @end deffn
  6478. @anchor{softwaredebugmessagesandtracing}
  6479. @section Software Debug Messages and Tracing
  6480. @cindex Linux-ARM DCC support
  6481. @cindex tracing
  6482. @cindex libdcc
  6483. @cindex DCC
  6484. OpenOCD can process certain requests from target software, when
  6485. the target uses appropriate libraries.
  6486. The most powerful mechanism is semihosting, but there is also
  6487. a lighter weight mechanism using only the DCC channel.
  6488. Currently @command{target_request debugmsgs}
  6489. is supported only for @option{arm7_9} and @option{cortex_m} cores.
  6490. These messages are received as part of target polling, so
  6491. you need to have @command{poll on} active to receive them.
  6492. They are intrusive in that they will affect program execution
  6493. times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
  6494. See @file{libdcc} in the contrib dir for more details.
  6495. In addition to sending strings, characters, and
  6496. arrays of various size integers from the target,
  6497. @file{libdcc} also exports a software trace point mechanism.
  6498. The target being debugged may
  6499. issue trace messages which include a 24-bit @dfn{trace point} number.
  6500. Trace point support includes two distinct mechanisms,
  6501. each supported by a command:
  6502. @itemize
  6503. @item @emph{History} ... A circular buffer of trace points
  6504. can be set up, and then displayed at any time.
  6505. This tracks where code has been, which can be invaluable in
  6506. finding out how some fault was triggered.
  6507. The buffer may overflow, since it collects records continuously.
  6508. It may be useful to use some of the 24 bits to represent a
  6509. particular event, and other bits to hold data.
  6510. @item @emph{Counting} ... An array of counters can be set up,
  6511. and then displayed at any time.
  6512. This can help establish code coverage and identify hot spots.
  6513. The array of counters is directly indexed by the trace point
  6514. number, so trace points with higher numbers are not counted.
  6515. @end itemize
  6516. Linux-ARM kernels have a ``Kernel low-level debugging
  6517. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  6518. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  6519. deliver messages before a serial console can be activated.
  6520. This is not the same format used by @file{libdcc}.
  6521. Other software, such as the U-Boot boot loader, sometimes
  6522. does the same thing.
  6523. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  6524. Displays current handling of target DCC message requests.
  6525. These messages may be sent to the debugger while the target is running.
  6526. The optional @option{enable} and @option{charmsg} parameters
  6527. both enable the messages, while @option{disable} disables them.
  6528. With @option{charmsg} the DCC words each contain one character,
  6529. as used by Linux with CONFIG_DEBUG_ICEDCC;
  6530. otherwise the libdcc format is used.
  6531. @end deffn
  6532. @deffn Command {trace history} [@option{clear}|count]
  6533. With no parameter, displays all the trace points that have triggered
  6534. in the order they triggered.
  6535. With the parameter @option{clear}, erases all current trace history records.
  6536. With a @var{count} parameter, allocates space for that many
  6537. history records.
  6538. @end deffn
  6539. @deffn Command {trace point} [@option{clear}|identifier]
  6540. With no parameter, displays all trace point identifiers and how many times
  6541. they have been triggered.
  6542. With the parameter @option{clear}, erases all current trace point counters.
  6543. With a numeric @var{identifier} parameter, creates a new a trace point counter
  6544. and associates it with that identifier.
  6545. @emph{Important:} The identifier and the trace point number
  6546. are not related except by this command.
  6547. These trace point numbers always start at zero (from server startup,
  6548. or after @command{trace point clear}) and count up from there.
  6549. @end deffn
  6550. @node JTAG Commands
  6551. @chapter JTAG Commands
  6552. @cindex JTAG Commands
  6553. Most general purpose JTAG commands have been presented earlier.
  6554. (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  6555. Lower level JTAG commands, as presented here,
  6556. may be needed to work with targets which require special
  6557. attention during operations such as reset or initialization.
  6558. To use these commands you will need to understand some
  6559. of the basics of JTAG, including:
  6560. @itemize @bullet
  6561. @item A JTAG scan chain consists of a sequence of individual TAP
  6562. devices such as a CPUs.
  6563. @item Control operations involve moving each TAP through the same
  6564. standard state machine (in parallel)
  6565. using their shared TMS and clock signals.
  6566. @item Data transfer involves shifting data through the chain of
  6567. instruction or data registers of each TAP, writing new register values
  6568. while the reading previous ones.
  6569. @item Data register sizes are a function of the instruction active in
  6570. a given TAP, while instruction register sizes are fixed for each TAP.
  6571. All TAPs support a BYPASS instruction with a single bit data register.
  6572. @item The way OpenOCD differentiates between TAP devices is by
  6573. shifting different instructions into (and out of) their instruction
  6574. registers.
  6575. @end itemize
  6576. @section Low Level JTAG Commands
  6577. These commands are used by developers who need to access
  6578. JTAG instruction or data registers, possibly controlling
  6579. the order of TAP state transitions.
  6580. If you're not debugging OpenOCD internals, or bringing up a
  6581. new JTAG adapter or a new type of TAP device (like a CPU or
  6582. JTAG router), you probably won't need to use these commands.
  6583. In a debug session that doesn't use JTAG for its transport protocol,
  6584. these commands are not available.
  6585. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  6586. Loads the data register of @var{tap} with a series of bit fields
  6587. that specify the entire register.
  6588. Each field is @var{numbits} bits long with
  6589. a numeric @var{value} (hexadecimal encouraged).
  6590. The return value holds the original value of each
  6591. of those fields.
  6592. For example, a 38 bit number might be specified as one
  6593. field of 32 bits then one of 6 bits.
  6594. @emph{For portability, never pass fields which are more
  6595. than 32 bits long. Many OpenOCD implementations do not
  6596. support 64-bit (or larger) integer values.}
  6597. All TAPs other than @var{tap} must be in BYPASS mode.
  6598. The single bit in their data registers does not matter.
  6599. When @var{tap_state} is specified, the JTAG state machine is left
  6600. in that state.
  6601. For example @sc{drpause} might be specified, so that more
  6602. instructions can be issued before re-entering the @sc{run/idle} state.
  6603. If the end state is not specified, the @sc{run/idle} state is entered.
  6604. @quotation Warning
  6605. OpenOCD does not record information about data register lengths,
  6606. so @emph{it is important that you get the bit field lengths right}.
  6607. Remember that different JTAG instructions refer to different
  6608. data registers, which may have different lengths.
  6609. Moreover, those lengths may not be fixed;
  6610. the SCAN_N instruction can change the length of
  6611. the register accessed by the INTEST instruction
  6612. (by connecting a different scan chain).
  6613. @end quotation
  6614. @end deffn
  6615. @deffn Command {flush_count}
  6616. Returns the number of times the JTAG queue has been flushed.
  6617. This may be used for performance tuning.
  6618. For example, flushing a queue over USB involves a
  6619. minimum latency, often several milliseconds, which does
  6620. not change with the amount of data which is written.
  6621. You may be able to identify performance problems by finding
  6622. tasks which waste bandwidth by flushing small transfers too often,
  6623. instead of batching them into larger operations.
  6624. @end deffn
  6625. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  6626. For each @var{tap} listed, loads the instruction register
  6627. with its associated numeric @var{instruction}.
  6628. (The number of bits in that instruction may be displayed
  6629. using the @command{scan_chain} command.)
  6630. <