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  1. #
  2. # script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
  3. #
  4. #
  5. # samdXX devices only support SWD transports.
  6. #
  7. source [find target/swj-dp.tcl]
  8. if { [info exists CHIPNAME] } {
  9. set _CHIPNAME $CHIPNAME
  10. } else {
  11. set _CHIPNAME at91samd
  12. }
  13. if { [info exists ENDIAN] } {
  14. set _ENDIAN $ENDIAN
  15. } else {
  16. set _ENDIAN little
  17. }
  18. # Work-area is a space in RAM used for flash programming
  19. # By default use 2kB
  20. if { [info exists WORKAREASIZE] } {
  21. set _WORKAREASIZE $WORKAREASIZE
  22. } else {
  23. set _WORKAREASIZE 0x800
  24. }
  25. if { [info exists CPUTAPID] } {
  26. set _CPUTAPID $CPUTAPID
  27. } else {
  28. set _CPUTAPID 0x4ba00477
  29. }
  30. swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  31. set _TARGETNAME $_CHIPNAME.cpu
  32. target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  33. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  34. # SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
  35. # deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
  36. #
  37. # dsu_reset_deassert configures whether we want to run or halt out of reset,
  38. # then instruct the DSU to let us out of reset.
  39. $_TARGETNAME configure -event reset-deassert-post {
  40. at91samd dsu_reset_deassert
  41. }
  42. # SRST (wired to RESET_N) resets debug circuitry
  43. reset_config srst_gates_jtag srst_pulls_trst
  44. # Do not use a reset button with other SWD adapter than Atmel's EDBG.
  45. # DSU usually locks MCU in reset state until you issue a reset command
  46. # in OpenOCD.
  47. # SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
  48. # Other members of family usually use SYSCLK = 4 MHz after reset.
  49. # Datasheet does not specify SYSCLK to SWD clock ratio.
  50. # Usually used SYSCLK/6 is slow, testing shows that debugging can
  51. # work @ SYSCLK/2 but your mileage may vary.
  52. # This limit is most probably imposed by incorrectly handled SWD WAIT
  53. # on some SWD adapters.
  54. adapter_khz 400
  55. # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
  56. # without problem at maximal clock speed. Atmel recommends
  57. # adapter speed less than 10 * CPU clock.
  58. # adapter_khz 5000
  59. if {![using_hla]} {
  60. # if srst is not fitted use SYSRESETREQ to
  61. # perform a soft reset
  62. cortex_m reset_config sysresetreq
  63. }
  64. set _FLASHNAME $_CHIPNAME.flash
  65. flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME