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  1. # TI/Luminary Stellaris LM3S chip family
  2. # Some devices have errata in returning their device class.
  3. # DEVICECLASS is provided as a manual override
  4. # Manual setting of a device class of 0xff is not allowed
  5. global _DEVICECLASS
  6. if { [info exists DEVICECLASS ] } {
  7. set _DEVICECLASS $DEVICECLASS
  8. } else {
  9. set _DEVICECLASS 0xff
  10. }
  11. # Luminary chips support both JTAG and SWD transports.
  12. # Adapt based on what transport is active.
  13. source [find target/swj-dp.tcl]
  14. # For now we ignore the SPI and UART options, which
  15. # are usable only for ISP style initial flash programming.
  16. if { [info exists CHIPNAME] } {
  17. set _CHIPNAME $CHIPNAME
  18. } else {
  19. set _CHIPNAME lm3s
  20. }
  21. # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  22. # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  23. # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  24. # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
  25. # ... we'll ignore the JTAG version field, rather than list every
  26. # chip revision that turns up.
  27. if { [info exists CPUTAPID ] } {
  28. set _CPUTAPID $CPUTAPID
  29. } else {
  30. set _CPUTAPID 0x0ba00477
  31. }
  32. # SWD DAP, and JTAG TAP, take same params for now;
  33. # ... even though SWD ignores all except TAPID, and
  34. # JTAG shouldn't need anything more then irlen. (and TAPID).
  35. swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  36. -expected-id $_CPUTAPID -ignore-version
  37. if { [info exists WORKAREASIZE ] } {
  38. set _WORKAREASIZE $WORKAREASIZE
  39. } else {
  40. # default to 8K working area
  41. set _WORKAREASIZE 0x2000
  42. }
  43. set _TARGETNAME $_CHIPNAME.cpu
  44. target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
  45. # 8K working area at base of ram, not backed up
  46. #
  47. # NOTE: you may need or want to reconfigure the work area;
  48. # some parts have just 6K, and you may want to use other
  49. # addresses (at end of mem not beginning) or back it up.
  50. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  51. # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  52. # LM3S parts don't support RTCK
  53. #
  54. # NOTE: this may be increased by a reset-init handler, after it
  55. # configures and enables the PLL. Or you might need to decrease
  56. # this, if you're using a slower clock.
  57. adapter_khz 500
  58. source [find mem_helper.tcl]
  59. $_TARGETNAME configure -event reset-start {
  60. adapter_khz 500
  61. #
  62. # When nRST is asserted on most Stellaris devices, it clears some of
  63. # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
  64. # and OpenOCD depends on those TRMs. So we won't use SRST on those
  65. # chips. (Only power-on reset should affect debug state, beyond a
  66. # few specified bits; not the chip's nRST input, wired to SRST.)
  67. #
  68. # REVISIT current errata specs don't seem to cover this issue.
  69. # Do we have more details than this email?
  70. # https://lists.berlios.de/pipermail
  71. # /openocd-development/2008-August/003065.html
  72. #
  73. global _DEVICECLASS
  74. if {$_DEVICECLASS != 0xff} {
  75. set device_class $_DEVICECLASS
  76. } else {
  77. set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
  78. }
  79. if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
  80. # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
  81. cortex_m3 reset_config sysresetreq
  82. } else {
  83. # Tempest and newer default to using NVIC VECTRESET
  84. # this does mean a reset-init event handler is required to reset
  85. # any peripherals
  86. cortex_m3 reset_config vectreset
  87. }
  88. }
  89. # flash configuration ... autodetects sizes, autoprobed
  90. flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME