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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2008 by Oyvind Harboe *
  9. * oyvind.harboe@zylin.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "replacements.h"
  30. #include "arm_disassembler.h"
  31. #include "armv4_5.h"
  32. #include "target.h"
  33. #include "register.h"
  34. #include "log.h"
  35. #include "binarybuffer.h"
  36. #include "command.h"
  37. #include <stdlib.h>
  38. #include <string.h>
  39. #include <unistd.h>
  40. bitfield_desc_t armv4_5_psr_bitfield_desc[] =
  41. {
  42. {"M[4:0]", 5},
  43. {"T", 1},
  44. {"F", 1},
  45. {"I", 1},
  46. {"reserved", 16},
  47. {"J", 1},
  48. {"reserved", 2},
  49. {"Q", 1},
  50. {"V", 1},
  51. {"C", 1},
  52. {"Z", 1},
  53. {"N", 1},
  54. };
  55. char* armv4_5_core_reg_list[] =
  56. {
  57. "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
  58. "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
  59. "r13_irq", "lr_irq",
  60. "r13_svc", "lr_svc",
  61. "r13_abt", "lr_abt",
  62. "r13_und", "lr_und",
  63. "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
  64. };
  65. char * armv4_5_mode_strings_list[] =
  66. {
  67. "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
  68. };
  69. /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
  70. char** armv4_5_mode_strings = armv4_5_mode_strings_list+1;
  71. char* armv4_5_state_strings[] =
  72. {
  73. "ARM", "Thumb", "Jazelle"
  74. };
  75. int armv4_5_core_reg_arch_type = -1;
  76. armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
  77. {
  78. {0, ARMV4_5_MODE_ANY, NULL, NULL},
  79. {1, ARMV4_5_MODE_ANY, NULL, NULL},
  80. {2, ARMV4_5_MODE_ANY, NULL, NULL},
  81. {3, ARMV4_5_MODE_ANY, NULL, NULL},
  82. {4, ARMV4_5_MODE_ANY, NULL, NULL},
  83. {5, ARMV4_5_MODE_ANY, NULL, NULL},
  84. {6, ARMV4_5_MODE_ANY, NULL, NULL},
  85. {7, ARMV4_5_MODE_ANY, NULL, NULL},
  86. {8, ARMV4_5_MODE_ANY, NULL, NULL},
  87. {9, ARMV4_5_MODE_ANY, NULL, NULL},
  88. {10, ARMV4_5_MODE_ANY, NULL, NULL},
  89. {11, ARMV4_5_MODE_ANY, NULL, NULL},
  90. {12, ARMV4_5_MODE_ANY, NULL, NULL},
  91. {13, ARMV4_5_MODE_USR, NULL, NULL},
  92. {14, ARMV4_5_MODE_USR, NULL, NULL},
  93. {15, ARMV4_5_MODE_ANY, NULL, NULL},
  94. {8, ARMV4_5_MODE_FIQ, NULL, NULL},
  95. {9, ARMV4_5_MODE_FIQ, NULL, NULL},
  96. {10, ARMV4_5_MODE_FIQ, NULL, NULL},
  97. {11, ARMV4_5_MODE_FIQ, NULL, NULL},
  98. {12, ARMV4_5_MODE_FIQ, NULL, NULL},
  99. {13, ARMV4_5_MODE_FIQ, NULL, NULL},
  100. {14, ARMV4_5_MODE_FIQ, NULL, NULL},
  101. {13, ARMV4_5_MODE_IRQ, NULL, NULL},
  102. {14, ARMV4_5_MODE_IRQ, NULL, NULL},
  103. {13, ARMV4_5_MODE_SVC, NULL, NULL},
  104. {14, ARMV4_5_MODE_SVC, NULL, NULL},
  105. {13, ARMV4_5_MODE_ABT, NULL, NULL},
  106. {14, ARMV4_5_MODE_ABT, NULL, NULL},
  107. {13, ARMV4_5_MODE_UND, NULL, NULL},
  108. {14, ARMV4_5_MODE_UND, NULL, NULL},
  109. {16, ARMV4_5_MODE_ANY, NULL, NULL},
  110. {16, ARMV4_5_MODE_FIQ, NULL, NULL},
  111. {16, ARMV4_5_MODE_IRQ, NULL, NULL},
  112. {16, ARMV4_5_MODE_SVC, NULL, NULL},
  113. {16, ARMV4_5_MODE_ABT, NULL, NULL},
  114. {16, ARMV4_5_MODE_UND, NULL, NULL}
  115. };
  116. /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
  117. int armv4_5_core_reg_map[7][17] =
  118. {
  119. { /* USR */
  120. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
  121. },
  122. { /* FIQ */
  123. 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
  124. },
  125. { /* IRQ */
  126. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
  127. },
  128. { /* SVC */
  129. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
  130. },
  131. { /* ABT */
  132. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
  133. },
  134. { /* UND */
  135. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
  136. },
  137. { /* SYS */
  138. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
  139. }
  140. };
  141. u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  142. reg_t armv4_5_gdb_dummy_fp_reg =
  143. {
  144. "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  145. };
  146. u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  147. reg_t armv4_5_gdb_dummy_fps_reg =
  148. {
  149. "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  150. };
  151. int armv4_5_get_core_reg(reg_t *reg)
  152. {
  153. int retval;
  154. armv4_5_core_reg_t *armv4_5 = reg->arch_info;
  155. target_t *target = armv4_5->target;
  156. if (target->state != TARGET_HALTED)
  157. {
  158. LOG_ERROR("Target not halted");
  159. return ERROR_TARGET_NOT_HALTED;
  160. }
  161. /* retval = armv4_5->armv4_5_common->full_context(target); */
  162. retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
  163. return retval;
  164. }
  165. int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
  166. {
  167. armv4_5_core_reg_t *armv4_5 = reg->arch_info;
  168. target_t *target = armv4_5->target;
  169. armv4_5_common_t *armv4_5_target = target->arch_info;
  170. u32 value = buf_get_u32(buf, 0, 32);
  171. if (target->state != TARGET_HALTED)
  172. {
  173. return ERROR_TARGET_NOT_HALTED;
  174. }
  175. if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
  176. {
  177. if (value & 0x20)
  178. {
  179. /* T bit should be set */
  180. if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
  181. {
  182. /* change state to Thumb */
  183. LOG_DEBUG("changing to Thumb state");
  184. armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
  185. }
  186. }
  187. else
  188. {
  189. /* T bit should be cleared */
  190. if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
  191. {
  192. /* change state to ARM */
  193. LOG_DEBUG("changing to ARM state");
  194. armv4_5_target->core_state = ARMV4_5_STATE_ARM;
  195. }
  196. }
  197. if (armv4_5_target->core_mode != (value & 0x1f))
  198. {
  199. LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
  200. armv4_5_target->core_mode = value & 0x1f;
  201. armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
  202. }
  203. }
  204. buf_set_u32(reg->value, 0, 32, value);
  205. reg->dirty = 1;
  206. reg->valid = 1;
  207. return ERROR_OK;
  208. }
  209. int armv4_5_invalidate_core_regs(target_t *target)
  210. {
  211. armv4_5_common_t *armv4_5 = target->arch_info;
  212. int i;
  213. for (i = 0; i < 37; i++)
  214. {
  215. armv4_5->core_cache->reg_list[i].valid = 0;
  216. armv4_5->core_cache->reg_list[i].dirty = 0;
  217. }
  218. return ERROR_OK;
  219. }
  220. reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
  221. {
  222. int num_regs = 37;
  223. reg_cache_t *cache = malloc(sizeof(reg_cache_t));
  224. reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
  225. armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
  226. int i;
  227. cache->name = "arm v4/5 registers";
  228. cache->next = NULL;
  229. cache->reg_list = reg_list;
  230. cache->num_regs = num_regs;
  231. if (armv4_5_core_reg_arch_type == -1)
  232. armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
  233. register_init_dummy(&armv4_5_gdb_dummy_fp_reg);
  234. register_init_dummy(&armv4_5_gdb_dummy_fps_reg);
  235. for (i = 0; i < 37; i++)
  236. {
  237. arch_info[i] = armv4_5_core_reg_list_arch_info[i];
  238. arch_info[i].target = target;
  239. arch_info[i].armv4_5_common = armv4_5_common;
  240. reg_list[i].name = armv4_5_core_reg_list[i];
  241. reg_list[i].size = 32;
  242. reg_list[i].value = calloc(1, 4);
  243. reg_list[i].dirty = 0;
  244. reg_list[i].valid = 0;
  245. reg_list[i].bitfield_desc = NULL;
  246. reg_list[i].num_bitfields = 0;
  247. reg_list[i].arch_type = armv4_5_core_reg_arch_type;
  248. reg_list[i].arch_info = &arch_info[i];
  249. }
  250. return cache;
  251. }
  252. int armv4_5_arch_state(struct target_s *target)
  253. {
  254. armv4_5_common_t *armv4_5 = target->arch_info;
  255. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  256. {
  257. LOG_ERROR("BUG: called for a non-ARMv4/5 target");
  258. exit(-1);
  259. }
  260. LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
  261. armv4_5_state_strings[armv4_5->core_state],
  262. Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
  263. armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
  264. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  265. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  266. return ERROR_OK;
  267. }
  268. int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  269. {
  270. char output[128];
  271. int output_len;
  272. int mode, num;
  273. target_t *target = get_current_target(cmd_ctx);
  274. armv4_5_common_t *armv4_5 = target->arch_info;
  275. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  276. {
  277. command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
  278. return ERROR_OK;
  279. }
  280. if (target->state != TARGET_HALTED)
  281. {
  282. command_print(cmd_ctx, "error: target must be halted for register accesses");
  283. return ERROR_OK;
  284. }
  285. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  286. return ERROR_FAIL;
  287. for (num = 0; num <= 15; num++)
  288. {
  289. output_len = 0;
  290. for (mode = 0; mode < 6; mode++)
  291. {
  292. if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
  293. {
  294. armv4_5->full_context(target);
  295. }
  296. output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
  297. buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
  298. }
  299. command_print(cmd_ctx, output);
  300. }
  301. command_print(cmd_ctx, " cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
  302. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  303. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
  304. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
  305. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
  306. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
  307. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
  308. return ERROR_OK;
  309. }
  310. int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  311. {
  312. target_t *target = get_current_target(cmd_ctx);
  313. armv4_5_common_t *armv4_5 = target->arch_info;
  314. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  315. {
  316. command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
  317. return ERROR_OK;
  318. }
  319. if (argc > 0)
  320. {
  321. if (strcmp(args[0], "arm") == 0)
  322. {
  323. armv4_5->core_state = ARMV4_5_STATE_ARM;
  324. }
  325. if (strcmp(args[0], "thumb") == 0)
  326. {
  327. armv4_5->core_state = ARMV4_5_STATE_THUMB;
  328. }
  329. }
  330. command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
  331. return ERROR_OK;
  332. }
  333. int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  334. {
  335. int retval = ERROR_OK;
  336. target_t *target = get_current_target(cmd_ctx);
  337. armv4_5_common_t *armv4_5 = target->arch_info;
  338. u32 address;
  339. int count;
  340. int i;
  341. arm_instruction_t cur_instruction;
  342. u32 opcode;
  343. u16 thumb_opcode;
  344. int thumb = 0;
  345. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  346. {
  347. command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
  348. return ERROR_OK;
  349. }
  350. if (argc < 2)
  351. {
  352. command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
  353. return ERROR_OK;
  354. }
  355. address = strtoul(args[0], NULL, 0);
  356. count = strtoul(args[1], NULL, 0);
  357. if (argc >= 3)
  358. if (strcmp(args[2], "thumb") == 0)
  359. thumb = 1;
  360. for (i = 0; i < count; i++)
  361. {
  362. if(thumb)
  363. {
  364. if((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
  365. {
  366. return retval;
  367. }
  368. if((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
  369. {
  370. return retval;
  371. }
  372. }
  373. else {
  374. if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
  375. {
  376. return retval;
  377. }
  378. if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
  379. {
  380. return retval;
  381. }
  382. }
  383. command_print(cmd_ctx, "%s", cur_instruction.text);
  384. address += (thumb) ? 2 : 4;
  385. }
  386. return ERROR_OK;
  387. }
  388. int armv4_5_register_commands(struct command_context_s *cmd_ctx)
  389. {
  390. command_t *armv4_5_cmd;
  391. armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
  392. register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
  393. register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
  394. register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
  395. return ERROR_OK;
  396. }
  397. int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
  398. {
  399. armv4_5_common_t *armv4_5 = target->arch_info;
  400. int i;
  401. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  402. return ERROR_FAIL;
  403. *reg_list_size = 26;
  404. *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
  405. for (i = 0; i < 16; i++)
  406. {
  407. (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
  408. }
  409. for (i = 16; i < 24; i++)
  410. {
  411. (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
  412. }
  413. (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
  414. (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
  415. return ERROR_OK;
  416. }
  417. /* wait for execution to complete and check exit point */
  418. static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
  419. {
  420. int retval;
  421. armv4_5_common_t *armv4_5 = target->arch_info;
  422. if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
  423. {
  424. return retval;
  425. }
  426. if (target->state != TARGET_HALTED)
  427. {
  428. if ((retval=target_halt(target))!=ERROR_OK)
  429. return retval;
  430. if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
  431. {
  432. return retval;
  433. }
  434. return ERROR_TARGET_TIMEOUT;
  435. }
  436. if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)
  437. {
  438. LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
  439. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  440. return ERROR_TARGET_TIMEOUT;
  441. }
  442. return ERROR_OK;
  443. }
  444. int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
  445. {
  446. armv4_5_common_t *armv4_5 = target->arch_info;
  447. armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
  448. enum armv4_5_state core_state = armv4_5->core_state;
  449. enum armv4_5_mode core_mode = armv4_5->core_mode;
  450. u32 context[17];
  451. u32 cpsr;
  452. int exit_breakpoint_size = 0;
  453. int i;
  454. int retval = ERROR_OK;
  455. LOG_DEBUG("Running algorithm");
  456. if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
  457. {
  458. LOG_ERROR("current target isn't an ARMV4/5 target");
  459. return ERROR_TARGET_INVALID;
  460. }
  461. if (target->state != TARGET_HALTED)
  462. {
  463. LOG_WARNING("target not halted");
  464. return ERROR_TARGET_NOT_HALTED;
  465. }
  466. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  467. return ERROR_FAIL;
  468. for (i = 0; i <= 16; i++)
  469. {
  470. if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
  471. armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
  472. context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
  473. }
  474. cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
  475. for (i = 0; i < num_mem_params; i++)
  476. {
  477. if((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
  478. {
  479. return retval;
  480. }
  481. }
  482. for (i = 0; i < num_reg_params; i++)
  483. {
  484. reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
  485. if (!reg)
  486. {
  487. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  488. exit(-1);
  489. }
  490. if (reg->size != reg_params[i].size)
  491. {
  492. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
  493. exit(-1);
  494. }
  495. if((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
  496. {
  497. return retval;
  498. }
  499. }
  500. armv4_5->core_state = armv4_5_algorithm_info->core_state;
  501. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  502. exit_breakpoint_size = 4;
  503. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  504. exit_breakpoint_size = 2;
  505. else
  506. {
  507. LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
  508. exit(-1);
  509. }
  510. if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
  511. {
  512. LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
  513. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
  514. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  515. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  516. }
  517. if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
  518. {
  519. LOG_ERROR("can't add breakpoint to finish algorithm execution");
  520. return ERROR_TARGET_FAILURE;
  521. }
  522. if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
  523. {
  524. return retval;
  525. }
  526. int retvaltemp;
  527. retval=run_it(target, exit_point, timeout_ms, arch_info);
  528. breakpoint_remove(target, exit_point);
  529. if (retval!=ERROR_OK)
  530. return retval;
  531. for (i = 0; i < num_mem_params; i++)
  532. {
  533. if (mem_params[i].direction != PARAM_OUT)
  534. if((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
  535. {
  536. retval = retvaltemp;
  537. }
  538. }
  539. for (i = 0; i < num_reg_params; i++)
  540. {
  541. if (reg_params[i].direction != PARAM_OUT)
  542. {
  543. reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
  544. if (!reg)
  545. {
  546. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  547. exit(-1);
  548. }
  549. if (reg->size != reg_params[i].size)
  550. {
  551. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
  552. exit(-1);
  553. }
  554. buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
  555. }
  556. }
  557. for (i = 0; i <= 16; i++)
  558. {
  559. LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
  560. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
  561. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
  562. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
  563. }
  564. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
  565. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  566. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  567. armv4_5->core_state = core_state;
  568. armv4_5->core_mode = core_mode;
  569. return retval;
  570. }
  571. int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
  572. {
  573. return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
  574. }
  575. int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
  576. {
  577. target->arch_info = armv4_5;
  578. armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
  579. armv4_5->core_state = ARMV4_5_STATE_ARM;
  580. armv4_5->core_mode = ARMV4_5_MODE_USR;
  581. return ERROR_OK;
  582. }