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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename openocd.info
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
  20. @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
  22. @item Copyright @copyright{} 2009-2010 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developer Resources
  53. * Debug Adapter Hardware:: Debug Adapter Hardware
  54. * About Jim-Tcl:: About Jim-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Server Configuration:: Server Configuration
  59. * Debug Adapter Configuration:: Debug Adapter Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * Flash Programming:: Flash Programming
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * Utility Commands:: Utility Commands
  71. * TFTP:: TFTP
  72. * GDB and OpenOCD:: Using GDB and OpenOCD
  73. * Tcl Scripting API:: Tcl Scripting API
  74. * FAQ:: Frequently Asked Questions
  75. * Tcl Crash Course:: Tcl Crash Course
  76. * License:: GNU Free Documentation License
  77. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  78. @comment case issue with ``Index.html'' and ``index.html''
  79. @comment Occurs when creating ``--html --no-split'' output
  80. @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
  81. * OpenOCD Concept Index:: Concept Index
  82. * Command and Driver Index:: Command and Driver Index
  83. @end menu
  84. @node About
  85. @unnumbered About
  86. @cindex about
  87. OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
  88. at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
  89. Since that time, the project has grown into an active open-source project,
  90. supported by a diverse community of software and hardware developers from
  91. around the world.
  92. @section What is OpenOCD?
  93. @cindex TAP
  94. @cindex JTAG
  95. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  96. in-system programming and boundary-scan testing for embedded target
  97. devices.
  98. It does so with the assistance of a @dfn{debug adapter}, which is
  99. a small hardware module which helps provide the right kind of
  100. electrical signaling to the target being debugged. These are
  101. required since the debug host (on which OpenOCD runs) won't
  102. usually have native support for such signaling, or the connector
  103. needed to hook up to the target.
  104. Such debug adapters support one or more @dfn{transport} protocols,
  105. each of which involves different electrical signaling (and uses
  106. different messaging protocols on top of that signaling). There
  107. are many types of debug adapter, and little uniformity in what
  108. they are called. (There are also product naming differences.)
  109. These adapters are sometimes packaged as discrete dongles, which
  110. may generically be called @dfn{hardware interface dongles}.
  111. Some development boards also integrate them directly, which may
  112. let the development board connect directly to the debug
  113. host over USB (and sometimes also to power it over USB).
  114. For example, a @dfn{JTAG Adapter} supports JTAG
  115. signaling, and is used to communicate
  116. with JTAG (IEEE 1149.1) compliant TAPs on your target board.
  117. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  118. special instructions and data. TAPs are daisy-chained within and
  119. between chips and boards. JTAG supports debugging and boundary
  120. scan operations.
  121. There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
  122. signaling to communicate with some newer ARM cores, as well as debug
  123. adapters which support both JTAG and SWD transports. SWD supports only
  124. debugging, whereas JTAG also supports boundary scan operations.
  125. For some chips, there are also @dfn{Programming Adapters} supporting
  126. special transports used only to write code to flash memory, without
  127. support for on-chip debugging or boundary scan.
  128. (At this writing, OpenOCD does not support such non-debug adapters.)
  129. @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
  130. USB-based, parallel port-based, and other standalone boxes that run
  131. OpenOCD internally. @xref{Debug Adapter Hardware}.
  132. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  133. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
  134. (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
  135. Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
  136. @b{Flash Programming:} Flash writing is supported for external
  137. CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
  138. internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
  139. STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
  140. controllers (LPC3180, Orion, S3C24xx, more) is included.
  141. @section OpenOCD Web Site
  142. The OpenOCD web site provides the latest public news from the community:
  143. @uref{http://openocd.org/}
  144. @section Latest User's Guide:
  145. The user's guide you are now reading may not be the latest one
  146. available. A version for more recent code may be available.
  147. Its HTML form is published regularly at:
  148. @uref{http://openocd.org/doc/html/index.html}
  149. PDF form is likewise published at:
  150. @uref{http://openocd.org/doc/pdf/openocd.pdf}
  151. @section OpenOCD User's Forum
  152. There is an OpenOCD forum (phpBB) hosted by SparkFun,
  153. which might be helpful to you. Note that if you want
  154. anything to come to the attention of developers, you
  155. should post it to the OpenOCD Developer Mailing List
  156. instead of this forum.
  157. @uref{http://forum.sparkfun.com/viewforum.php?f=18}
  158. @section OpenOCD User's Mailing List
  159. The OpenOCD User Mailing List provides the primary means of
  160. communication between users:
  161. @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
  162. @section OpenOCD IRC
  163. Support can also be found on irc:
  164. @uref{irc://irc.freenode.net/openocd}
  165. @node Developers
  166. @chapter OpenOCD Developer Resources
  167. @cindex developers
  168. If you are interested in improving the state of OpenOCD's debugging and
  169. testing support, new contributions will be welcome. Motivated developers
  170. can produce new target, flash or interface drivers, improve the
  171. documentation, as well as more conventional bug fixes and enhancements.
  172. The resources in this chapter are available for developers wishing to explore
  173. or expand the OpenOCD source code.
  174. @section OpenOCD Git Repository
  175. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  176. a Git repository hosted at SourceForge. The repository URL is:
  177. @uref{git://git.code.sf.net/p/openocd/code}
  178. or via http
  179. @uref{http://git.code.sf.net/p/openocd/code}
  180. You may prefer to use a mirror and the HTTP protocol:
  181. @uref{http://repo.or.cz/r/openocd.git}
  182. With standard Git tools, use @command{git clone} to initialize
  183. a local repository, and @command{git pull} to update it.
  184. There are also gitweb pages letting you browse the repository
  185. with a web browser, or download arbitrary snapshots without
  186. needing a Git client:
  187. @uref{http://repo.or.cz/w/openocd.git}
  188. The @file{README} file contains the instructions for building the project
  189. from the repository or a snapshot.
  190. Developers that want to contribute patches to the OpenOCD system are
  191. @b{strongly} encouraged to work against mainline.
  192. Patches created against older versions may require additional
  193. work from their submitter in order to be updated for newer releases.
  194. @section Doxygen Developer Manual
  195. During the 0.2.x release cycle, the OpenOCD project began
  196. providing a Doxygen reference manual. This document contains more
  197. technical information about the software internals, development
  198. processes, and similar documentation:
  199. @uref{http://openocd.org/doc/doxygen/html/index.html}
  200. This document is a work-in-progress, but contributions would be welcome
  201. to fill in the gaps. All of the source files are provided in-tree,
  202. listed in the Doxyfile configuration at the top of the source tree.
  203. @section Gerrit Review System
  204. All changes in the OpenOCD Git repository go through the web-based Gerrit
  205. Code Review System:
  206. @uref{http://openocd.zylin.com/}
  207. After a one-time registration and repository setup, anyone can push commits
  208. from their local Git repository directly into Gerrit.
  209. All users and developers are encouraged to review, test, discuss and vote
  210. for changes in Gerrit. The feedback provides the basis for a maintainer to
  211. eventually submit the change to the main Git repository.
  212. The @file{HACKING} file, also available as the Patch Guide in the Doxygen
  213. Developer Manual, contains basic information about how to connect a
  214. repository to Gerrit, prepare and push patches. Patch authors are expected to
  215. maintain their changes while they're in Gerrit, respond to feedback and if
  216. necessary rework and push improved versions of the change.
  217. @section OpenOCD Developer Mailing List
  218. The OpenOCD Developer Mailing List provides the primary means of
  219. communication between developers:
  220. @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
  221. @section OpenOCD Bug Tracker
  222. The OpenOCD Bug Tracker is hosted on SourceForge:
  223. @uref{http://bugs.openocd.org/}
  224. @node Debug Adapter Hardware
  225. @chapter Debug Adapter Hardware
  226. @cindex dongles
  227. @cindex FTDI
  228. @cindex wiggler
  229. @cindex zy1000
  230. @cindex printer port
  231. @cindex USB Adapter
  232. @cindex RTCK
  233. Defined: @b{dongle}: A small device that plugs into a computer and serves as
  234. an adapter .... [snip]
  235. In the OpenOCD case, this generally refers to @b{a small adapter} that
  236. attaches to your computer via USB or the parallel port. One
  237. exception is the Ultimate Solutions ZY1000, packaged as a small box you
  238. attach via an ethernet cable. The ZY1000 has the advantage that it does not
  239. require any drivers to be installed on the developer PC. It also has
  240. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  241. and has a built-in relay to power cycle targets remotely.
  242. @section Choosing a Dongle
  243. There are several things you should keep in mind when choosing a dongle.
  244. @enumerate
  245. @item @b{Transport} Does it support the kind of communication that you need?
  246. OpenOCD focusses mostly on JTAG. Your version may also support
  247. other ways to communicate with target devices.
  248. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  249. Does your dongle support it? You might need a level converter.
  250. @item @b{Pinout} What pinout does your target board use?
  251. Does your dongle support it? You may be able to use jumper
  252. wires, or an "octopus" connector, to convert pinouts.
  253. @item @b{Connection} Does your computer have the USB, parallel, or
  254. Ethernet port needed?
  255. @item @b{RTCK} Do you expect to use it with ARM chips and boards with
  256. RTCK support (also known as ``adaptive clocking'')?
  257. @end enumerate
  258. @section Stand-alone JTAG Probe
  259. The ZY1000 from Ultimate Solutions is technically not a dongle but a
  260. stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
  261. running on the developer's host computer.
  262. Once installed on a network using DHCP or a static IP assignment, users can
  263. access the ZY1000 probe locally or remotely from any host with access to the
  264. IP address assigned to the probe.
  265. The ZY1000 provides an intuitive web interface with direct access to the
  266. OpenOCD debugger.
  267. Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
  268. of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
  269. the target.
  270. The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
  271. to power cycle the target remotely.
  272. For more information, visit:
  273. @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
  274. @section USB FT2232 Based
  275. There are many USB JTAG dongles on the market, many of them based
  276. on a chip from ``Future Technology Devices International'' (FTDI)
  277. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  278. See: @url{http://www.ftdichip.com} for more information.
  279. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  280. chips started to become available in JTAG adapters. Around 2012, a new
  281. variant appeared - FT232H - this is a single-channel version of FT2232H.
  282. (Adapters using those high speed FT2232H or FT232H chips may support adaptive
  283. clocking.)
  284. The FT2232 chips are flexible enough to support some other
  285. transport options, such as SWD or the SPI variants used to
  286. program some chips. They have two communications channels,
  287. and one can be used for a UART adapter at the same time the
  288. other one is used to provide a debug adapter.
  289. Also, some development boards integrate an FT2232 chip to serve as
  290. a built-in low-cost debug adapter and USB-to-serial solution.
  291. @itemize @bullet
  292. @item @b{usbjtag}
  293. @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
  294. @item @b{jtagkey}
  295. @* See: @url{http://www.amontec.com/jtagkey.shtml}
  296. @item @b{jtagkey2}
  297. @* See: @url{http://www.amontec.com/jtagkey2.shtml}
  298. @item @b{oocdlink}
  299. @* See: @url{http://www.oocdlink.com} By Joern Kaipf
  300. @item @b{signalyzer}
  301. @* See: @url{http://www.signalyzer.com}
  302. @item @b{Stellaris Eval Boards}
  303. @* See: @url{http://www.ti.com} - The Stellaris eval boards
  304. bundle FT2232-based JTAG and SWD support, which can be used to debug
  305. the Stellaris chips. Using separate JTAG adapters is optional.
  306. These boards can also be used in a "pass through" mode as JTAG adapters
  307. to other target boards, disabling the Stellaris chip.
  308. @item @b{TI/Luminary ICDI}
  309. @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
  310. Interface (ICDI) Boards are included in Stellaris LM3S9B9x
  311. Evaluation Kits. Like the non-detachable FT2232 support on the other
  312. Stellaris eval boards, they can be used to debug other target boards.
  313. @item @b{olimex-jtag}
  314. @* See: @url{http://www.olimex.com}
  315. @item @b{Flyswatter/Flyswatter2}
  316. @* See: @url{http://www.tincantools.com}
  317. @item @b{turtelizer2}
  318. @* See:
  319. @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
  320. @url{http://www.ethernut.de}
  321. @item @b{comstick}
  322. @* Link: @url{http://www.hitex.com/index.php?id=383}
  323. @item @b{stm32stick}
  324. @* Link @url{http://www.hitex.com/stm32-stick}
  325. @item @b{axm0432_jtag}
  326. @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
  327. to be available anymore as of April 2012.
  328. @item @b{cortino}
  329. @* Link @url{http://www.hitex.com/index.php?id=cortino}
  330. @item @b{dlp-usb1232h}
  331. @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
  332. @item @b{digilent-hs1}
  333. @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
  334. @item @b{opendous}
  335. @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
  336. (OpenHardware).
  337. @item @b{JTAG-lock-pick Tiny 2}
  338. @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
  339. @item @b{GW16042}
  340. @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
  341. FT2232H-based
  342. @end itemize
  343. @section USB-JTAG / Altera USB-Blaster compatibles
  344. These devices also show up as FTDI devices, but are not
  345. protocol-compatible with the FT2232 devices. They are, however,
  346. protocol-compatible among themselves. USB-JTAG devices typically consist
  347. of a FT245 followed by a CPLD that understands a particular protocol,
  348. or emulates this protocol using some other hardware.
  349. They may appear under different USB VID/PID depending on the particular
  350. product. The driver can be configured to search for any VID/PID pair
  351. (see the section on driver commands).
  352. @itemize
  353. @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
  354. @* Link: @url{http://ixo-jtag.sourceforge.net/}
  355. @item @b{Altera USB-Blaster}
  356. @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
  357. @end itemize
  358. @section USB J-Link based
  359. There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
  360. an example of a microcontroller based JTAG adapter, it uses an
  361. AT91SAM764 internally.
  362. @itemize @bullet
  363. @item @b{SEGGER J-Link}
  364. @* Link: @url{http://www.segger.com/jlink.html}
  365. @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
  366. @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
  367. @item @b{IAR J-Link}
  368. @end itemize
  369. @section USB RLINK based
  370. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
  371. permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
  372. SWD and not JTAG, thus not supported.
  373. @itemize @bullet
  374. @item @b{Raisonance RLink}
  375. @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
  376. @item @b{STM32 Primer}
  377. @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
  378. @item @b{STM32 Primer2}
  379. @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
  380. @end itemize
  381. @section USB ST-LINK based
  382. STMicroelectronics has an adapter called @b{ST-LINK}.
  383. They only work with STMicroelectronics chips, notably STM32 and STM8.
  384. @itemize @bullet
  385. @item @b{ST-LINK}
  386. @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
  387. @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
  388. @item @b{ST-LINK/V2}
  389. @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
  390. @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
  391. @item @b{STLINK-V3}
  392. @* This is available standalone and as part of some kits.
  393. @* Link: @url{http://www.st.com/stlink-v3}
  394. @end itemize
  395. For info the original ST-LINK enumerates using the mass storage usb class; however,
  396. its implementation is completely broken. The result is this causes issues under Linux.
  397. The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
  398. @itemize @bullet
  399. @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
  400. @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
  401. @end itemize
  402. @section USB TI/Stellaris ICDI based
  403. Texas Instruments has an adapter called @b{ICDI}.
  404. It is not to be confused with the FTDI based adapters that were originally fitted to their
  405. evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
  406. @section USB CMSIS-DAP based
  407. ARM has released a interface standard called CMSIS-DAP that simplifies connecting
  408. debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
  409. @section USB Other
  410. @itemize @bullet
  411. @item @b{USBprog}
  412. @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
  413. @item @b{USB - Presto}
  414. @* Link: @url{http://tools.asix.net/prg_presto.htm}
  415. @item @b{Versaloon-Link}
  416. @* Link: @url{http://www.versaloon.com}
  417. @item @b{ARM-JTAG-EW}
  418. @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
  419. @item @b{Buspirate}
  420. @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
  421. @item @b{opendous}
  422. @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
  423. @item @b{estick}
  424. @* Link: @url{http://code.google.com/p/estick-jtag/}
  425. @item @b{Keil ULINK v1}
  426. @* Link: @url{http://www.keil.com/ulink1/}
  427. @item @b{TI XDS110 Debug Probe}
  428. @* The XDS110 is included as the embedded debug probe on many Texas Instruments
  429. LaunchPad evaluation boards.
  430. @* The XDS110 is also available as a stand-alone USB debug probe. The XDS110
  431. stand-alone probe has the additional ability to supply voltage to the target
  432. board via its AUX FUNCTIONS port. Use the
  433. @command{xds110_supply_voltage <millivolts>} command to set the voltage. 0 turns
  434. off the supply. Otherwise, the supply can be set to any value in the range 1800
  435. to 3600 millivolts.
  436. @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
  437. @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
  438. @end itemize
  439. @section IBM PC Parallel Printer Port Based
  440. The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
  441. and the Macraigor Wiggler. There are many clones and variations of
  442. these on the market.
  443. Note that parallel ports are becoming much less common, so if you
  444. have the choice you should probably avoid these adapters in favor
  445. of USB-based ones.
  446. @itemize @bullet
  447. @item @b{Wiggler} - There are many clones of this.
  448. @* Link: @url{http://www.macraigor.com/wiggler.htm}
  449. @item @b{DLC5} - From XILINX - There are many clones of this
  450. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  451. produced, PDF schematics are easily found and it is easy to make.
  452. @item @b{Amontec - JTAG Accelerator}
  453. @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
  454. @item @b{Wiggler2}
  455. @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
  456. @item @b{Wiggler_ntrst_inverted}
  457. @* Yet another variation - See the source code, src/jtag/parport.c
  458. @item @b{old_amt_wiggler}
  459. @* Unknown - probably not on the market today
  460. @item @b{arm-jtag}
  461. @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
  462. @item @b{chameleon}
  463. @* Link: @url{http://www.amontec.com/chameleon.shtml}
  464. @item @b{Triton}
  465. @* Unknown.
  466. @item @b{Lattice}
  467. @* ispDownload from Lattice Semiconductor
  468. @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
  469. @item @b{flashlink}
  470. @* From STMicroelectronics;
  471. @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
  472. @end itemize
  473. @section Other...
  474. @itemize @bullet
  475. @item @b{ep93xx}
  476. @* An EP93xx based Linux machine using the GPIO pins directly.
  477. @item @b{at91rm9200}
  478. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  479. @item @b{bcm2835gpio}
  480. @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
  481. @item @b{imx_gpio}
  482. @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
  483. @item @b{jtag_vpi}
  484. @* A JTAG driver acting as a client for the JTAG VPI server interface.
  485. @* Link: @url{http://github.com/fjullien/jtag_vpi}
  486. @end itemize
  487. @node About Jim-Tcl
  488. @chapter About Jim-Tcl
  489. @cindex Jim-Tcl
  490. @cindex tcl
  491. OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
  492. This programming language provides a simple and extensible
  493. command interpreter.
  494. All commands presented in this Guide are extensions to Jim-Tcl.
  495. You can use them as simple commands, without needing to learn
  496. much of anything about Tcl.
  497. Alternatively, you can write Tcl programs with them.
  498. You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
  499. There is an active and responsive community, get on the mailing list
  500. if you have any questions. Jim-Tcl maintainers also lurk on the
  501. OpenOCD mailing list.
  502. @itemize @bullet
  503. @item @b{Jim vs. Tcl}
  504. @* Jim-Tcl is a stripped down version of the well known Tcl language,
  505. which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
  506. fewer features. Jim-Tcl is several dozens of .C files and .H files and
  507. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  508. 4.2 MB .zip file containing 1540 files.
  509. @item @b{Missing Features}
  510. @* Our practice has been: Add/clone the real Tcl feature if/when
  511. needed. We welcome Jim-Tcl improvements, not bloat. Also there
  512. are a large number of optional Jim-Tcl features that are not
  513. enabled in OpenOCD.
  514. @item @b{Scripts}
  515. @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
  516. command interpreter today is a mixture of (newer)
  517. Jim-Tcl commands, and the (older) original command interpreter.
  518. @item @b{Commands}
  519. @* At the OpenOCD telnet command line (or via the GDB monitor command) one
  520. can type a Tcl for() loop, set variables, etc.
  521. Some of the commands documented in this guide are implemented
  522. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  523. @item @b{Historical Note}
  524. @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
  525. before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
  526. as a Git submodule, which greatly simplified upgrading Jim-Tcl
  527. to benefit from new features and bugfixes in Jim-Tcl.
  528. @item @b{Need a crash course in Tcl?}
  529. @*@xref{Tcl Crash Course}.
  530. @end itemize
  531. @node Running
  532. @chapter Running
  533. @cindex command line options
  534. @cindex logfile
  535. @cindex directory search
  536. Properly installing OpenOCD sets up your operating system to grant it access
  537. to the debug adapters. On Linux, this usually involves installing a file
  538. in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
  539. that works for many common adapters is shipped with OpenOCD in the
  540. @file{contrib} directory. MS-Windows needs
  541. complex and confusing driver configuration for every peripheral. Such issues
  542. are unique to each operating system, and are not detailed in this User's Guide.
  543. Then later you will invoke the OpenOCD server, with various options to
  544. tell it how each debug session should work.
  545. The @option{--help} option shows:
  546. @verbatim
  547. bash$ openocd --help
  548. --help | -h display this help
  549. --version | -v display OpenOCD version
  550. --file | -f use configuration file <name>
  551. --search | -s dir to search for config files and scripts
  552. --debug | -d set debug level to 3
  553. | -d<n> set debug level to <level>
  554. --log_output | -l redirect log output to file <name>
  555. --command | -c run <command>
  556. @end verbatim
  557. If you don't give any @option{-f} or @option{-c} options,
  558. OpenOCD tries to read the configuration file @file{openocd.cfg}.
  559. To specify one or more different
  560. configuration files, use @option{-f} options. For example:
  561. @example
  562. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  563. @end example
  564. Configuration files and scripts are searched for in
  565. @enumerate
  566. @item the current directory,
  567. @item any search dir specified on the command line using the @option{-s} option,
  568. @item any search dir specified using the @command{add_script_search_dir} command,
  569. @item @file{$HOME/.openocd} (not on Windows),
  570. @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
  571. @item the site wide script library @file{$pkgdatadir/site} and
  572. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  573. @end enumerate
  574. The first found file with a matching file name will be used.
  575. @quotation Note
  576. Don't try to use configuration script names or paths which
  577. include the "#" character. That character begins Tcl comments.
  578. @end quotation
  579. @section Simple setup, no customization
  580. In the best case, you can use two scripts from one of the script
  581. libraries, hook up your JTAG adapter, and start the server ... and
  582. your JTAG setup will just work "out of the box". Always try to
  583. start by reusing those scripts, but assume you'll need more
  584. customization even if this works. @xref{OpenOCD Project Setup}.
  585. If you find a script for your JTAG adapter, and for your board or
  586. target, you may be able to hook up your JTAG adapter then start
  587. the server with some variation of one of the following:
  588. @example
  589. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  590. openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
  591. @end example
  592. You might also need to configure which reset signals are present,
  593. using @option{-c 'reset_config trst_and_srst'} or something similar.
  594. If all goes well you'll see output something like
  595. @example
  596. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  597. For bug reports, read
  598. http://openocd.org/doc/doxygen/bugs.html
  599. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  600. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  601. @end example
  602. Seeing that "tap/device found" message, and no warnings, means
  603. the JTAG communication is working. That's a key milestone, but
  604. you'll probably need more project-specific setup.
  605. @section What OpenOCD does as it starts
  606. OpenOCD starts by processing the configuration commands provided
  607. on the command line or, if there were no @option{-c command} or
  608. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  609. @xref{configurationstage,,Configuration Stage}.
  610. At the end of the configuration stage it verifies the JTAG scan
  611. chain defined using those commands; your configuration should
  612. ensure that this always succeeds.
  613. Normally, OpenOCD then starts running as a server.
  614. Alternatively, commands may be used to terminate the configuration
  615. stage early, perform work (such as updating some flash memory),
  616. and then shut down without acting as a server.
  617. Once OpenOCD starts running as a server, it waits for connections from
  618. clients (Telnet, GDB, RPC) and processes the commands issued through
  619. those channels.
  620. If you are having problems, you can enable internal debug messages via
  621. the @option{-d} option.
  622. Also it is possible to interleave Jim-Tcl commands w/config scripts using the
  623. @option{-c} command line switch.
  624. To enable debug output (when reporting problems or working on OpenOCD
  625. itself), use the @option{-d} command line switch. This sets the
  626. @option{debug_level} to "3", outputting the most information,
  627. including debug messages. The default setting is "2", outputting only
  628. informational messages, warnings and errors. You can also change this
  629. setting from within a telnet or gdb session using @command{debug_level<n>}
  630. (@pxref{debuglevel,,debug_level}).
  631. You can redirect all output from the server to a file using the
  632. @option{-l <logfile>} switch.
  633. Note! OpenOCD will launch the GDB & telnet server even if it can not
  634. establish a connection with the target. In general, it is possible for
  635. the JTAG controller to be unresponsive until the target is set up
  636. correctly via e.g. GDB monitor commands in a GDB init script.
  637. @node OpenOCD Project Setup
  638. @chapter OpenOCD Project Setup
  639. To use OpenOCD with your development projects, you need to do more than
  640. just connect the JTAG adapter hardware (dongle) to your development board
  641. and start the OpenOCD server.
  642. You also need to configure your OpenOCD server so that it knows
  643. about your adapter and board, and helps your work.
  644. You may also want to connect OpenOCD to GDB, possibly
  645. using Eclipse or some other GUI.
  646. @section Hooking up the JTAG Adapter
  647. Today's most common case is a dongle with a JTAG cable on one side
  648. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  649. and a USB cable on the other.
  650. Instead of USB, some cables use Ethernet;
  651. older ones may use a PC parallel port, or even a serial port.
  652. @enumerate
  653. @item @emph{Start with power to your target board turned off},
  654. and nothing connected to your JTAG adapter.
  655. If you're particularly paranoid, unplug power to the board.
  656. It's important to have the ground signal properly set up,
  657. unless you are using a JTAG adapter which provides
  658. galvanic isolation between the target board and the
  659. debugging host.
  660. @item @emph{Be sure it's the right kind of JTAG connector.}
  661. If your dongle has a 20-pin ARM connector, you need some kind
  662. of adapter (or octopus, see below) to hook it up to
  663. boards using 14-pin or 10-pin connectors ... or to 20-pin
  664. connectors which don't use ARM's pinout.
  665. In the same vein, make sure the voltage levels are compatible.
  666. Not all JTAG adapters have the level shifters needed to work
  667. with 1.2 Volt boards.
  668. @item @emph{Be certain the cable is properly oriented} or you might
  669. damage your board. In most cases there are only two possible
  670. ways to connect the cable.
  671. Connect the JTAG cable from your adapter to the board.
  672. Be sure it's firmly connected.
  673. In the best case, the connector is keyed to physically
  674. prevent you from inserting it wrong.
  675. This is most often done using a slot on the board's male connector
  676. housing, which must match a key on the JTAG cable's female connector.
  677. If there's no housing, then you must look carefully and
  678. make sure pin 1 on the cable hooks up to pin 1 on the board.
  679. Ribbon cables are frequently all grey except for a wire on one
  680. edge, which is red. The red wire is pin 1.
  681. Sometimes dongles provide cables where one end is an ``octopus'' of
  682. color coded single-wire connectors, instead of a connector block.
  683. These are great when converting from one JTAG pinout to another,
  684. but are tedious to set up.
  685. Use these with connector pinout diagrams to help you match up the
  686. adapter signals to the right board pins.
  687. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  688. A USB, parallel, or serial port connector will go to the host which
  689. you are using to run OpenOCD.
  690. For Ethernet, consult the documentation and your network administrator.
  691. For USB-based JTAG adapters you have an easy sanity check at this point:
  692. does the host operating system see the JTAG adapter? If you're running
  693. Linux, try the @command{lsusb} command. If that host is an
  694. MS-Windows host, you'll need to install a driver before OpenOCD works.
  695. @item @emph{Connect the adapter's power supply, if needed.}
  696. This step is primarily for non-USB adapters,
  697. but sometimes USB adapters need extra power.
  698. @item @emph{Power up the target board.}
  699. Unless you just let the magic smoke escape,
  700. you're now ready to set up the OpenOCD server
  701. so you can use JTAG to work with that board.
  702. @end enumerate
  703. Talk with the OpenOCD server using
  704. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  705. @xref{GDB and OpenOCD}.
  706. @section Project Directory
  707. There are many ways you can configure OpenOCD and start it up.
  708. A simple way to organize them all involves keeping a
  709. single directory for your work with a given board.
  710. When you start OpenOCD from that directory,
  711. it searches there first for configuration files, scripts,
  712. files accessed through semihosting,
  713. and for code you upload to the target board.
  714. It is also the natural place to write files,
  715. such as log files and data you download from the board.
  716. @section Configuration Basics
  717. There are two basic ways of configuring OpenOCD, and
  718. a variety of ways you can mix them.
  719. Think of the difference as just being how you start the server:
  720. @itemize
  721. @item Many @option{-f file} or @option{-c command} options on the command line
  722. @item No options, but a @dfn{user config file}
  723. in the current directory named @file{openocd.cfg}
  724. @end itemize
  725. Here is an example @file{openocd.cfg} file for a setup
  726. using a Signalyzer FT2232-based JTAG adapter to talk to
  727. a board with an Atmel AT91SAM7X256 microcontroller:
  728. @example
  729. source [find interface/ftdi/signalyzer.cfg]
  730. # GDB can also flash my flash!
  731. gdb_memory_map enable
  732. gdb_flash_program enable
  733. source [find target/sam7x256.cfg]
  734. @end example
  735. Here is the command line equivalent of that configuration:
  736. @example
  737. openocd -f interface/ftdi/signalyzer.cfg \
  738. -c "gdb_memory_map enable" \
  739. -c "gdb_flash_program enable" \
  740. -f target/sam7x256.cfg
  741. @end example
  742. You could wrap such long command lines in shell scripts,
  743. each supporting a different development task.
  744. One might re-flash the board with a specific firmware version.
  745. Another might set up a particular debugging or run-time environment.
  746. @quotation Important
  747. At this writing (October 2009) the command line method has
  748. problems with how it treats variables.
  749. For example, after @option{-c "set VAR value"}, or doing the
  750. same in a script, the variable @var{VAR} will have no value
  751. that can be tested in a later script.
  752. @end quotation
  753. Here we will focus on the simpler solution: one user config
  754. file, including basic configuration plus any TCL procedures
  755. to simplify your work.
  756. @section User Config Files
  757. @cindex config file, user
  758. @cindex user config file
  759. @cindex config file, overview
  760. A user configuration file ties together all the parts of a project
  761. in one place.
  762. One of the following will match your situation best:
  763. @itemize
  764. @item Ideally almost everything comes from configuration files
  765. provided by someone else.
  766. For example, OpenOCD distributes a @file{scripts} directory
  767. (probably in @file{/usr/share/openocd/scripts} on Linux).
  768. Board and tool vendors can provide these too, as can individual
  769. user sites; the @option{-s} command line option lets you say
  770. where to find these files. (@xref{Running}.)
  771. The AT91SAM7X256 example above works this way.
  772. Three main types of non-user configuration file each have their
  773. own subdirectory in the @file{scripts} directory:
  774. @enumerate
  775. @item @b{interface} -- one for each different debug adapter;
  776. @item @b{board} -- one for each different board
  777. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  778. @end enumerate
  779. Best case: include just two files, and they handle everything else.
  780. The first is an interface config file.
  781. The second is board-specific, and it sets up the JTAG TAPs and
  782. their GDB targets (by deferring to some @file{target.cfg} file),
  783. declares all flash memory, and leaves you nothing to do except
  784. meet your deadline:
  785. @example
  786. source [find interface/olimex-jtag-tiny.cfg]
  787. source [find board/csb337.cfg]
  788. @end example
  789. Boards with a single microcontroller often won't need more
  790. than the target config file, as in the AT91SAM7X256 example.
  791. That's because there is no external memory (flash, DDR RAM), and
  792. the board differences are encapsulated by application code.
  793. @item Maybe you don't know yet what your board looks like to JTAG.
  794. Once you know the @file{interface.cfg} file to use, you may
  795. need help from OpenOCD to discover what's on the board.
  796. Once you find the JTAG TAPs, you can just search for appropriate
  797. target and board
  798. configuration files ... or write your own, from the bottom up.
  799. @xref{autoprobing,,Autoprobing}.
  800. @item You can often reuse some standard config files but
  801. need to write a few new ones, probably a @file{board.cfg} file.
  802. You will be using commands described later in this User's Guide,
  803. and working with the guidelines in the next chapter.
  804. For example, there may be configuration files for your JTAG adapter
  805. and target chip, but you need a new board-specific config file
  806. giving access to your particular flash chips.
  807. Or you might need to write another target chip configuration file
  808. for a new chip built around the Cortex-M3 core.
  809. @quotation Note
  810. When you write new configuration files, please submit
  811. them for inclusion in the next OpenOCD release.
  812. For example, a @file{board/newboard.cfg} file will help the
  813. next users of that board, and a @file{target/newcpu.cfg}
  814. will help support users of any board using that chip.
  815. @end quotation
  816. @item
  817. You may may need to write some C code.
  818. It may be as simple as supporting a new FT2232 or parport
  819. based adapter; a bit more involved, like a NAND or NOR flash
  820. controller driver; or a big piece of work like supporting
  821. a new chip architecture.
  822. @end itemize
  823. Reuse the existing config files when you can.
  824. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  825. You may find a board configuration that's a good example to follow.
  826. When you write config files, separate the reusable parts
  827. (things every user of that interface, chip, or board needs)
  828. from ones specific to your environment and debugging approach.
  829. @itemize
  830. @item
  831. For example, a @code{gdb-attach} event handler that invokes
  832. the @command{reset init} command will interfere with debugging
  833. early boot code, which performs some of the same actions
  834. that the @code{reset-init} event handler does.
  835. @item
  836. Likewise, the @command{arm9 vector_catch} command (or
  837. @cindex vector_catch
  838. its siblings @command{xscale vector_catch}
  839. and @command{cortex_m vector_catch}) can be a time-saver
  840. during some debug sessions, but don't make everyone use that either.
  841. Keep those kinds of debugging aids in your user config file,
  842. along with messaging and tracing setup.
  843. (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
  844. @item
  845. You might need to override some defaults.
  846. For example, you might need to move, shrink, or back up the target's
  847. work area if your application needs much SRAM.
  848. @item
  849. TCP/IP port configuration is another example of something which
  850. is environment-specific, and should only appear in
  851. a user config file. @xref{tcpipports,,TCP/IP Ports}.
  852. @end itemize
  853. @section Project-Specific Utilities
  854. A few project-specific utility
  855. routines may well speed up your work.
  856. Write them, and keep them in your project's user config file.
  857. For example, if you are making a boot loader work on a
  858. board, it's nice to be able to debug the ``after it's
  859. loaded to RAM'' parts separately from the finicky early
  860. code which sets up the DDR RAM controller and clocks.
  861. A script like this one, or a more GDB-aware sibling,
  862. may help:
  863. @example
  864. proc ramboot @{ @} @{
  865. # Reset, running the target's "reset-init" scripts
  866. # to initialize clocks and the DDR RAM controller.
  867. # Leave the CPU halted.
  868. reset init
  869. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  870. load_image u-boot.bin 0x20000000
  871. # Start running.
  872. resume 0x20000000
  873. @}
  874. @end example
  875. Then once that code is working you will need to make it
  876. boot from NOR flash; a different utility would help.
  877. Alternatively, some developers write to flash using GDB.
  878. (You might use a similar script if you're working with a flash
  879. based microcontroller application instead of a boot loader.)
  880. @example
  881. proc newboot @{ @} @{
  882. # Reset, leaving the CPU halted. The "reset-init" event
  883. # proc gives faster access to the CPU and to NOR flash;
  884. # "reset halt" would be slower.
  885. reset init
  886. # Write standard version of U-Boot into the first two
  887. # sectors of NOR flash ... the standard version should
  888. # do the same lowlevel init as "reset-init".
  889. flash protect 0 0 1 off
  890. flash erase_sector 0 0 1
  891. flash write_bank 0 u-boot.bin 0x0
  892. flash protect 0 0 1 on
  893. # Reboot from scratch using that new boot loader.
  894. reset run
  895. @}
  896. @end example
  897. You may need more complicated utility procedures when booting
  898. from NAND.
  899. That often involves an extra bootloader stage,
  900. running from on-chip SRAM to perform DDR RAM setup so it can load
  901. the main bootloader code (which won't fit into that SRAM).
  902. Other helper scripts might be used to write production system images,
  903. involving considerably more than just a three stage bootloader.
  904. @section Target Software Changes
  905. Sometimes you may want to make some small changes to the software
  906. you're developing, to help make JTAG debugging work better.
  907. For example, in C or assembly language code you might
  908. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  909. handling issues like:
  910. @itemize @bullet
  911. @item @b{Watchdog Timers}...
  912. Watchdog timers are typically used to automatically reset systems if
  913. some application task doesn't periodically reset the timer. (The
  914. assumption is that the system has locked up if the task can't run.)
  915. When a JTAG debugger halts the system, that task won't be able to run
  916. and reset the timer ... potentially causing resets in the middle of
  917. your debug sessions.
  918. It's rarely a good idea to disable such watchdogs, since their usage
  919. needs to be debugged just like all other parts of your firmware.
  920. That might however be your only option.
  921. Look instead for chip-specific ways to stop the watchdog from counting
  922. while the system is in a debug halt state. It may be simplest to set
  923. that non-counting mode in your debugger startup scripts. You may however
  924. need a different approach when, for example, a motor could be physically
  925. damaged by firmware remaining inactive in a debug halt state. That might
  926. involve a type of firmware mode where that "non-counting" mode is disabled
  927. at the beginning then re-enabled at the end; a watchdog reset might fire
  928. and complicate the debug session, but hardware (or people) would be
  929. protected.@footnote{Note that many systems support a "monitor mode" debug
  930. that is a somewhat cleaner way to address such issues. You can think of
  931. it as only halting part of the system, maybe just one task,
  932. instead of the whole thing.
  933. At this writing, January 2010, OpenOCD based debugging does not support
  934. monitor mode debug, only "halt mode" debug.}
  935. @item @b{ARM Semihosting}...
  936. @cindex ARM semihosting
  937. When linked with a special runtime library provided with many
  938. toolchains@footnote{See chapter 8 "Semihosting" in
  939. @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
  940. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  941. The CodeSourcery EABI toolchain also includes a semihosting library.},
  942. your target code can use I/O facilities on the debug host. That library
  943. provides a small set of system calls which are handled by OpenOCD.
  944. It can let the debugger provide your system console and a file system,
  945. helping with early debugging or providing a more capable environment
  946. for sometimes-complex tasks like installing system firmware onto
  947. NAND or SPI flash.
  948. @item @b{ARM Wait-For-Interrupt}...
  949. Many ARM chips synchronize the JTAG clock using the core clock.
  950. Low power states which stop that core clock thus prevent JTAG access.
  951. Idle loops in tasking environments often enter those low power states
  952. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  953. You may want to @emph{disable that instruction} in source code,
  954. or otherwise prevent using that state,
  955. to ensure you can get JTAG access at any time.@footnote{As a more
  956. polite alternative, some processors have special debug-oriented
  957. registers which can be used to change various features including
  958. how the low power states are clocked while debugging.
  959. The STM32 DBGMCU_CR register is an example; at the cost of extra
  960. power consumption, JTAG can be used during low power states.}
  961. For example, the OpenOCD @command{halt} command may not
  962. work for an idle processor otherwise.
  963. @item @b{Delay after reset}...
  964. Not all chips have good support for debugger access
  965. right after reset; many LPC2xxx chips have issues here.
  966. Similarly, applications that reconfigure pins used for
  967. JTAG access as they start will also block debugger access.
  968. To work with boards like this, @emph{enable a short delay loop}
  969. the first thing after reset, before "real" startup activities.
  970. For example, one second's delay is usually more than enough
  971. time for a JTAG debugger to attach, so that
  972. early code execution can be debugged
  973. or firmware can be replaced.
  974. @item @b{Debug Communications Channel (DCC)}...
  975. Some processors include mechanisms to send messages over JTAG.
  976. Many ARM cores support these, as do some cores from other vendors.
  977. (OpenOCD may be able to use this DCC internally, speeding up some
  978. operations like writing to memory.)
  979. Your application may want to deliver various debugging messages
  980. over JTAG, by @emph{linking with a small library of code}
  981. provided with OpenOCD and using the utilities there to send
  982. various kinds of message.
  983. @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
  984. @end itemize
  985. @section Target Hardware Setup
  986. Chip vendors often provide software development boards which
  987. are highly configurable, so that they can support all options
  988. that product boards may require. @emph{Make sure that any
  989. jumpers or switches match the system configuration you are
  990. working with.}
  991. Common issues include:
  992. @itemize @bullet
  993. @item @b{JTAG setup} ...
  994. Boards may support more than one JTAG configuration.
  995. Examples include jumpers controlling pullups versus pulldowns
  996. on the nTRST and/or nSRST signals, and choice of connectors
  997. (e.g. which of two headers on the base board,
  998. or one from a daughtercard).
  999. For some Texas Instruments boards, you may need to jumper the
  1000. EMU0 and EMU1 signals (which OpenOCD won't currently control).
  1001. @item @b{Boot Modes} ...
  1002. Complex chips often support multiple boot modes, controlled
  1003. by external jumpers. Make sure this is set up correctly.
  1004. For example many i.MX boards from NXP need to be jumpered
  1005. to "ATX mode" to start booting using the on-chip ROM, when
  1006. using second stage bootloader code stored in a NAND flash chip.
  1007. Such explicit configuration is common, and not limited to
  1008. booting from NAND. You might also need to set jumpers to
  1009. start booting using code loaded from an MMC/SD card; external
  1010. SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
  1011. flash; some external host; or various other sources.
  1012. @item @b{Memory Addressing} ...
  1013. Boards which support multiple boot modes may also have jumpers
  1014. to configure memory addressing. One board, for example, jumpers
  1015. external chipselect 0 (used for booting) to address either
  1016. a large SRAM (which must be pre-loaded via JTAG), NOR flash,
  1017. or NAND flash. When it's jumpered to address NAND flash, that
  1018. board must also be told to start booting from on-chip ROM.
  1019. Your @file{board.cfg} file may also need to be told this jumper
  1020. configuration, so that it can know whether to declare NOR flash
  1021. using @command{flash bank} or instead declare NAND flash with
  1022. @command{nand device}; and likewise which probe to perform in
  1023. its @code{reset-init} handler.
  1024. A closely related issue is bus width. Jumpers might need to
  1025. distinguish between 8 bit or 16 bit bus access for the flash
  1026. used to start booting.
  1027. @item @b{Peripheral Access} ...
  1028. Development boards generally provide access to every peripheral
  1029. on the chip, sometimes in multiple modes (such as by providing
  1030. multiple audio codec chips).
  1031. This interacts with software
  1032. configuration of pin multiplexing, where for example a
  1033. given pin may be routed either to the MMC/SD controller
  1034. or the GPIO controller. It also often interacts with
  1035. configuration jumpers. One jumper may be used to route
  1036. signals to an MMC/SD card slot or an expansion bus (which
  1037. might in turn affect booting); others might control which
  1038. audio or video codecs are used.
  1039. @end itemize
  1040. Plus you should of course have @code{reset-init} event handlers
  1041. which set up the hardware to match that jumper configuration.
  1042. That includes in particular any oscillator or PLL used to clock
  1043. the CPU, and any memory controllers needed to access external
  1044. memory and peripherals. Without such handlers, you won't be
  1045. able to access those resources without working target firmware
  1046. which can do that setup ... this can be awkward when you're
  1047. trying to debug that target firmware. Even if there's a ROM
  1048. bootloader which handles a few issues, it rarely provides full
  1049. access to all board-specific capabilities.
  1050. @node Config File Guidelines
  1051. @chapter Config File Guidelines
  1052. This chapter is aimed at any user who needs to write a config file,
  1053. including developers and integrators of OpenOCD and any user who
  1054. needs to get a new board working smoothly.
  1055. It provides guidelines for creating those files.
  1056. You should find the following directories under
  1057. @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
  1058. them as-is where you can; or as models for new files.
  1059. @itemize @bullet
  1060. @item @file{interface} ...
  1061. These are for debug adapters. Files that specify configuration to use
  1062. specific JTAG, SWD and other adapters go here.
  1063. @item @file{board} ...
  1064. Think Circuit Board, PWA, PCB, they go by many names. Board files
  1065. contain initialization items that are specific to a board.
  1066. They reuse target configuration files, since the same
  1067. microprocessor chips are used on many boards,
  1068. but support for external parts varies widely. For
  1069. example, the SDRAM initialization sequence for the board, or the type
  1070. of external flash and what address it uses. Any initialization
  1071. sequence to enable that external flash or SDRAM should be found in the
  1072. board file. Boards may also contain multiple targets: two CPUs; or
  1073. a CPU and an FPGA.
  1074. @item @file{target} ...
  1075. Think chip. The ``target'' directory represents the JTAG TAPs
  1076. on a chip
  1077. which OpenOCD should control, not a board. Two common types of targets
  1078. are ARM chips and FPGA or CPLD chips.
  1079. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  1080. the target config file defines all of them.
  1081. @item @emph{more} ... browse for other library files which may be useful.
  1082. For example, there are various generic and CPU-specific utilities.
  1083. @end itemize
  1084. The @file{openocd.cfg} user config
  1085. file may override features in any of the above files by
  1086. setting variables before sourcing the target file, or by adding
  1087. commands specific to their situation.
  1088. @section Interface Config Files
  1089. The user config file
  1090. should be able to source one of these files with a command like this:
  1091. @example
  1092. source [find interface/FOOBAR.cfg]
  1093. @end example
  1094. A preconfigured interface file should exist for every debug adapter
  1095. in use today with OpenOCD.
  1096. That said, perhaps some of these config files
  1097. have only been used by the developer who created it.
  1098. A separate chapter gives information about how to set these up.
  1099. @xref{Debug Adapter Configuration}.
  1100. Read the OpenOCD source code (and Developer's Guide)
  1101. if you have a new kind of hardware interface
  1102. and need to provide a driver for it.
  1103. @section Board Config Files
  1104. @cindex config file, board
  1105. @cindex board config file
  1106. The user config file
  1107. should be able to source one of these files with a command like this:
  1108. @example
  1109. source [find board/FOOBAR.cfg]
  1110. @end example
  1111. The point of a board config file is to package everything
  1112. about a given board that user config files need to know.
  1113. In summary the board files should contain (if present)
  1114. @enumerate
  1115. @item One or more @command{source [find target/...cfg]} statements
  1116. @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
  1117. @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
  1118. @item Target @code{reset} handlers for SDRAM and I/O configuration
  1119. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  1120. @item All things that are not ``inside a chip''
  1121. @end enumerate
  1122. Generic things inside target chips belong in target config files,
  1123. not board config files. So for example a @code{reset-init} event
  1124. handler should know board-specific oscillator and PLL parameters,
  1125. which it passes to target-specific utility code.
  1126. The most complex task of a board config file is creating such a
  1127. @code{reset-init} event handler.
  1128. Define those handlers last, after you verify the rest of the board
  1129. configuration works.
  1130. @subsection Communication Between Config files
  1131. In addition to target-specific utility code, another way that
  1132. board and target config files communicate is by following a
  1133. convention on how to use certain variables.
  1134. The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
  1135. Thus the rule we follow in OpenOCD is this: Variables that begin with
  1136. a leading underscore are temporary in nature, and can be modified and
  1137. used at will within a target configuration file.
  1138. Complex board config files can do the things like this,
  1139. for a board with three chips:
  1140. @example
  1141. # Chip #1: PXA270 for network side, big endian
  1142. set CHIPNAME network
  1143. set ENDIAN big
  1144. source [find target/pxa270.cfg]
  1145. # on return: _TARGETNAME = network.cpu
  1146. # other commands can refer to the "network.cpu" target.
  1147. $_TARGETNAME configure .... events for this CPU..
  1148. # Chip #2: PXA270 for video side, little endian
  1149. set CHIPNAME video
  1150. set ENDIAN little
  1151. source [find target/pxa270.cfg]
  1152. # on return: _TARGETNAME = video.cpu
  1153. # other commands can refer to the "video.cpu" target.
  1154. $_TARGETNAME configure .... events for this CPU..
  1155. # Chip #3: Xilinx FPGA for glue logic
  1156. set CHIPNAME xilinx
  1157. unset ENDIAN
  1158. source [find target/spartan3.cfg]
  1159. @end example
  1160. That example is oversimplified because it doesn't show any flash memory,
  1161. or the @code{reset-init} event handlers to initialize external DRAM
  1162. or (assuming it needs it) load a configuration into the FPGA.
  1163. Such features are usually needed for low-level work with many boards,
  1164. where ``low level'' implies that the board initialization software may
  1165. not be working. (That's a common reason to need JTAG tools. Another
  1166. is to enable working with microcontroller-based systems, which often
  1167. have no debugging support except a JTAG connector.)
  1168. Target config files may also export utility functions to board and user
  1169. config files. Such functions should use name prefixes, to help avoid
  1170. naming collisions.
  1171. Board files could also accept input variables from user config files.
  1172. For example, there might be a @code{J4_JUMPER} setting used to identify
  1173. what kind of flash memory a development board is using, or how to set
  1174. up other clocks and peripherals.
  1175. @subsection Variable Naming Convention
  1176. @cindex variable names
  1177. Most boards have only one instance of a chip.
  1178. However, it should be easy to create a board with more than
  1179. one such chip (as shown above).
  1180. Accordingly, we encourage these conventions for naming
  1181. variables associated with different @file{target.cfg} files,
  1182. to promote consistency and
  1183. so that board files can override target defaults.
  1184. Inputs to target config files include:
  1185. @itemize @bullet
  1186. @item @code{CHIPNAME} ...
  1187. This gives a name to the overall chip, and is used as part of
  1188. tap identifier dotted names.
  1189. While the default is normally provided by the chip manufacturer,
  1190. board files may need to distinguish between instances of a chip.
  1191. @item @code{ENDIAN} ...
  1192. By default @option{little} - although chips may hard-wire @option{big}.
  1193. Chips that can't change endianess don't need to use this variable.
  1194. @item @code{CPUTAPID} ...
  1195. When OpenOCD examines the JTAG chain, it can be told verify the
  1196. chips against the JTAG IDCODE register.
  1197. The target file will hold one or more defaults, but sometimes the
  1198. chip in a board will use a different ID (perhaps a newer revision).
  1199. @end itemize
  1200. Outputs from target config files include:
  1201. @itemize @bullet
  1202. @item @code{_TARGETNAME} ...
  1203. By convention, this variable is created by the target configuration
  1204. script. The board configuration file may make use of this variable to
  1205. configure things like a ``reset init'' script, or other things
  1206. specific to that board and that target.
  1207. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  1208. @code{_TARGETNAME1}, ... etc.
  1209. @end itemize
  1210. @subsection The reset-init Event Handler
  1211. @cindex event, reset-init
  1212. @cindex reset-init handler
  1213. Board config files run in the OpenOCD configuration stage;
  1214. they can't use TAPs or targets, since they haven't been
  1215. fully set up yet.
  1216. This means you can't write memory or access chip registers;
  1217. you can't even verify that a flash chip is present.
  1218. That's done later in event handlers, of which the target @code{reset-init}
  1219. handler is one of the most important.
  1220. Except on microcontrollers, the basic job of @code{reset-init} event
  1221. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1222. Microcontrollers rarely use boot loaders; they run right out of their
  1223. on-chip flash and SRAM memory. But they may want to use one of these
  1224. handlers too, if just for developer convenience.
  1225. @quotation Note
  1226. Because this is so very board-specific, and chip-specific, no examples
  1227. are included here.
  1228. Instead, look at the board config files distributed with OpenOCD.
  1229. If you have a boot loader, its source code will help; so will
  1230. configuration files for other JTAG tools
  1231. (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
  1232. @end quotation
  1233. Some of this code could probably be shared between different boards.
  1234. For example, setting up a DRAM controller often doesn't differ by
  1235. much except the bus width (16 bits or 32?) and memory timings, so a
  1236. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1237. those as parameters.
  1238. Similarly with oscillator, PLL, and clock setup;
  1239. and disabling the watchdog.
  1240. Structure the code cleanly, and provide comments to help
  1241. the next developer doing such work.
  1242. (@emph{You might be that next person} trying to reuse init code!)
  1243. The last thing normally done in a @code{reset-init} handler is probing
  1244. whatever flash memory was configured. For most chips that needs to be
  1245. done while the associated target is halted, either because JTAG memory
  1246. access uses the CPU or to prevent conflicting CPU access.
  1247. @subsection JTAG Clock Rate
  1248. Before your @code{reset-init} handler has set up
  1249. the PLLs and clocking, you may need to run with
  1250. a low JTAG clock rate.
  1251. @xref{jtagspeed,,JTAG Speed}.
  1252. Then you'd increase that rate after your handler has
  1253. made it possible to use the faster JTAG clock.
  1254. When the initial low speed is board-specific, for example
  1255. because it depends on a board-specific oscillator speed, then
  1256. you should probably set it up in the board config file;
  1257. if it's target-specific, it belongs in the target config file.
  1258. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1259. @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
  1260. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1261. Consult chip documentation to determine the peak JTAG clock rate,
  1262. which might be less than that.
  1263. @quotation Warning
  1264. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1265. software using a @option{wait for interrupt} operation blocks JTAG access.
  1266. Adaptive clocking provides a partial workaround, but a more complete
  1267. solution just avoids using that instruction with JTAG debuggers.
  1268. @end quotation
  1269. If both the chip and the board support adaptive clocking,
  1270. use the @command{jtag_rclk}
  1271. command, in case your board is used with JTAG adapter which
  1272. also supports it. Otherwise use @command{adapter_khz}.
  1273. Set the slow rate at the beginning of the reset sequence,
  1274. and the faster rate as soon as the clocks are at full speed.
  1275. @anchor{theinitboardprocedure}
  1276. @subsection The init_board procedure
  1277. @cindex init_board procedure
  1278. The concept of @code{init_board} procedure is very similar to @code{init_targets}
  1279. (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
  1280. configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
  1281. (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
  1282. separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
  1283. everything target specific (internal flash, internal RAM, etc.) and the second one to configure
  1284. everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
  1285. Additionally ``linear'' board config file will most likely fail when target config file uses
  1286. @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
  1287. so separating these two configuration stages is very convenient, as the easiest way to overcome this
  1288. problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
  1289. need to override @code{init_targets} defined in target config files when they only need to add some specifics.
  1290. Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
  1291. the original), allowing greater code reuse.
  1292. @example
  1293. ### board_file.cfg ###
  1294. # source target file that does most of the config in init_targets
  1295. source [find target/target.cfg]
  1296. proc enable_fast_clock @{@} @{
  1297. # enables fast on-board clock source
  1298. # configures the chip to use it
  1299. @}
  1300. # initialize only board specifics - reset, clock, adapter frequency
  1301. proc init_board @{@} @{
  1302. reset_config trst_and_srst trst_pulls_srst
  1303. $_TARGETNAME configure -event reset-start @{
  1304. adapter_khz 100
  1305. @}
  1306. $_TARGETNAME configure -event reset-init @{
  1307. enable_fast_clock
  1308. adapter_khz 10000
  1309. @}
  1310. @}
  1311. @end example
  1312. @section Target Config Files
  1313. @cindex config file, target
  1314. @cindex target config file
  1315. Board config files communicate with target config files using
  1316. naming conventions as described above, and may source one or
  1317. more target config files like this:
  1318. @example
  1319. source [find target/FOOBAR.cfg]
  1320. @end example
  1321. The point of a target config file is to package everything
  1322. about a given chip that board config files need to know.
  1323. In summary the target files should contain
  1324. @enumerate
  1325. @item Set defaults
  1326. @item Add TAPs to the scan chain
  1327. @item Add CPU targets (includes GDB support)
  1328. @item CPU/Chip/CPU-Core specific features
  1329. @item On-Chip flash
  1330. @end enumerate
  1331. As a rule of thumb, a target file sets up only one chip.
  1332. For a microcontroller, that will often include a single TAP,
  1333. which is a CPU needing a GDB target, and its on-chip flash.
  1334. More complex chips may include multiple TAPs, and the target
  1335. config file may need to define them all before OpenOCD
  1336. can talk to the chip.
  1337. For example, some phone chips have JTAG scan chains that include
  1338. an ARM core for operating system use, a DSP,
  1339. another ARM core embedded in an image processing engine,
  1340. and other processing engines.
  1341. @subsection Default Value Boiler Plate Code
  1342. All target configuration files should start with code like this,
  1343. letting board config files express environment-specific
  1344. differences in how things should be set up.
  1345. @example
  1346. # Boards may override chip names, perhaps based on role,
  1347. # but the default should match what the vendor uses
  1348. if @{ [info exists CHIPNAME] @} @{
  1349. set _CHIPNAME $CHIPNAME
  1350. @} else @{
  1351. set _CHIPNAME sam7x256
  1352. @}
  1353. # ONLY use ENDIAN with targets that can change it.
  1354. if @{ [info exists ENDIAN] @} @{
  1355. set _ENDIAN $ENDIAN
  1356. @} else @{
  1357. set _ENDIAN little
  1358. @}
  1359. # TAP identifiers may change as chips mature, for example with
  1360. # new revision fields (the "3" here). Pick a good default; you
  1361. # can pass several such identifiers to the "jtag newtap" command.
  1362. if @{ [info exists CPUTAPID ] @} @{
  1363. set _CPUTAPID $CPUTAPID
  1364. @} else @{
  1365. set _CPUTAPID 0x3f0f0f0f
  1366. @}
  1367. @end example
  1368. @c but 0x3f0f0f0f is for an str73x part ...
  1369. @emph{Remember:} Board config files may include multiple target
  1370. config files, or the same target file multiple times
  1371. (changing at least @code{CHIPNAME}).
  1372. Likewise, the target configuration file should define
  1373. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1374. use it later on when defining debug targets:
  1375. @example
  1376. set _TARGETNAME $_CHIPNAME.cpu
  1377. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1378. @end example
  1379. @subsection Adding TAPs to the Scan Chain
  1380. After the ``defaults'' are set up,
  1381. add the TAPs on each chip to the JTAG scan chain.
  1382. @xref{TAP Declaration}, and the naming convention
  1383. for taps.
  1384. In the simplest case the chip has only one TAP,
  1385. probably for a CPU or FPGA.
  1386. The config file for the Atmel AT91SAM7X256
  1387. looks (in part) like this:
  1388. @example
  1389. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1390. @end example
  1391. A board with two such at91sam7 chips would be able
  1392. to source such a config file twice, with different
  1393. values for @code{CHIPNAME}, so
  1394. it adds a different TAP each time.
  1395. If there are nonzero @option{-expected-id} values,
  1396. OpenOCD attempts to verify the actual tap id against those values.
  1397. It will issue error messages if there is mismatch, which
  1398. can help to pinpoint problems in OpenOCD configurations.
  1399. @example
  1400. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1401. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1402. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1403. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1404. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1405. @end example
  1406. There are more complex examples too, with chips that have
  1407. multiple TAPs. Ones worth looking at include:
  1408. @itemize
  1409. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1410. plus a JRC to enable them
  1411. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1412. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1413. is not currently used)
  1414. @end itemize
  1415. @subsection Add CPU targets
  1416. After adding a TAP for a CPU, you should set it up so that
  1417. GDB and other commands can use it.
  1418. @xref{CPU Configuration}.
  1419. For the at91sam7 example above, the command can look like this;
  1420. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1421. to little endian, and this chip doesn't support changing that.
  1422. @example
  1423. set _TARGETNAME $_CHIPNAME.cpu
  1424. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1425. @end example
  1426. Work areas are small RAM areas associated with CPU targets.
  1427. They are used by OpenOCD to speed up downloads,
  1428. and to download small snippets of code to program flash chips.
  1429. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1430. a work area if you can.
  1431. Again using the at91sam7 as an example, this can look like:
  1432. @example
  1433. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1434. -work-area-size 0x4000 -work-area-backup 0
  1435. @end example
  1436. @anchor{definecputargetsworkinginsmp}
  1437. @subsection Define CPU targets working in SMP
  1438. @cindex SMP
  1439. After setting targets, you can define a list of targets working in SMP.
  1440. @example
  1441. set _TARGETNAME_1 $_CHIPNAME.cpu1
  1442. set _TARGETNAME_2 $_CHIPNAME.cpu2
  1443. target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
  1444. -coreid 0 -dbgbase $_DAP_DBG1
  1445. target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
  1446. -coreid 1 -dbgbase $_DAP_DBG2
  1447. #define 2 targets working in smp.
  1448. target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
  1449. @end example
  1450. In the above example on cortex_a, 2 cpus are working in SMP.
  1451. In SMP only one GDB instance is created and :
  1452. @itemize @bullet
  1453. @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
  1454. @item halt command triggers the halt of all targets in the list.
  1455. @item resume command triggers the write context and the restart of all targets in the list.
  1456. @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
  1457. @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
  1458. displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
  1459. @end itemize
  1460. The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
  1461. command have been implemented.
  1462. @itemize @bullet
  1463. @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
  1464. @item cortex_a smp_off : disable SMP mode, the current target is the one
  1465. displayed in the GDB session, only this target is now controlled by GDB
  1466. session. This behaviour is useful during system boot up.
  1467. @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
  1468. following example.
  1469. @end itemize
  1470. @example
  1471. >cortex_a smp_gdb
  1472. gdb coreid 0 -> -1
  1473. #0 : coreid 0 is displayed to GDB ,
  1474. #-> -1 : next resume triggers a real resume
  1475. > cortex_a smp_gdb 1
  1476. gdb coreid 0 -> 1
  1477. #0 :coreid 0 is displayed to GDB ,
  1478. #->1 : next resume displays coreid 1 to GDB
  1479. > resume
  1480. > cortex_a smp_gdb
  1481. gdb coreid 1 -> 1
  1482. #1 :coreid 1 is displayed to GDB ,
  1483. #->1 : next resume displays coreid 1 to GDB
  1484. > cortex_a smp_gdb -1
  1485. gdb coreid 1 -> -1
  1486. #1 :coreid 1 is displayed to GDB,
  1487. #->-1 : next resume triggers a real resume
  1488. @end example
  1489. @subsection Chip Reset Setup
  1490. As a rule, you should put the @command{reset_config} command
  1491. into the board file. Most things you think you know about a
  1492. chip can be tweaked by the board.
  1493. Some chips have specific ways the TRST and SRST signals are
  1494. managed. In the unusual case that these are @emph{chip specific}
  1495. and can never be changed by board wiring, they could go here.
  1496. For example, some chips can't support JTAG debugging without
  1497. both signals.
  1498. Provide a @code{reset-assert} event handler if you can.
  1499. Such a handler uses JTAG operations to reset the target,
  1500. letting this target config be used in systems which don't
  1501. provide the optional SRST signal, or on systems where you
  1502. don't want to reset all targets at once.
  1503. Such a handler might write to chip registers to force a reset,
  1504. use a JRC to do that (preferable -- the target may be wedged!),
  1505. or force a watchdog timer to trigger.
  1506. (For Cortex-M targets, this is not necessary. The target
  1507. driver knows how to use trigger an NVIC reset when SRST is
  1508. not available.)
  1509. Some chips need special attention during reset handling if
  1510. they're going to be used with JTAG.
  1511. An example might be needing to send some commands right
  1512. after the target's TAP has been reset, providing a
  1513. @code{reset-deassert-post} event handler that writes a chip
  1514. register to report that JTAG debugging is being done.
  1515. Another would be reconfiguring the watchdog so that it stops
  1516. counting while the core is halted in the debugger.
  1517. JTAG clocking constraints often change during reset, and in
  1518. some cases target config files (rather than board config files)
  1519. are the right places to handle some of those issues.
  1520. For example, immediately after reset most chips run using a
  1521. slower clock than they will use later.
  1522. That means that after reset (and potentially, as OpenOCD
  1523. first starts up) they must use a slower JTAG clock rate
  1524. than they will use later.
  1525. @xref{jtagspeed,,JTAG Speed}.
  1526. @quotation Important
  1527. When you are debugging code that runs right after chip
  1528. reset, getting these issues right is critical.
  1529. In particular, if you see intermittent failures when
  1530. OpenOCD verifies the scan chain after reset,
  1531. look at how you are setting up JTAG clocking.
  1532. @end quotation
  1533. @anchor{theinittargetsprocedure}
  1534. @subsection The init_targets procedure
  1535. @cindex init_targets procedure
  1536. Target config files can either be ``linear'' (script executed line-by-line when parsed in
  1537. configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
  1538. procedure called @code{init_targets}, which will be executed when entering run stage
  1539. (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
  1540. Such procedure can be overridden by ``next level'' script (which sources the original).
  1541. This concept facilitates code reuse when basic target config files provide generic configuration
  1542. procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
  1543. a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
  1544. because sourcing them executes every initialization commands they provide.
  1545. @example
  1546. ### generic_file.cfg ###
  1547. proc setup_my_chip @{chip_name flash_size ram_size@} @{
  1548. # basic initialization procedure ...
  1549. @}
  1550. proc init_targets @{@} @{
  1551. # initializes generic chip with 4kB of flash and 1kB of RAM
  1552. setup_my_chip MY_GENERIC_CHIP 4096 1024
  1553. @}
  1554. ### specific_file.cfg ###
  1555. source [find target/generic_file.cfg]
  1556. proc init_targets @{@} @{
  1557. # initializes specific chip with 128kB of flash and 64kB of RAM
  1558. setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
  1559. @}
  1560. @end example
  1561. The easiest way to convert ``linear'' config files to @code{init_targets} version is to
  1562. enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
  1563. For an example of this scheme see LPC2000 target config files.
  1564. The @code{init_boards} procedure is a similar concept concerning board config files
  1565. (@xref{theinitboardprocedure,,The init_board procedure}.)
  1566. @anchor{theinittargeteventsprocedure}
  1567. @subsection The init_target_events procedure
  1568. @cindex init_target_events procedure
  1569. A special procedure called @code{init_target_events} is run just after
  1570. @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
  1571. procedure}.) and before @code{init_board}
  1572. (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
  1573. to set up default target events for the targets that do not have those
  1574. events already assigned.
  1575. @subsection ARM Core Specific Hacks
  1576. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1577. special high speed download features - enable it.
  1578. If present, the MMU, the MPU and the CACHE should be disabled.
  1579. Some ARM cores are equipped with trace support, which permits
  1580. examination of the instruction and data bus activity. Trace
  1581. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1582. on one of the core's scan chains. The ETM emits voluminous data
  1583. through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
  1584. If you are using an external trace port,
  1585. configure it in your board config file.
  1586. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1587. configure it in your target config file.
  1588. @example
  1589. etm config $_TARGETNAME 16 normal full etb
  1590. etb config $_TARGETNAME $_CHIPNAME.etb
  1591. @end example
  1592. @subsection Internal Flash Configuration
  1593. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1594. @b{Never ever} in the ``target configuration file'' define any type of
  1595. flash that is external to the chip. (For example a BOOT flash on
  1596. Chip Select 0.) Such flash information goes in a board file - not
  1597. the TARGET (chip) file.
  1598. Examples:
  1599. @itemize @bullet
  1600. @item at91sam7x256 - has 256K flash YES enable it.
  1601. @item str912 - has flash internal YES enable it.
  1602. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1603. @item pxa270 - again - CS0 flash - it goes in the board file.
  1604. @end itemize
  1605. @anchor{translatingconfigurationfiles}
  1606. @section Translating Configuration Files
  1607. @cindex translation
  1608. If you have a configuration file for another hardware debugger
  1609. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1610. Lauterbach, SEGGER, Macraigor, etc.), translating
  1611. it into OpenOCD syntax is often quite straightforward. The most tricky
  1612. part of creating a configuration script is oftentimes the reset init
  1613. sequence where e.g. PLLs, DRAM and the like is set up.
  1614. One trick that you can use when translating is to write small
  1615. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1616. can avoid manual translation errors and make it easier to
  1617. convert other scripts later on.
  1618. Example of transforming quirky arguments to a simple search and
  1619. replace job:
  1620. @example
  1621. # Lauterbach syntax(?)
  1622. #
  1623. # Data.Set c15:0x042f %long 0x40000015
  1624. #
  1625. # OpenOCD syntax when using procedure below.
  1626. #
  1627. # setc15 0x01 0x00050078
  1628. proc setc15 @{regs value@} @{
  1629. global TARGETNAME
  1630. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1631. arm mcr 15 [expr ($regs>>12)&0x7] \
  1632. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1633. [expr ($regs>>8)&0x7] $value
  1634. @}
  1635. @end example
  1636. @node Server Configuration
  1637. @chapter Server Configuration
  1638. @cindex initialization
  1639. The commands here are commonly found in the openocd.cfg file and are
  1640. used to specify what TCP/IP ports are used, and how GDB should be
  1641. supported.
  1642. @anchor{configurationstage}
  1643. @section Configuration Stage
  1644. @cindex configuration stage
  1645. @cindex config command
  1646. When the OpenOCD server process starts up, it enters a
  1647. @emph{configuration stage} which is the only time that
  1648. certain commands, @emph{configuration commands}, may be issued.
  1649. Normally, configuration commands are only available
  1650. inside startup scripts.
  1651. In this manual, the definition of a configuration command is
  1652. presented as a @emph{Config Command}, not as a @emph{Command}
  1653. which may be issued interactively.
  1654. The runtime @command{help} command also highlights configuration
  1655. commands, and those which may be issued at any time.
  1656. Those configuration commands include declaration of TAPs,
  1657. flash banks,
  1658. the interface used for JTAG communication,
  1659. and other basic setup.
  1660. The server must leave the configuration stage before it
  1661. may access or activate TAPs.
  1662. After it leaves this stage, configuration commands may no
  1663. longer be issued.
  1664. @anchor{enteringtherunstage}
  1665. @section Entering the Run Stage
  1666. The first thing OpenOCD does after leaving the configuration
  1667. stage is to verify that it can talk to the scan chain
  1668. (list of TAPs) which has been configured.
  1669. It will warn if it doesn't find TAPs it expects to find,
  1670. or finds TAPs that aren't supposed to be there.
  1671. You should see no errors at this point.
  1672. If you see errors, resolve them by correcting the
  1673. commands you used to configure the server.
  1674. Common errors include using an initial JTAG speed that's too
  1675. fast, and not providing the right IDCODE values for the TAPs
  1676. on the scan chain.
  1677. Once OpenOCD has entered the run stage, a number of commands
  1678. become available.
  1679. A number of these relate to the debug targets you may have declared.
  1680. For example, the @command{mww} command will not be available until
  1681. a target has been successfully instantiated.
  1682. If you want to use those commands, you may need to force
  1683. entry to the run stage.
  1684. @deffn {Config Command} init
  1685. This command terminates the configuration stage and
  1686. enters the run stage. This helps when you need to have
  1687. the startup scripts manage tasks such as resetting the target,
  1688. programming flash, etc. To reset the CPU upon startup, add "init" and
  1689. "reset" at the end of the config script or at the end of the OpenOCD
  1690. command line using the @option{-c} command line switch.
  1691. If this command does not appear in any startup/configuration file
  1692. OpenOCD executes the command for you after processing all
  1693. configuration files and/or command line options.
  1694. @b{NOTE:} This command normally occurs at or near the end of your
  1695. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1696. targets ready. For example: If your openocd.cfg file needs to
  1697. read/write memory on your target, @command{init} must occur before
  1698. the memory read/write commands. This includes @command{nand probe}.
  1699. @end deffn
  1700. @deffn {Overridable Procedure} jtag_init
  1701. This is invoked at server startup to verify that it can talk
  1702. to the scan chain (list of TAPs) which has been configured.
  1703. The default implementation first tries @command{jtag arp_init},
  1704. which uses only a lightweight JTAG reset before examining the
  1705. scan chain.
  1706. If that fails, it tries again, using a harder reset
  1707. from the overridable procedure @command{init_reset}.
  1708. Implementations must have verified the JTAG scan chain before
  1709. they return.
  1710. This is done by calling @command{jtag arp_init}
  1711. (or @command{jtag arp_init-reset}).
  1712. @end deffn
  1713. @anchor{tcpipports}
  1714. @section TCP/IP Ports
  1715. @cindex TCP port
  1716. @cindex server
  1717. @cindex port
  1718. @cindex security
  1719. The OpenOCD server accepts remote commands in several syntaxes.
  1720. Each syntax uses a different TCP/IP port, which you may specify
  1721. only during configuration (before those ports are opened).
  1722. For reasons including security, you may wish to prevent remote
  1723. access using one or more of these ports.
  1724. In such cases, just specify the relevant port number as "disabled".
  1725. If you disable all access through TCP/IP, you will need to
  1726. use the command line @option{-pipe} option.
  1727. @anchor{gdb_port}
  1728. @deffn {Command} gdb_port [number]
  1729. @cindex GDB server
  1730. Normally gdb listens to a TCP/IP port, but GDB can also
  1731. communicate via pipes(stdin/out or named pipes). The name
  1732. "gdb_port" stuck because it covers probably more than 90% of
  1733. the normal use cases.
  1734. No arguments reports GDB port. "pipe" means listen to stdin
  1735. output to stdout, an integer is base port number, "disabled"
  1736. disables the gdb server.
  1737. When using "pipe", also use log_output to redirect the log
  1738. output to a file so as not to flood the stdin/out pipes.
  1739. The -p/--pipe option is deprecated and a warning is printed
  1740. as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
  1741. Any other string is interpreted as named pipe to listen to.
  1742. Output pipe is the same name as input pipe, but with 'o' appended,
  1743. e.g. /var/gdb, /var/gdbo.
  1744. The GDB port for the first target will be the base port, the
  1745. second target will listen on gdb_port + 1, and so on.
  1746. When not specified during the configuration stage,
  1747. the port @var{number} defaults to 3333.
  1748. When @var{number} is not a numeric value, incrementing it to compute
  1749. the next port number does not work. In this case, specify the proper
  1750. @var{number} for each target by using the option @code{-gdb-port} of the
  1751. commands @command{target create} or @command{$target_name configure}.
  1752. @xref{gdbportoverride,,option -gdb-port}.
  1753. Note: when using "gdb_port pipe", increasing the default remote timeout in
  1754. gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
  1755. cause initialization to fail with "Unknown remote qXfer reply: OK".
  1756. @end deffn
  1757. @deffn {Command} tcl_port [number]
  1758. Specify or query the port used for a simplified RPC
  1759. connection that can be used by clients to issue TCL commands and get the
  1760. output from the Tcl engine.
  1761. Intended as a machine interface.
  1762. When not specified during the configuration stage,
  1763. the port @var{number} defaults to 6666.
  1764. When specified as "disabled", this service is not activated.
  1765. @end deffn
  1766. @deffn {Command} telnet_port [number]
  1767. Specify or query the
  1768. port on which to listen for incoming telnet connections.
  1769. This port is intended for interaction with one human through TCL commands.
  1770. When not specified during the configuration stage,
  1771. the port @var{number} defaults to 4444.
  1772. When specified as "disabled", this service is not activated.
  1773. @end deffn
  1774. @anchor{gdbconfiguration}
  1775. @section GDB Configuration
  1776. @cindex GDB
  1777. @cindex GDB configuration
  1778. You can reconfigure some GDB behaviors if needed.
  1779. The ones listed here are static and global.
  1780. @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
  1781. @xref{targetevents,,Target Events}, about configuring target-specific event handling.
  1782. @anchor{gdbbreakpointoverride}
  1783. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1784. Force breakpoint type for gdb @command{break} commands.
  1785. This option supports GDB GUIs which don't
  1786. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1787. GDB behaviour is not sufficient. GDB normally uses hardware
  1788. breakpoints if the memory map has been set up for flash regions.
  1789. @end deffn
  1790. @anchor{gdbflashprogram}
  1791. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1792. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1793. vFlash packet is received.
  1794. The default behaviour is @option{enable}.
  1795. @end deffn
  1796. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1797. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1798. requested. GDB will then know when to set hardware breakpoints, and program flash
  1799. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1800. for flash programming to work.
  1801. Default behaviour is @option{enable}.
  1802. @xref{gdbflashprogram,,gdb_flash_program}.
  1803. @end deffn
  1804. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1805. Specifies whether data aborts cause an error to be reported
  1806. by GDB memory read packets.
  1807. The default behaviour is @option{disable};
  1808. use @option{enable} see these errors reported.
  1809. @end deffn
  1810. @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
  1811. Specifies whether register accesses requested by GDB register read/write
  1812. packets report errors or not.
  1813. The default behaviour is @option{disable};
  1814. use @option{enable} see these errors reported.
  1815. @end deffn
  1816. @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
  1817. Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
  1818. The default behaviour is @option{enable}.
  1819. @end deffn
  1820. @deffn {Command} gdb_save_tdesc
  1821. Saves the target description file to the local file system.
  1822. The file name is @i{target_name}.xml.
  1823. @end deffn
  1824. @anchor{eventpolling}
  1825. @section Event Polling
  1826. Hardware debuggers are parts of asynchronous systems,
  1827. where significant events can happen at any time.
  1828. The OpenOCD server needs to detect some of these events,
  1829. so it can report them to through TCL command line
  1830. or to GDB.
  1831. Examples of such events include:
  1832. @itemize
  1833. @item One of the targets can stop running ... maybe it triggers
  1834. a code breakpoint or data watchpoint, or halts itself.
  1835. @item Messages may be sent over ``debug message'' channels ... many
  1836. targets support such messages sent over JTAG,
  1837. for receipt by the person debugging or tools.
  1838. @item Loss of power ... some adapters can detect these events.
  1839. @item Resets not issued through JTAG ... such reset sources
  1840. can include button presses or other system hardware, sometimes
  1841. including the target itself (perhaps through a watchdog).
  1842. @item Debug instrumentation sometimes supports event triggering
  1843. such as ``trace buffer full'' (so it can quickly be emptied)
  1844. or other signals (to correlate with code behavior).
  1845. @end itemize
  1846. None of those events are signaled through standard JTAG signals.
  1847. However, most conventions for JTAG connectors include voltage
  1848. level and system reset (SRST) signal detection.
  1849. Some connectors also include instrumentation signals, which
  1850. can imply events when those signals are inputs.
  1851. In general, OpenOCD needs to periodically check for those events,
  1852. either by looking at the status of signals on the JTAG connector
  1853. or by sending synchronous ``tell me your status'' JTAG requests
  1854. to the various active targets.
  1855. There is a command to manage and monitor that polling,
  1856. which is normally done in the background.
  1857. @deffn Command poll [@option{on}|@option{off}]
  1858. Poll the current target for its current state.
  1859. (Also, @pxref{targetcurstate,,target curstate}.)
  1860. If that target is in debug mode, architecture
  1861. specific information about the current state is printed.
  1862. An optional parameter
  1863. allows background polling to be enabled and disabled.
  1864. You could use this from the TCL command shell, or
  1865. from GDB using @command{monitor poll} command.
  1866. Leave background polling enabled while you're using GDB.
  1867. @example
  1868. > poll
  1869. background polling: on
  1870. target state: halted
  1871. target halted in ARM state due to debug-request, \
  1872. current mode: Supervisor
  1873. cpsr: 0x800000d3 pc: 0x11081bfc
  1874. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1875. >
  1876. @end example
  1877. @end deffn
  1878. @node Debug Adapter Configuration
  1879. @chapter Debug Adapter Configuration
  1880. @cindex config file, interface
  1881. @cindex interface config file
  1882. Correctly installing OpenOCD includes making your operating system give
  1883. OpenOCD access to debug adapters. Once that has been done, Tcl commands
  1884. are used to select which one is used, and to configure how it is used.
  1885. @quotation Note
  1886. Because OpenOCD started out with a focus purely on JTAG, you may find
  1887. places where it wrongly presumes JTAG is the only transport protocol
  1888. in use. Be aware that recent versions of OpenOCD are removing that
  1889. limitation. JTAG remains more functional than most other transports.
  1890. Other transports do not support boundary scan operations, or may be
  1891. specific to a given chip vendor. Some might be usable only for
  1892. programming flash memory, instead of also for debugging.
  1893. @end quotation
  1894. Debug Adapters/Interfaces/Dongles are normally configured
  1895. through commands in an interface configuration
  1896. file which is sourced by your @file{openocd.cfg} file, or
  1897. through a command line @option{-f interface/....cfg} option.
  1898. @example
  1899. source [find interface/olimex-jtag-tiny.cfg]
  1900. @end example
  1901. These commands tell
  1902. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1903. A few cases are so simple that you only need to say what driver to use:
  1904. @example
  1905. # jlink interface
  1906. interface jlink
  1907. @end example
  1908. Most adapters need a bit more configuration than that.
  1909. @section Interface Configuration
  1910. The interface command tells OpenOCD what type of debug adapter you are
  1911. using. Depending on the type of adapter, you may need to use one or
  1912. more additional commands to further identify or configure the adapter.
  1913. @deffn {Config Command} {interface} name
  1914. Use the interface driver @var{name} to connect to the
  1915. target.
  1916. @end deffn
  1917. @deffn Command {interface_list}
  1918. List the debug adapter drivers that have been built into
  1919. the running copy of OpenOCD.
  1920. @end deffn
  1921. @deffn Command {interface transports} transport_name+
  1922. Specifies the transports supported by this debug adapter.
  1923. The adapter driver builds-in similar knowledge; use this only
  1924. when external configuration (such as jumpering) changes what
  1925. the hardware can support.
  1926. @end deffn
  1927. @deffn Command {adapter_name}
  1928. Returns the name of the debug adapter driver being used.
  1929. @end deffn
  1930. @section Interface Drivers
  1931. Each of the interface drivers listed here must be explicitly
  1932. enabled when OpenOCD is configured, in order to be made
  1933. available at run time.
  1934. @deffn {Interface Driver} {amt_jtagaccel}
  1935. Amontec Chameleon in its JTAG Accelerator configuration,
  1936. connected to a PC's EPP mode parallel port.
  1937. This defines some driver-specific commands:
  1938. @deffn {Config Command} {parport_port} number
  1939. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1940. the number of the @file{/dev/parport} device.
  1941. @end deffn
  1942. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  1943. Displays status of RTCK option.
  1944. Optionally sets that option first.
  1945. @end deffn
  1946. @end deffn
  1947. @deffn {Interface Driver} {arm-jtag-ew}
  1948. Olimex ARM-JTAG-EW USB adapter
  1949. This has one driver-specific command:
  1950. @deffn Command {armjtagew_info}
  1951. Logs some status
  1952. @end deffn
  1953. @end deffn
  1954. @deffn {Interface Driver} {at91rm9200}
  1955. Supports bitbanged JTAG from the local system,
  1956. presuming that system is an Atmel AT91rm9200
  1957. and a specific set of GPIOs is used.
  1958. @c command: at91rm9200_device NAME
  1959. @c chooses among list of bit configs ... only one option
  1960. @end deffn
  1961. @deffn {Interface Driver} {cmsis-dap}
  1962. ARM CMSIS-DAP compliant based adapter.
  1963. @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
  1964. The vendor ID and product ID of the CMSIS-DAP device. If not specified
  1965. the driver will attempt to auto detect the CMSIS-DAP device.
  1966. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1967. @example
  1968. cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
  1969. @end example
  1970. @end deffn
  1971. @deffn {Config Command} {cmsis_dap_serial} [serial]
  1972. Specifies the @var{serial} of the CMSIS-DAP device to use.
  1973. If not specified, serial numbers are not considered.
  1974. @end deffn
  1975. @deffn {Command} {cmsis-dap info}
  1976. Display various device information, like hardware version, firmware version, current bus status.
  1977. @end deffn
  1978. @end deffn
  1979. @deffn {Interface Driver} {dummy}
  1980. A dummy software-only driver for debugging.
  1981. @end deffn
  1982. @deffn {Interface Driver} {ep93xx}
  1983. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1984. @end deffn
  1985. @deffn {Interface Driver} {ftdi}
  1986. This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
  1987. Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
  1988. The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
  1989. bypassing intermediate libraries like libftdi or D2XX.
  1990. Support for new FTDI based adapters can be added completely through
  1991. configuration files, without the need to patch and rebuild OpenOCD.
  1992. The driver uses a signal abstraction to enable Tcl configuration files to
  1993. define outputs for one or several FTDI GPIO. These outputs can then be
  1994. controlled using the @command{ftdi_set_signal} command. Special signal names
  1995. are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
  1996. will be used for their customary purpose. Inputs can be read using the
  1997. @command{ftdi_get_signal} command.
  1998. To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
  1999. SWD protocol is selected. When set, the adapter should route the SWDIO pin to
  2000. the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
  2001. required by the protocol, to tell the adapter to drive the data output onto
  2002. the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
  2003. Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
  2004. be controlled differently. In order to support tristateable signals such as
  2005. nSRST, both a data GPIO and an output-enable GPIO can be specified for each
  2006. signal. The following output buffer configurations are supported:
  2007. @itemize @minus
  2008. @item Push-pull with one FTDI output as (non-)inverted data line
  2009. @item Open drain with one FTDI output as (non-)inverted output-enable
  2010. @item Tristate with one FTDI output as (non-)inverted data line and another
  2011. FTDI output as (non-)inverted output-enable
  2012. @item Unbuffered, using the FTDI GPIO as a tristate output directly by
  2013. switching data and direction as necessary
  2014. @end itemize
  2015. These interfaces have several commands, used to configure the driver
  2016. before initializing the JTAG scan chain:
  2017. @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
  2018. The vendor ID and product ID of the adapter. Up to eight
  2019. [@var{vid}, @var{pid}] pairs may be given, e.g.
  2020. @example
  2021. ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2022. @end example
  2023. @end deffn
  2024. @deffn {Config Command} {ftdi_device_desc} description
  2025. Provides the USB device description (the @emph{iProduct string})
  2026. of the adapter. If not specified, the device description is ignored
  2027. during device selection.
  2028. @end deffn
  2029. @deffn {Config Command} {ftdi_serial} serial-number
  2030. Specifies the @var{serial-number} of the adapter to use,
  2031. in case the vendor provides unique IDs and more than one adapter
  2032. is connected to the host.
  2033. If not specified, serial numbers are not considered.
  2034. (Note that USB serial numbers can be arbitrary Unicode strings,
  2035. and are not restricted to containing only decimal digits.)
  2036. @end deffn
  2037. @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
  2038. Specifies the physical USB port of the adapter to use. The path
  2039. roots at @var{bus} and walks down the physical ports, with each
  2040. @var{port} option specifying a deeper level in the bus topology, the last
  2041. @var{port} denoting where the target adapter is actually plugged.
  2042. The USB bus topology can be queried with the command @emph{lsusb -t}.
  2043. This command is only available if your libusb1 is at least version 1.0.16.
  2044. @end deffn
  2045. @deffn {Config Command} {ftdi_channel} channel
  2046. Selects the channel of the FTDI device to use for MPSSE operations. Most
  2047. adapters use the default, channel 0, but there are exceptions.
  2048. @end deffn
  2049. @deffn {Config Command} {ftdi_layout_init} data direction
  2050. Specifies the initial values of the FTDI GPIO data and direction registers.
  2051. Each value is a 16-bit number corresponding to the concatenation of the high
  2052. and low FTDI GPIO registers. The values should be selected based on the
  2053. schematics of the adapter, such that all signals are set to safe levels with
  2054. minimal impact on the target system. Avoid floating inputs, conflicting outputs
  2055. and initially asserted reset signals.
  2056. @end deffn
  2057. @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
  2058. Creates a signal with the specified @var{name}, controlled by one or more FTDI
  2059. GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
  2060. register bitmasks to tell the driver the connection and type of the output
  2061. buffer driving the respective signal. @var{data_mask} is the bitmask for the
  2062. pin(s) connected to the data input of the output buffer. @option{-ndata} is
  2063. used with inverting data inputs and @option{-data} with non-inverting inputs.
  2064. The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
  2065. not-output-enable) input to the output buffer is connected. The options
  2066. @option{-input} and @option{-ninput} specify the bitmask for pins to be read
  2067. with the method @command{ftdi_get_signal}.
  2068. Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
  2069. simple open-collector transistor driver would be specified with @option{-oe}
  2070. only. In that case the signal can only be set to drive low or to Hi-Z and the
  2071. driver will complain if the signal is set to drive high. Which means that if
  2072. it's a reset signal, @command{reset_config} must be specified as
  2073. @option{srst_open_drain}, not @option{srst_push_pull}.
  2074. A special case is provided when @option{-data} and @option{-oe} is set to the
  2075. same bitmask. Then the FTDI pin is considered being connected straight to the
  2076. target without any buffer. The FTDI pin is then switched between output and
  2077. input as necessary to provide the full set of low, high and Hi-Z
  2078. characteristics. In all other cases, the pins specified in a signal definition
  2079. are always driven by the FTDI.
  2080. If @option{-alias} or @option{-nalias} is used, the signal is created
  2081. identical (or with data inverted) to an already specified signal
  2082. @var{name}.
  2083. @end deffn
  2084. @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
  2085. Set a previously defined signal to the specified level.
  2086. @itemize @minus
  2087. @item @option{0}, drive low
  2088. @item @option{1}, drive high
  2089. @item @option{z}, set to high-impedance
  2090. @end itemize
  2091. @end deffn
  2092. @deffn {Command} {ftdi_get_signal} name
  2093. Get the value of a previously defined signal.
  2094. @end deffn
  2095. @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
  2096. Configure TCK edge at which the adapter samples the value of the TDO signal
  2097. Due to signal propagation delays, sampling TDO on rising TCK can become quite
  2098. peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
  2099. TDO on falling edge of TCK. With some board/adapter configurations, this may increase
  2100. stability at higher JTAG clocks.
  2101. @itemize @minus
  2102. @item @option{rising}, sample TDO on rising edge of TCK - this is the default
  2103. @item @option{falling}, sample TDO on falling edge of TCK
  2104. @end itemize
  2105. @end deffn
  2106. For example adapter definitions, see the configuration files shipped in the
  2107. @file{interface/ftdi} directory.
  2108. @end deffn
  2109. @deffn {Interface Driver} {ft232r}
  2110. This driver is implementing synchronous bitbang mode of an FTDI FT232R,
  2111. FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
  2112. It currently doesn't support using CBUS pins as GPIO.
  2113. List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
  2114. @itemize @minus
  2115. @item RXD(5) - TDI
  2116. @item TXD(1) - TCK
  2117. @item RTS(3) - TDO
  2118. @item CTS(11) - TMS
  2119. @item DTR(2) - TRST
  2120. @item DCD(10) - SRST
  2121. @end itemize
  2122. User can change default pinout by supplying configuration
  2123. commands with GPIO numbers or RS232 signal names.
  2124. GPIO numbers correspond to bit numbers in FTDI GPIO register.
  2125. They differ from physical pin numbers.
  2126. For details see actual FTDI chip datasheets.
  2127. Every JTAG line must be configured to unique GPIO number
  2128. different than any other JTAG line, even those lines
  2129. that are sometimes not used like TRST or SRST.
  2130. FT232R
  2131. @itemize @minus
  2132. @item bit 7 - RI
  2133. @item bit 6 - DCD
  2134. @item bit 5 - DSR
  2135. @item bit 4 - DTR
  2136. @item bit 3 - CTS
  2137. @item bit 2 - RTS
  2138. @item bit 1 - RXD
  2139. @item bit 0 - TXD
  2140. @end itemize
  2141. These interfaces have several commands, used to configure the driver
  2142. before initializing the JTAG scan chain:
  2143. @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
  2144. The vendor ID and product ID of the adapter. If not specified, default
  2145. 0x0403:0x6001 is used.
  2146. @end deffn
  2147. @deffn {Config Command} {ft232r_serial_desc} @var{serial}
  2148. Specifies the @var{serial} of the adapter to use, in case the
  2149. vendor provides unique IDs and more than one adapter is connected to
  2150. the host. If not specified, serial numbers are not considered.
  2151. @end deffn
  2152. @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
  2153. Set four JTAG GPIO numbers at once.
  2154. If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
  2155. @end deffn
  2156. @deffn {Config Command} {ft232r_tck_num} @var{tck}
  2157. Set TCK GPIO number. If not specified, default 0 or TXD is used.
  2158. @end deffn
  2159. @deffn {Config Command} {ft232r_tms_num} @var{tms}
  2160. Set TMS GPIO number. If not specified, default 3 or CTS is used.
  2161. @end deffn
  2162. @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
  2163. Set TDI GPIO number. If not specified, default 1 or RXD is used.
  2164. @end deffn
  2165. @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
  2166. Set TDO GPIO number. If not specified, default 2 or RTS is used.
  2167. @end deffn
  2168. @deffn {Config Command} {ft232r_trst_num} @var{trst}
  2169. Set TRST GPIO number. If not specified, default 4 or DTR is used.
  2170. @end deffn
  2171. @deffn {Config Command} {ft232r_srst_num} @var{srst}
  2172. Set SRST GPIO number. If not specified, default 6 or DCD is used.
  2173. @end deffn
  2174. @deffn {Config Command} {ft232r_restore_serial} @var{word}
  2175. Restore serial port after JTAG. This USB bitmode control word
  2176. (16-bit) will be sent before quit. Lower byte should
  2177. set GPIO direction register to a "sane" state:
  2178. 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
  2179. byte is usually 0 to disable bitbang mode.
  2180. When kernel driver reattaches, serial port should continue to work.
  2181. Value 0xFFFF disables sending control word and serial port,
  2182. then kernel driver will not reattach.
  2183. If not specified, default 0xFFFF is used.
  2184. @end deffn
  2185. @end deffn
  2186. @deffn {Interface Driver} {remote_bitbang}
  2187. Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
  2188. with a remote process and sends ASCII encoded bitbang requests to that process
  2189. instead of directly driving JTAG.
  2190. The remote_bitbang driver is useful for debugging software running on
  2191. processors which are being simulated.
  2192. @deffn {Config Command} {remote_bitbang_port} number
  2193. Specifies the TCP port of the remote process to connect to or 0 to use UNIX
  2194. sockets instead of TCP.
  2195. @end deffn
  2196. @deffn {Config Command} {remote_bitbang_host} hostname
  2197. Specifies the hostname of the remote process to connect to using TCP, or the
  2198. name of the UNIX socket to use if remote_bitbang_port is 0.
  2199. @end deffn
  2200. For example, to connect remotely via TCP to the host foobar you might have
  2201. something like:
  2202. @example
  2203. interface remote_bitbang
  2204. remote_bitbang_port 3335
  2205. remote_bitbang_host foobar
  2206. @end example
  2207. To connect to another process running locally via UNIX sockets with socket
  2208. named mysocket:
  2209. @example
  2210. interface remote_bitbang
  2211. remote_bitbang_port 0
  2212. remote_bitbang_host mysocket
  2213. @end example
  2214. @end deffn
  2215. @deffn {Interface Driver} {usb_blaster}
  2216. USB JTAG/USB-Blaster compatibles over one of the userspace libraries
  2217. for FTDI chips. These interfaces have several commands, used to
  2218. configure the driver before initializing the JTAG scan chain:
  2219. @deffn {Config Command} {usb_blaster_device_desc} description
  2220. Provides the USB device description (the @emph{iProduct string})
  2221. of the FTDI FT245 device. If not
  2222. specified, the FTDI default value is used. This setting is only valid
  2223. if compiled with FTD2XX support.
  2224. @end deffn
  2225. @deffn {Config Command} {usb_blaster_vid_pid} vid pid
  2226. The vendor ID and product ID of the FTDI FT245 device. If not specified,
  2227. default values are used.
  2228. Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
  2229. Altera USB-Blaster (default):
  2230. @example
  2231. usb_blaster_vid_pid 0x09FB 0x6001
  2232. @end example
  2233. The following VID/PID is for Kolja Waschk's USB JTAG:
  2234. @example
  2235. usb_blaster_vid_pid 0x16C0 0x06AD
  2236. @end example
  2237. @end deffn
  2238. @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
  2239. Sets the state or function of the unused GPIO pins on USB-Blasters
  2240. (pins 6 and 8 on the female JTAG header). These pins can be used as
  2241. SRST and/or TRST provided the appropriate connections are made on the
  2242. target board.
  2243. For example, to use pin 6 as SRST:
  2244. @example
  2245. usb_blaster_pin pin6 s
  2246. reset_config srst_only
  2247. @end example
  2248. @end deffn
  2249. @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
  2250. Chooses the low level access method for the adapter. If not specified,
  2251. @option{ftdi} is selected unless it wasn't enabled during the
  2252. configure stage. USB-Blaster II needs @option{ublast2}.
  2253. @end deffn
  2254. @deffn {Command} {usb_blaster_firmware} @var{path}
  2255. This command specifies @var{path} to access USB-Blaster II firmware
  2256. image. To be used with USB-Blaster II only.
  2257. @end deffn
  2258. @end deffn
  2259. @deffn {Interface Driver} {gw16012}
  2260. Gateworks GW16012 JTAG programmer.
  2261. This has one driver-specific command:
  2262. @deffn {Config Command} {parport_port} [port_number]
  2263. Display either the address of the I/O port
  2264. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2265. If a parameter is provided, first switch to use that port.
  2266. This is a write-once setting.
  2267. @end deffn
  2268. @end deffn
  2269. @deffn {Interface Driver} {jlink}
  2270. SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
  2271. transports.
  2272. @quotation Compatibility Note
  2273. SEGGER released many firmware versions for the many hardware versions they
  2274. produced. OpenOCD was extensively tested and intended to run on all of them,
  2275. but some combinations were reported as incompatible. As a general
  2276. recommendation, it is advisable to use the latest firmware version
  2277. available for each hardware version. However the current V8 is a moving
  2278. target, and SEGGER firmware versions released after the OpenOCD was
  2279. released may not be compatible. In such cases it is recommended to
  2280. revert to the last known functional version. For 0.5.0, this is from
  2281. "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
  2282. version is from "May 3 2012 18:36:22", packed with 4.46f.
  2283. @end quotation
  2284. @deffn {Command} {jlink hwstatus}
  2285. Display various hardware related information, for example target voltage and pin
  2286. states.
  2287. @end deffn
  2288. @deffn {Command} {jlink freemem}
  2289. Display free device internal memory.
  2290. @end deffn
  2291. @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
  2292. Set the JTAG command version to be used. Without argument, show the actual JTAG
  2293. command version.
  2294. @end deffn
  2295. @deffn {Command} {jlink config}
  2296. Display the device configuration.
  2297. @end deffn
  2298. @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
  2299. Set the target power state on JTAG-pin 19. Without argument, show the target
  2300. power state.
  2301. @end deffn
  2302. @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
  2303. Set the MAC address of the device. Without argument, show the MAC address.
  2304. @end deffn
  2305. @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
  2306. Set the IP configuration of the device, where A.B.C.D is the IP address, E the
  2307. bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
  2308. IP configuration.
  2309. @end deffn
  2310. @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
  2311. Set the USB address of the device. This will also change the USB Product ID
  2312. (PID) of the device. Without argument, show the USB address.
  2313. @end deffn
  2314. @deffn {Command} {jlink config reset}
  2315. Reset the current configuration.
  2316. @end deffn
  2317. @deffn {Command} {jlink config write}
  2318. Write the current configuration to the internal persistent storage.
  2319. @end deffn
  2320. @deffn {Command} {jlink emucom write <channel> <data>}
  2321. Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
  2322. pairs.
  2323. The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
  2324. the EMUCOM channel 0x10:
  2325. @example
  2326. > jlink emucom write 0x10 aa0b23
  2327. @end example
  2328. @end deffn
  2329. @deffn {Command} {jlink emucom read <channel> <length>}
  2330. Read data from an EMUCOM channel. The read data is encoded as hexadecimal
  2331. pairs.
  2332. The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
  2333. @example
  2334. > jlink emucom read 0x0 4
  2335. 77a90000
  2336. @end example
  2337. @end deffn
  2338. @deffn {Config} {jlink usb} <@option{0} to @option{3}>
  2339. Set the USB address of the interface, in case more than one adapter is connected
  2340. to the host. If not specified, USB addresses are not considered. Device
  2341. selection via USB address is deprecated and the serial number should be used
  2342. instead.
  2343. As a configuration command, it can be used only before 'init'.
  2344. @end deffn
  2345. @deffn {Config} {jlink serial} <serial number>
  2346. Set the serial number of the interface, in case more than one adapter is
  2347. connected to the host. If not specified, serial numbers are not considered.
  2348. As a configuration command, it can be used only before 'init'.
  2349. @end deffn
  2350. @end deffn
  2351. @deffn {Interface Driver} {kitprog}
  2352. This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
  2353. SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
  2354. families, but it is possible to use it with some other devices. If you are using
  2355. this adapter with a PSoC or a PRoC, you may need to add
  2356. @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
  2357. configuration script.
  2358. Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
  2359. mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
  2360. be used with this driver, and must either be used with the cmsis-dap driver or
  2361. switched back to KitProg mode. See the Cypress KitProg User Guide for
  2362. instructions on how to switch KitProg modes.
  2363. Known limitations:
  2364. @itemize @bullet
  2365. @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
  2366. and 2.7 MHz.
  2367. @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
  2368. "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
  2369. not support sending arbitrary SWD sequences, and only firmware 2.14 and later
  2370. implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
  2371. versions only implement "SWD line reset". Second, due to a firmware quirk, an
  2372. SWD sequence must be sent after every target reset in order to re-establish
  2373. communications with the target.
  2374. @item Due in part to the limitation above, KitProg devices with firmware below
  2375. version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
  2376. communicate with PSoC 5LP devices. This is because, assuming debug is not
  2377. disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
  2378. mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
  2379. could only be sent with an acquisition sequence.
  2380. @end itemize
  2381. @deffn {Config Command} {kitprog_init_acquire_psoc}
  2382. Indicate that a PSoC acquisition sequence needs to be run during adapter init.
  2383. Please be aware that the acquisition sequence hard-resets the target.
  2384. @end deffn
  2385. @deffn {Config Command} {kitprog_serial} serial
  2386. Select a KitProg device by its @var{serial}. If left unspecified, the first
  2387. device detected by OpenOCD will be used.
  2388. @end deffn
  2389. @deffn {Command} {kitprog acquire_psoc}
  2390. Run a PSoC acquisition sequence immediately. Typically, this should not be used
  2391. outside of the target-specific configuration scripts since it hard-resets the
  2392. target as a side-effect.
  2393. This is necessary for "reset halt" on some PSoC 4 series devices.
  2394. @end deffn
  2395. @deffn {Command} {kitprog info}
  2396. Display various adapter information, such as the hardware version, firmware
  2397. version, and target voltage.
  2398. @end deffn
  2399. @end deffn
  2400. @deffn {Interface Driver} {parport}
  2401. Supports PC parallel port bit-banging cables:
  2402. Wigglers, PLD download cable, and more.
  2403. These interfaces have several commands, used to configure the driver
  2404. before initializing the JTAG scan chain:
  2405. @deffn {Config Command} {parport_cable} name
  2406. Set the layout of the parallel port cable used to connect to the target.
  2407. This is a write-once setting.
  2408. Currently valid cable @var{name} values include:
  2409. @itemize @minus
  2410. @item @b{altium} Altium Universal JTAG cable.
  2411. @item @b{arm-jtag} Same as original wiggler except SRST and
  2412. TRST connections reversed and TRST is also inverted.
  2413. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  2414. in configuration mode. This is only used to
  2415. program the Chameleon itself, not a connected target.
  2416. @item @b{dlc5} The Xilinx Parallel cable III.
  2417. @item @b{flashlink} The ST Parallel cable.
  2418. @item @b{lattice} Lattice ispDOWNLOAD Cable
  2419. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  2420. some versions of
  2421. Amontec's Chameleon Programmer. The new version available from
  2422. the website uses the original Wiggler layout ('@var{wiggler}')
  2423. @item @b{triton} The parallel port adapter found on the
  2424. ``Karo Triton 1 Development Board''.
  2425. This is also the layout used by the HollyGates design
  2426. (see @uref{http://www.lartmaker.nl/projects/jtag/}).
  2427. @item @b{wiggler} The original Wiggler layout, also supported by
  2428. several clones, such as the Olimex ARM-JTAG
  2429. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  2430. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  2431. @end itemize
  2432. @end deffn
  2433. @deffn {Config Command} {parport_port} [port_number]
  2434. Display either the address of the I/O port
  2435. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2436. If a parameter is provided, first switch to use that port.
  2437. This is a write-once setting.
  2438. When using PPDEV to access the parallel port, use the number of the parallel port:
  2439. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  2440. you may encounter a problem.
  2441. @end deffn
  2442. @deffn Command {parport_toggling_time} [nanoseconds]
  2443. Displays how many nanoseconds the hardware needs to toggle TCK;
  2444. the parport driver uses this value to obey the
  2445. @command{adapter_khz} configuration.
  2446. When the optional @var{nanoseconds} parameter is given,
  2447. that setting is changed before displaying the current value.
  2448. The default setting should work reasonably well on commodity PC hardware.
  2449. However, you may want to calibrate for your specific hardware.
  2450. @quotation Tip
  2451. To measure the toggling time with a logic analyzer or a digital storage
  2452. oscilloscope, follow the procedure below:
  2453. @example
  2454. > parport_toggling_time 1000
  2455. > adapter_khz 500
  2456. @end example
  2457. This sets the maximum JTAG clock speed of the hardware, but
  2458. the actual speed probably deviates from the requested 500 kHz.
  2459. Now, measure the time between the two closest spaced TCK transitions.
  2460. You can use @command{runtest 1000} or something similar to generate a
  2461. large set of samples.
  2462. Update the setting to match your measurement:
  2463. @example
  2464. > parport_toggling_time <measured nanoseconds>
  2465. @end example
  2466. Now the clock speed will be a better match for @command{adapter_khz rate}
  2467. commands given in OpenOCD scripts and event handlers.
  2468. You can do something similar with many digital multimeters, but note
  2469. that you'll probably need to run the clock continuously for several
  2470. seconds before it decides what clock rate to show. Adjust the
  2471. toggling time up or down until the measured clock rate is a good
  2472. match for the adapter_khz rate you specified; be conservative.
  2473. @end quotation
  2474. @end deffn
  2475. @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
  2476. This will configure the parallel driver to write a known
  2477. cable-specific value to the parallel interface on exiting OpenOCD.
  2478. @end deffn
  2479. For example, the interface configuration file for a
  2480. classic ``Wiggler'' cable on LPT2 might look something like this:
  2481. @example
  2482. interface parport
  2483. parport_port 0x278
  2484. parport_cable wiggler
  2485. @end example
  2486. @end deffn
  2487. @deffn {Interface Driver} {presto}
  2488. ASIX PRESTO USB JTAG programmer.
  2489. @deffn {Config Command} {presto_serial} serial_string
  2490. Configures the USB serial number of the Presto device to use.
  2491. @end deffn
  2492. @end deffn
  2493. @deffn {Interface Driver} {rlink}
  2494. Raisonance RLink USB adapter
  2495. @end deffn
  2496. @deffn {Interface Driver} {usbprog}
  2497. usbprog is a freely programmable USB adapter.
  2498. @end deffn
  2499. @deffn {Interface Driver} {vsllink}
  2500. vsllink is part of Versaloon which is a versatile USB programmer.
  2501. @quotation Note
  2502. This defines quite a few driver-specific commands,
  2503. which are not currently documented here.
  2504. @end quotation
  2505. @end deffn
  2506. @anchor{hla_interface}
  2507. @deffn {Interface Driver} {hla}
  2508. This is a driver that supports multiple High Level Adapters.
  2509. This type of adapter does not expose some of the lower level api's
  2510. that OpenOCD would normally use to access the target.
  2511. Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
  2512. ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
  2513. versions of firmware where serial number is reset after first use. Suggest
  2514. using ST firmware update utility to upgrade ST-LINK firmware even if current
  2515. version reported is V2.J21.S4.
  2516. @deffn {Config Command} {hla_device_desc} description
  2517. Currently Not Supported.
  2518. @end deffn
  2519. @deffn {Config Command} {hla_serial} serial
  2520. Specifies the serial number of the adapter.
  2521. @end deffn
  2522. @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
  2523. Specifies the adapter layout to use.
  2524. @end deffn
  2525. @deffn {Config Command} {hla_vid_pid} [vid pid]+
  2526. Pairs of vendor IDs and product IDs of the device.
  2527. @end deffn
  2528. @deffn {Command} {hla_command} command
  2529. Execute a custom adapter-specific command. The @var{command} string is
  2530. passed as is to the underlying adapter layout handler.
  2531. @end deffn
  2532. @end deffn
  2533. @deffn {Interface Driver} {opendous}
  2534. opendous-jtag is a freely programmable USB adapter.
  2535. @end deffn
  2536. @deffn {Interface Driver} {ulink}
  2537. This is the Keil ULINK v1 JTAG debugger.
  2538. @end deffn
  2539. @deffn {Interface Driver} {ZY1000}
  2540. This is the Zylin ZY1000 JTAG debugger.
  2541. @end deffn
  2542. @quotation Note
  2543. This defines some driver-specific commands,
  2544. which are not currently documented here.
  2545. @end quotation
  2546. @deffn Command power [@option{on}|@option{off}]
  2547. Turn power switch to target on/off.
  2548. No arguments: print status.
  2549. @end deffn
  2550. @deffn {Interface Driver} {bcm2835gpio}
  2551. This SoC is present in Raspberry Pi which is a cheap single-board computer
  2552. exposing some GPIOs on its expansion header.
  2553. The driver accesses memory-mapped GPIO peripheral registers directly
  2554. for maximum performance, but the only possible race condition is for
  2555. the pins' modes/muxing (which is highly unlikely), so it should be
  2556. able to coexist nicely with both sysfs bitbanging and various
  2557. peripherals' kernel drivers. The driver restores the previous
  2558. configuration on exit.
  2559. See @file{interface/raspberrypi-native.cfg} for a sample config and
  2560. pinout.
  2561. @end deffn
  2562. @deffn {Interface Driver} {imx_gpio}
  2563. i.MX SoC is present in many community boards. Wandboard is an example
  2564. of the one which is most popular.
  2565. This driver is mostly the same as bcm2835gpio.
  2566. See @file{interface/imx-native.cfg} for a sample config and
  2567. pinout.
  2568. @end deffn
  2569. @deffn {Interface Driver} {openjtag}
  2570. OpenJTAG compatible USB adapter.
  2571. This defines some driver-specific commands:
  2572. @deffn {Config Command} {openjtag_variant} variant
  2573. Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
  2574. Currently valid @var{variant} values include:
  2575. @itemize @minus
  2576. @item @b{standard} Standard variant (default).
  2577. @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
  2578. (see @uref{http://www.cypress.com/?rID=82870}).
  2579. @end itemize
  2580. @end deffn
  2581. @deffn {Config Command} {openjtag_device_desc} string
  2582. The USB device description string of the adapter.
  2583. This value is only used with the standard variant.
  2584. @end deffn
  2585. @end deffn
  2586. @section Transport Configuration
  2587. @cindex Transport
  2588. As noted earlier, depending on the version of OpenOCD you use,
  2589. and the debug adapter you are using,
  2590. several transports may be available to
  2591. communicate with debug targets (or perhaps to program flash memory).
  2592. @deffn Command {transport list}
  2593. displays the names of the transports supported by this
  2594. version of OpenOCD.
  2595. @end deffn
  2596. @deffn Command {transport select} @option{transport_name}
  2597. Select which of the supported transports to use in this OpenOCD session.
  2598. When invoked with @option{transport_name}, attempts to select the named
  2599. transport. The transport must be supported by the debug adapter
  2600. hardware and by the version of OpenOCD you are using (including the
  2601. adapter's driver).
  2602. If no transport has been selected and no @option{transport_name} is
  2603. provided, @command{transport select} auto-selects the first transport
  2604. supported by the debug adapter.
  2605. @command{transport select} always returns the name of the session's selected
  2606. transport, if any.
  2607. @end deffn
  2608. @subsection JTAG Transport
  2609. @cindex JTAG
  2610. JTAG is the original transport supported by OpenOCD, and most
  2611. of the OpenOCD commands support it.
  2612. JTAG transports expose a chain of one or more Test Access Points (TAPs),
  2613. each of which must be explicitly declared.
  2614. JTAG supports both debugging and boundary scan testing.
  2615. Flash programming support is built on top of debug support.
  2616. JTAG transport is selected with the command @command{transport select
  2617. jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
  2618. driver}, in which case the command is @command{transport select
  2619. hla_jtag}.
  2620. @subsection SWD Transport
  2621. @cindex SWD
  2622. @cindex Serial Wire Debug
  2623. SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
  2624. Debug Access Point (DAP, which must be explicitly declared.
  2625. (SWD uses fewer signal wires than JTAG.)
  2626. SWD is debug-oriented, and does not support boundary scan testing.
  2627. Flash programming support is built on top of debug support.
  2628. (Some processors support both JTAG and SWD.)
  2629. SWD transport is selected with the command @command{transport select
  2630. swd}. Unless your adapter uses @ref{hla_interface,the hla interface
  2631. driver}, in which case the command is @command{transport select
  2632. hla_swd}.
  2633. @deffn Command {swd newdap} ...
  2634. Declares a single DAP which uses SWD transport.
  2635. Parameters are currently the same as "jtag newtap" but this is
  2636. expected to change.
  2637. @end deffn
  2638. @deffn Command {swd wcr trn prescale}
  2639. Updates TRN (turnaround delay) and prescaling.fields of the
  2640. Wire Control Register (WCR).
  2641. No parameters: displays current settings.
  2642. @end deffn
  2643. @subsection SPI Transport
  2644. @cindex SPI
  2645. @cindex Serial Peripheral Interface
  2646. The Serial Peripheral Interface (SPI) is a general purpose transport
  2647. which uses four wire signaling. Some processors use it as part of a
  2648. solution for flash programming.
  2649. @anchor{jtagspeed}
  2650. @section JTAG Speed
  2651. JTAG clock setup is part of system setup.
  2652. It @emph{does not belong with interface setup} since any interface
  2653. only knows a few of the constraints for the JTAG clock speed.
  2654. Sometimes the JTAG speed is
  2655. changed during the target initialization process: (1) slow at
  2656. reset, (2) program the CPU clocks, (3) run fast.
  2657. Both the "slow" and "fast" clock rates are functions of the
  2658. oscillators used, the chip, the board design, and sometimes
  2659. power management software that may be active.
  2660. The speed used during reset, and the scan chain verification which
  2661. follows reset, can be adjusted using a @code{reset-start}
  2662. target event handler.
  2663. It can then be reconfigured to a faster speed by a
  2664. @code{reset-init} target event handler after it reprograms those
  2665. CPU clocks, or manually (if something else, such as a boot loader,
  2666. sets up those clocks).
  2667. @xref{targetevents,,Target Events}.
  2668. When the initial low JTAG speed is a chip characteristic, perhaps
  2669. because of a required oscillator speed, provide such a handler
  2670. in the target config file.
  2671. When that speed is a function of a board-specific characteristic
  2672. such as which speed oscillator is used, it belongs in the board
  2673. config file instead.
  2674. In both cases it's safest to also set the initial JTAG clock rate
  2675. to that same slow speed, so that OpenOCD never starts up using a
  2676. clock speed that's faster than the scan chain can support.
  2677. @example
  2678. jtag_rclk 3000
  2679. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  2680. @end example
  2681. If your system supports adaptive clocking (RTCK), configuring
  2682. JTAG to use that is probably the most robust approach.
  2683. However, it introduces delays to synchronize clocks; so it
  2684. may not be the fastest solution.
  2685. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  2686. instead of @command{adapter_khz}, but only for (ARM) cores and boards
  2687. which support adaptive clocking.
  2688. @deffn {Command} adapter_khz max_speed_kHz
  2689. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  2690. JTAG interfaces usually support a limited number of
  2691. speeds. The speed actually used won't be faster
  2692. than the speed specified.
  2693. Chip data sheets generally include a top JTAG clock rate.
  2694. The actual rate is often a function of a CPU core clock,
  2695. and is normally less than that peak rate.
  2696. For example, most ARM cores accept at most one sixth of the CPU clock.
  2697. Speed 0 (khz) selects RTCK method.
  2698. @xref{faqrtck,,FAQ RTCK}.
  2699. If your system uses RTCK, you won't need to change the
  2700. JTAG clocking after setup.
  2701. Not all interfaces, boards, or targets support ``rtck''.
  2702. If the interface device can not
  2703. support it, an error is returned when you try to use RTCK.
  2704. @end deffn
  2705. @defun jtag_rclk fallback_speed_kHz
  2706. @cindex adaptive clocking
  2707. @cindex RTCK
  2708. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  2709. If that fails (maybe the interface, board, or target doesn't
  2710. support it), falls back to the specified frequency.
  2711. @example
  2712. # Fall back to 3mhz if RTCK is not supported
  2713. jtag_rclk 3000
  2714. @end example
  2715. @end defun
  2716. @node Reset Configuration
  2717. @chapter Reset Configuration
  2718. @cindex Reset Configuration
  2719. Every system configuration may require a different reset
  2720. configuration. This can also be quite confusing.
  2721. Resets also interact with @var{reset-init} event handlers,
  2722. which do things like setting up clocks and DRAM, and
  2723. JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
  2724. They can also interact with JTAG routers.
  2725. Please see the various board files for examples.
  2726. @quotation Note
  2727. To maintainers and integrators:
  2728. Reset configuration touches several things at once.
  2729. Normally the board configuration file
  2730. should define it and assume that the JTAG adapter supports
  2731. everything that's wired up to the board's JTAG connector.
  2732. However, the target configuration file could also make note
  2733. of something the silicon vendor has done inside the chip,
  2734. which will be true for most (or all) boards using that chip.
  2735. And when the JTAG adapter doesn't support everything, the
  2736. user configuration file will need to override parts of
  2737. the reset configuration provided by other files.
  2738. @end quotation
  2739. @section Types of Reset
  2740. There are many kinds of reset possible through JTAG, but
  2741. they may not all work with a given board and adapter.
  2742. That's part of why reset configuration can be error prone.
  2743. @itemize @bullet
  2744. @item
  2745. @emph{System Reset} ... the @emph{SRST} hardware signal
  2746. resets all chips connected to the JTAG adapter, such as processors,
  2747. power management chips, and I/O controllers. Normally resets triggered
  2748. with this signal behave exactly like pressing a RESET button.
  2749. @item
  2750. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  2751. just the TAP controllers connected to the JTAG adapter.
  2752. Such resets should not be visible to the rest of the system; resetting a
  2753. device's TAP controller just puts that controller into a known state.
  2754. @item
  2755. @emph{Emulation Reset} ... many devices can be reset through JTAG
  2756. commands. These resets are often distinguishable from system
  2757. resets, either explicitly (a "reset reason" register says so)
  2758. or implicitly (not all parts of the chip get reset).
  2759. @item
  2760. @emph{Other Resets} ... system-on-chip devices often support
  2761. several other types of reset.
  2762. You may need to arrange that a watchdog timer stops
  2763. while debugging, preventing a watchdog reset.
  2764. There may be individual module resets.
  2765. @end itemize
  2766. In the best case, OpenOCD can hold SRST, then reset
  2767. the TAPs via TRST and send commands through JTAG to halt the
  2768. CPU at the reset vector before the 1st instruction is executed.
  2769. Then when it finally releases the SRST signal, the system is
  2770. halted under debugger control before any code has executed.
  2771. This is the behavior required to support the @command{reset halt}
  2772. and @command{reset init} commands; after @command{reset init} a
  2773. board-specific script might do things like setting up DRAM.
  2774. (@xref{resetcommand,,Reset Command}.)
  2775. @anchor{srstandtrstissues}
  2776. @section SRST and TRST Issues
  2777. Because SRST and TRST are hardware signals, they can have a
  2778. variety of system-specific constraints. Some of the most
  2779. common issues are:
  2780. @itemize @bullet
  2781. @item @emph{Signal not available} ... Some boards don't wire
  2782. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  2783. support such signals even if they are wired up.
  2784. Use the @command{reset_config} @var{signals} options to say
  2785. when either of those signals is not connected.
  2786. When SRST is not available, your code might not be able to rely
  2787. on controllers having been fully reset during code startup.
  2788. Missing TRST is not a problem, since JTAG-level resets can
  2789. be triggered using with TMS signaling.
  2790. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  2791. adapter will connect SRST to TRST, instead of keeping them separate.
  2792. Use the @command{reset_config} @var{combination} options to say
  2793. when those signals aren't properly independent.
  2794. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  2795. delay circuit, reset supervisor, or on-chip features can extend
  2796. the effect of a JTAG adapter's reset for some time after the adapter
  2797. stops issuing the reset. For example, there may be chip or board
  2798. requirements that all reset pulses last for at least a
  2799. certain amount of time; and reset buttons commonly have
  2800. hardware debouncing.
  2801. Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
  2802. commands to say when extra delays are needed.
  2803. @item @emph{Drive type} ... Reset lines often have a pullup
  2804. resistor, letting the JTAG interface treat them as open-drain
  2805. signals. But that's not a requirement, so the adapter may need
  2806. to use push/pull output drivers.
  2807. Also, with weak pullups it may be advisable to drive
  2808. signals to both levels (push/pull) to minimize rise times.
  2809. Use the @command{reset_config} @var{trst_type} and
  2810. @var{srst_type} parameters to say how to drive reset signals.
  2811. @item @emph{Special initialization} ... Targets sometimes need
  2812. special JTAG initialization sequences to handle chip-specific
  2813. issues (not limited to errata).
  2814. For example, certain JTAG commands might need to be issued while
  2815. the system as a whole is in a reset state (SRST active)
  2816. but the JTAG scan chain is usable (TRST inactive).
  2817. Many systems treat combined assertion of SRST and TRST as a
  2818. trigger for a harder reset than SRST alone.
  2819. Such custom reset handling is discussed later in this chapter.
  2820. @end itemize
  2821. There can also be other issues.
  2822. Some devices don't fully conform to the JTAG specifications.
  2823. Trivial system-specific differences are common, such as
  2824. SRST and TRST using slightly different names.
  2825. There are also vendors who distribute key JTAG documentation for
  2826. their chips only to developers who have signed a Non-Disclosure
  2827. Agreement (NDA).
  2828. Sometimes there are chip-specific extensions like a requirement to use
  2829. the normally-optional TRST signal (precluding use of JTAG adapters which
  2830. don't pass TRST through), or needing extra steps to complete a TAP reset.
  2831. In short, SRST and especially TRST handling may be very finicky,
  2832. needing to cope with both architecture and board specific constraints.
  2833. @section Commands for Handling Resets
  2834. @deffn {Command} adapter_nsrst_assert_width milliseconds
  2835. Minimum amount of time (in milliseconds) OpenOCD should wait
  2836. after asserting nSRST (active-low system reset) before
  2837. allowing it to be deasserted.
  2838. @end deffn
  2839. @deffn {Command} adapter_nsrst_delay milliseconds
  2840. How long (in milliseconds) OpenOCD should wait after deasserting
  2841. nSRST (active-low system reset) before starting new JTAG operations.
  2842. When a board has a reset button connected to SRST line it will
  2843. probably have hardware debouncing, implying you should use this.
  2844. @end deffn
  2845. @deffn {Command} jtag_ntrst_assert_width milliseconds
  2846. Minimum amount of time (in milliseconds) OpenOCD should wait
  2847. after asserting nTRST (active-low JTAG TAP reset) before
  2848. allowing it to be deasserted.
  2849. @end deffn
  2850. @deffn {Command} jtag_ntrst_delay milliseconds
  2851. How long (in milliseconds) OpenOCD should wait after deasserting
  2852. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  2853. @end deffn
  2854. @anchor {reset_config}
  2855. @deffn {Command} reset_config mode_flag ...
  2856. This command displays or modifies the reset configuration
  2857. of your combination of JTAG board and target in target
  2858. configuration scripts.
  2859. Information earlier in this section describes the kind of problems
  2860. the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
  2861. As a rule this command belongs only in board config files,
  2862. describing issues like @emph{board doesn't connect TRST};
  2863. or in user config files, addressing limitations derived
  2864. from a particular combination of interface and board.
  2865. (An unlikely example would be using a TRST-only adapter
  2866. with a board that only wires up SRST.)
  2867. The @var{mode_flag} options can be specified in any order, but only one
  2868. of each type -- @var{signals}, @var{combination}, @var{gates},
  2869. @var{trst_type}, @var{srst_type} and @var{connect_type}
  2870. -- may be specified at a time.
  2871. If you don't provide a new value for a given type, its previous
  2872. value (perhaps the default) is unchanged.
  2873. For example, this means that you don't need to say anything at all about
  2874. TRST just to declare that if the JTAG adapter should want to drive SRST,
  2875. it must explicitly be driven high (@option{srst_push_pull}).
  2876. @itemize
  2877. @item
  2878. @var{signals} can specify which of the reset signals are connected.
  2879. For example, If the JTAG interface provides SRST, but the board doesn't
  2880. connect that signal properly, then OpenOCD can't use it.
  2881. Possible values are @option{none} (the default), @option{trst_only},
  2882. @option{srst_only} and @option{trst_and_srst}.
  2883. @quotation Tip
  2884. If your board provides SRST and/or TRST through the JTAG connector,
  2885. you must declare that so those signals can be used.
  2886. @end quotation
  2887. @item
  2888. The @var{combination} is an optional value specifying broken reset
  2889. signal implementations.
  2890. The default behaviour if no option given is @option{separate},
  2891. indicating everything behaves normally.
  2892. @option{srst_pulls_trst} states that the
  2893. test logic is reset together with the reset of the system (e.g. NXP
  2894. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  2895. the system is reset together with the test logic (only hypothetical, I
  2896. haven't seen hardware with such a bug, and can be worked around).
  2897. @option{combined} implies both @option{srst_pulls_trst} and
  2898. @option{trst_pulls_srst}.
  2899. @item
  2900. The @var{gates} tokens control flags that describe some cases where
  2901. JTAG may be unavailable during reset.
  2902. @option{srst_gates_jtag} (default)
  2903. indicates that asserting SRST gates the
  2904. JTAG clock. This means that no communication can happen on JTAG
  2905. while SRST is asserted.
  2906. Its converse is @option{srst_nogate}, indicating that JTAG commands
  2907. can safely be issued while SRST is active.
  2908. @item
  2909. The @var{connect_type} tokens control flags that describe some cases where
  2910. SRST is asserted while connecting to the target. @option{srst_nogate}
  2911. is required to use this option.
  2912. @option{connect_deassert_srst} (default)
  2913. indicates that SRST will not be asserted while connecting to the target.
  2914. Its converse is @option{connect_assert_srst}, indicating that SRST will
  2915. be asserted before any target connection.
  2916. Only some targets support this feature, STM32 and STR9 are examples.
  2917. This feature is useful if you are unable to connect to your target due
  2918. to incorrect options byte config or illegal program execution.
  2919. @end itemize
  2920. The optional @var{trst_type} and @var{srst_type} parameters allow the
  2921. driver mode of each reset line to be specified. These values only affect
  2922. JTAG interfaces with support for different driver modes, like the Amontec
  2923. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  2924. relevant signal (TRST or SRST) is not connected.
  2925. @itemize
  2926. @item
  2927. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  2928. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  2929. Most boards connect this signal to a pulldown, so the JTAG TAPs
  2930. never leave reset unless they are hooked up to a JTAG adapter.
  2931. @item
  2932. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  2933. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  2934. Most boards connect this signal to a pullup, and allow the
  2935. signal to be pulled low by various events including system
  2936. power-up and pressing a reset button.
  2937. @end itemize
  2938. @end deffn
  2939. @section Custom Reset Handling
  2940. @cindex events
  2941. OpenOCD has several ways to help support the various reset
  2942. mechanisms provided by chip and board vendors.
  2943. The commands shown in the previous section give standard parameters.
  2944. There are also @emph{event handlers} associated with TAPs or Targets.
  2945. Those handlers are Tcl procedures you can provide, which are invoked
  2946. at particular points in the reset sequence.
  2947. @emph{When SRST is not an option} you must set
  2948. up a @code{reset-assert} event handler for your target.
  2949. For example, some JTAG adapters don't include the SRST signal;
  2950. and some boards have multiple targets, and you won't always
  2951. want to reset everything at once.
  2952. After configuring those mechanisms, you might still
  2953. find your board doesn't start up or reset correctly.
  2954. For example, maybe it needs a slightly different sequence
  2955. of SRST and/or TRST manipulations, because of quirks that
  2956. the @command{reset_config} mechanism doesn't address;
  2957. or asserting both might trigger a stronger reset, which
  2958. needs special attention.
  2959. Experiment with lower level operations, such as @command{jtag_reset}
  2960. and the @command{jtag arp_*} operations shown here,
  2961. to find a sequence of operations that works.
  2962. @xref{JTAG Commands}.
  2963. When you find a working sequence, it can be used to override
  2964. @command{jtag_init}, which fires during OpenOCD startup
  2965. (@pxref{configurationstage,,Configuration Stage});
  2966. or @command{init_reset}, which fires during reset processing.
  2967. You might also want to provide some project-specific reset
  2968. schemes. For example, on a multi-target board the standard
  2969. @command{reset} command would reset all targets, but you
  2970. may need the ability to reset only one target at time and
  2971. thus want to avoid using the board-wide SRST signal.
  2972. @deffn {Overridable Procedure} init_reset mode
  2973. This is invoked near the beginning of the @command{reset} command,
  2974. usually to provide as much of a cold (power-up) reset as practical.
  2975. By default it is also invoked from @command{jtag_init} if
  2976. the scan chain does not respond to pure JTAG operations.
  2977. The @var{mode} parameter is the parameter given to the
  2978. low level reset command (@option{halt},
  2979. @option{init}, or @option{run}), @option{setup},
  2980. or potentially some other value.
  2981. The default implementation just invokes @command{jtag arp_init-reset}.
  2982. Replacements will normally build on low level JTAG
  2983. operations such as @command{jtag_reset}.
  2984. Operations here must not address individual TAPs
  2985. (or their associated targets)
  2986. until the JTAG scan chain has first been verified to work.
  2987. Implementations must have verified the JTAG scan chain before
  2988. they return.
  2989. This is done by calling @command{jtag arp_init}
  2990. (or @command{jtag arp_init-reset}).
  2991. @end deffn
  2992. @deffn Command {jtag arp_init}
  2993. This validates the scan chain using just the four
  2994. standard JTAG signals (TMS, TCK, TDI, TDO).
  2995. It starts by issuing a JTAG-only reset.
  2996. Then it performs checks to verify that the scan chain configuration
  2997. matches the TAPs it can observe.
  2998. Those checks include checking IDCODE values for each active TAP,
  2999. and verifying the length of their instruction registers using
  3000. TAP @code{-ircapture} and @code{-irmask} values.
  3001. If these tests all pass, TAP @code{setup} events are
  3002. issued to all TAPs with handlers for that event.
  3003. @end deffn
  3004. @deffn Command {jtag arp_init-reset}
  3005. This uses TRST and SRST to try resetting
  3006. everything on the JTAG scan chain
  3007. (and anything else connected to SRST).
  3008. It then invokes the logic of @command{jtag arp_init}.
  3009. @end deffn
  3010. @node TAP Declaration
  3011. @chapter TAP Declaration
  3012. @cindex TAP declaration
  3013. @cindex TAP configuration
  3014. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  3015. TAPs serve many roles, including:
  3016. @itemize @bullet
  3017. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
  3018. @item @b{Flash Programming} Some chips program the flash directly via JTAG.
  3019. Others do it indirectly, making a CPU do it.
  3020. @item @b{Program Download} Using the same CPU support GDB uses,
  3021. you can initialize a DRAM controller, download code to DRAM, and then
  3022. start running that code.
  3023. @item @b{Boundary Scan} Most chips support boundary scan, which
  3024. helps test for board assembly problems like solder bridges
  3025. and missing connections.
  3026. @end itemize
  3027. OpenOCD must know about the active TAPs on your board(s).
  3028. Setting up the TAPs is the core task of your configuration files.
  3029. Once those TAPs are set up, you can pass their names to code
  3030. which sets up CPUs and exports them as GDB targets,
  3031. probes flash memory, performs low-level JTAG operations, and more.
  3032. @section Scan Chains
  3033. @cindex scan chain
  3034. TAPs are part of a hardware @dfn{scan chain},
  3035. which is a daisy chain of TAPs.
  3036. They also need to be added to
  3037. OpenOCD's software mirror of that hardware list,
  3038. giving each member a name and associating other data with it.
  3039. Simple scan chains, with a single TAP, are common in
  3040. systems with a single microcontroller or microprocessor.
  3041. More complex chips may have several TAPs internally.
  3042. Very complex scan chains might have a dozen or more TAPs:
  3043. several in one chip, more in the next, and connecting
  3044. to other boards with their own chips and TAPs.
  3045. You can display the list with the @command{scan_chain} command.
  3046. (Don't confuse this with the list displayed by the @command{targets}
  3047. command, presented in the next chapter.
  3048. That only displays TAPs for CPUs which are configured as
  3049. debugging targets.)
  3050. Here's what the scan chain might look like for a chip more than one TAP:
  3051. @verbatim
  3052. TapName Enabled IdCode Expected IrLen IrCap IrMask
  3053. -- ------------------ ------- ---------- ---------- ----- ----- ------
  3054. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  3055. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  3056. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  3057. @end verbatim
  3058. OpenOCD can detect some of that information, but not all
  3059. of it. @xref{autoprobing,,Autoprobing}.
  3060. Unfortunately, those TAPs can't always be autoconfigured,
  3061. because not all devices provide good support for that.
  3062. JTAG doesn't require supporting IDCODE instructions, and
  3063. chips with JTAG routers may not link TAPs into the chain
  3064. until they are told to do so.
  3065. The configuration mechanism currently supported by OpenOCD
  3066. requires explicit configuration of all TAP devices using
  3067. @command{jtag newtap} commands, as detailed later in this chapter.
  3068. A command like this would declare one tap and name it @code{chip1.cpu}:
  3069. @example
  3070. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  3071. @end example
  3072. Each target configuration file lists the TAPs provided
  3073. by a given chip.
  3074. Board configuration files combine all the targets on a board,
  3075. and so forth.
  3076. Note that @emph{the order in which TAPs are declared is very important.}
  3077. That declaration order must match the order in the JTAG scan chain,
  3078. both inside a single chip and between them.
  3079. @xref{faqtaporder,,FAQ TAP Order}.
  3080. For example, the STMicroelectronics STR912 chip has
  3081. three separate TAPs@footnote{See the ST
  3082. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  3083. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  3084. @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
  3085. To configure those taps, @file{target/str912.cfg}
  3086. includes commands something like this:
  3087. @example
  3088. jtag newtap str912 flash ... params ...
  3089. jtag newtap str912 cpu ... params ...
  3090. jtag newtap str912 bs ... params ...
  3091. @end example
  3092. Actual config files typically use a variable such as @code{$_CHIPNAME}
  3093. instead of literals like @option{str912}, to support more than one chip
  3094. of each type. @xref{Config File Guidelines}.
  3095. @deffn Command {jtag names}
  3096. Returns the names of all current TAPs in the scan chain.
  3097. Use @command{jtag cget} or @command{jtag tapisenabled}
  3098. to examine attributes and state of each TAP.
  3099. @example
  3100. foreach t [jtag names] @{
  3101. puts [format "TAP: %s\n" $t]
  3102. @}
  3103. @end example
  3104. @end deffn
  3105. @deffn Command {scan_chain}
  3106. Displays the TAPs in the scan chain configuration,
  3107. and their status.
  3108. The set of TAPs listed by this command is fixed by
  3109. exiting the OpenOCD configuration stage,
  3110. but systems with a JTAG router can
  3111. enable or disable TAPs dynamically.
  3112. @end deffn
  3113. @c FIXME! "jtag cget" should be able to return all TAP
  3114. @c attributes, like "$target_name cget" does for targets.
  3115. @c Probably want "jtag eventlist", and a "tap-reset" event
  3116. @c (on entry to RESET state).
  3117. @section TAP Names
  3118. @cindex dotted name
  3119. When TAP objects are declared with @command{jtag newtap},
  3120. a @dfn{dotted.name} is created for the TAP, combining the
  3121. name of a module (usually a chip) and a label for the TAP.
  3122. For example: @code{xilinx.tap}, @code{str912.flash},
  3123. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  3124. Many other commands use that dotted.name to manipulate or
  3125. refer to the TAP. For example, CPU configuration uses the
  3126. name, as does declaration of NAND or NOR flash banks.
  3127. The components of a dotted name should follow ``C'' symbol
  3128. name rules: start with an alphabetic character, then numbers
  3129. and underscores are OK; while others (including dots!) are not.
  3130. @section TAP Declaration Commands
  3131. @c shouldn't this be(come) a {Config Command}?
  3132. @deffn Command {jtag newtap} chipname tapname configparams...
  3133. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  3134. and configured according to the various @var{configparams}.
  3135. The @var{chipname} is a symbolic name for the chip.
  3136. Conventionally target config files use @code{$_CHIPNAME},
  3137. defaulting to the model name given by the chip vendor but
  3138. overridable.
  3139. @cindex TAP naming convention
  3140. The @var{tapname} reflects the role of that TAP,
  3141. and should follow this convention:
  3142. @itemize @bullet
  3143. @item @code{bs} -- For boundary scan if this is a separate TAP;
  3144. @item @code{cpu} -- The main CPU of the chip, alternatively
  3145. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  3146. @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
  3147. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  3148. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  3149. @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
  3150. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  3151. @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
  3152. with a single TAP;
  3153. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  3154. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  3155. For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
  3156. a JTAG TAP; that TAP should be named @code{sdma}.
  3157. @end itemize
  3158. Every TAP requires at least the following @var{configparams}:
  3159. @itemize @bullet
  3160. @item @code{-irlen} @var{NUMBER}
  3161. @*The length in bits of the
  3162. instruction register, such as 4 or 5 bits.
  3163. @end itemize
  3164. A TAP may also provide optional @var{configparams}:
  3165. @itemize @bullet
  3166. @item @code{-disable} (or @code{-enable})
  3167. @*Use the @code{-disable} parameter to flag a TAP which is not
  3168. linked into the scan chain after a reset using either TRST
  3169. or the JTAG state machine's @sc{reset} state.
  3170. You may use @code{-enable} to highlight the default state
  3171. (the TAP is linked in).
  3172. @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
  3173. @item @code{-expected-id} @var{NUMBER}
  3174. @*A non-zero @var{number} represents a 32-bit IDCODE
  3175. which you expect to find when the scan chain is examined.
  3176. These codes are not required by all JTAG devices.
  3177. @emph{Repeat the option} as many times as required if more than one
  3178. ID code could appear (for example, multiple versions).
  3179. Specify @var{number} as zero to suppress warnings about IDCODE
  3180. values that were found but not included in the list.
  3181. Provide this value if at all possible, since it lets OpenOCD
  3182. tell when the scan chain it sees isn't right. These values
  3183. are provided in vendors' chip documentation, usually a technical
  3184. reference manual. Sometimes you may need to probe the JTAG
  3185. hardware to find these values.
  3186. @xref{autoprobing,,Autoprobing}.
  3187. @item @code{-ignore-version}
  3188. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  3189. option. When vendors put out multiple versions of a chip, or use the same
  3190. JTAG-level ID for several largely-compatible chips, it may be more practical
  3191. to ignore the version field than to update config files to handle all of
  3192. the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
  3193. @item @code{-ircapture} @var{NUMBER}
  3194. @*The bit pattern loaded by the TAP into the JTAG shift register
  3195. on entry to the @sc{ircapture} state, such as 0x01.
  3196. JTAG requires the two LSBs of this value to be 01.
  3197. By default, @code{-ircapture} and @code{-irmask} are set
  3198. up to verify that two-bit value. You may provide
  3199. additional bits if you know them, or indicate that
  3200. a TAP doesn't conform to the JTAG specification.
  3201. @item @code{-irmask} @var{NUMBER}
  3202. @*A mask used with @code{-ircapture}
  3203. to verify that instruction scans work correctly.
  3204. Such scans are not used by OpenOCD except to verify that
  3205. there seems to be no problems with JTAG scan chain operations.
  3206. @item @code{-ignore-syspwrupack}
  3207. @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
  3208. register during initial examination and when checking the sticky error bit.
  3209. This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
  3210. devices do not set the ack bit until sometime later.
  3211. @end itemize
  3212. @end deffn
  3213. @section Other TAP commands
  3214. @deffn Command {jtag cget} dotted.name @option{-event} event_name
  3215. @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
  3216. At this writing this TAP attribute
  3217. mechanism is used only for event handling.
  3218. (It is not a direct analogue of the @code{cget}/@code{configure}
  3219. mechanism for debugger targets.)
  3220. See the next section for information about the available events.
  3221. The @code{configure} subcommand assigns an event handler,
  3222. a TCL string which is evaluated when the event is triggered.
  3223. The @code{cget} subcommand returns that handler.
  3224. @end deffn
  3225. @section TAP Events
  3226. @cindex events
  3227. @cindex TAP events
  3228. OpenOCD includes two event mechanisms.
  3229. The one presented here applies to all JTAG TAPs.
  3230. The other applies to debugger targets,
  3231. which are associated with certain TAPs.
  3232. The TAP events currently defined are:
  3233. @itemize @bullet
  3234. @item @b{post-reset}
  3235. @* The TAP has just completed a JTAG reset.
  3236. The tap may still be in the JTAG @sc{reset} state.
  3237. Handlers for these events might perform initialization sequences
  3238. such as issuing TCK cycles, TMS sequences to ensure
  3239. exit from the ARM SWD mode, and more.
  3240. Because the scan chain has not yet been verified, handlers for these events
  3241. @emph{should not issue commands which scan the JTAG IR or DR registers}
  3242. of any particular target.
  3243. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  3244. @item @b{setup}
  3245. @* The scan chain has been reset and verified.
  3246. This handler may enable TAPs as needed.
  3247. @item @b{tap-disable}
  3248. @* The TAP needs to be disabled. This handler should
  3249. implement @command{jtag tapdisable}
  3250. by issuing the relevant JTAG commands.
  3251. @item @b{tap-enable}
  3252. @* The TAP needs to be enabled. This handler should
  3253. implement @command{jtag tapenable}
  3254. by issuing the relevant JTAG commands.
  3255. @end itemize
  3256. If you need some action after each JTAG reset which isn't actually
  3257. specific to any TAP (since you can't yet trust the scan chain's
  3258. contents to be accurate), you might:
  3259. @example
  3260. jtag configure CHIP.jrc -event post-reset @{
  3261. echo "JTAG Reset done"
  3262. ... non-scan jtag operations to be done after reset
  3263. @}
  3264. @end example
  3265. @anchor{enablinganddisablingtaps}
  3266. @section Enabling and Disabling TAPs
  3267. @cindex JTAG Route Controller
  3268. @cindex jrc
  3269. In some systems, a @dfn{JTAG Route Controller} (JRC)
  3270. is used to enable and/or disable specific JTAG TAPs.
  3271. Many ARM-based chips from Texas Instruments include
  3272. an ``ICEPick'' module, which is a JRC.
  3273. Such chips include DaVinci and OMAP3 processors.
  3274. A given TAP may not be visible until the JRC has been
  3275. told to link it into the scan chain; and if the JRC
  3276. has been told to unlink that TAP, it will no longer
  3277. be visible.
  3278. Such routers address problems that JTAG ``bypass mode''
  3279. ignores, such as:
  3280. @itemize
  3281. @item The scan chain can only go as fast as its slowest TAP.
  3282. @item Having many TAPs slows instruction scans, since all
  3283. TAPs receive new instructions.
  3284. @item TAPs in the scan chain must be powered up, which wastes
  3285. power and prevents debugging some power management mechanisms.
  3286. @end itemize
  3287. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  3288. as implied by the existence of JTAG routers.
  3289. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  3290. does include a kind of JTAG router functionality.
  3291. @c (a) currently the event handlers don't seem to be able to
  3292. @c fail in a way that could lead to no-change-of-state.
  3293. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  3294. shown below, and is implemented using TAP event handlers.
  3295. So for example, when defining a TAP for a CPU connected to
  3296. a JTAG router, your @file{target.cfg} file
  3297. should define TAP event handlers using
  3298. code that looks something like this:
  3299. @example
  3300. jtag configure CHIP.cpu -event tap-enable @{
  3301. ... jtag operations using CHIP.jrc
  3302. @}
  3303. jtag configure CHIP.cpu -event tap-disable @{
  3304. ... jtag operations using CHIP.jrc
  3305. @}
  3306. @end example
  3307. Then you might want that CPU's TAP enabled almost all the time:
  3308. @example
  3309. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  3310. @end example
  3311. Note how that particular setup event handler declaration
  3312. uses quotes to evaluate @code{$CHIP} when the event is configured.
  3313. Using brackets @{ @} would cause it to be evaluated later,
  3314. at runtime, when it might have a different value.
  3315. @deffn Command {jtag tapdisable} dotted.name
  3316. If necessary, disables the tap
  3317. by sending it a @option{tap-disable} event.
  3318. Returns the string "1" if the tap
  3319. specified by @var{dotted.name} is enabled,
  3320. and "0" if it is disabled.
  3321. @end deffn
  3322. @deffn Command {jtag tapenable} dotted.name
  3323. If necessary, enables the tap
  3324. by sending it a @option{tap-enable} event.
  3325. Returns the string "1" if the tap
  3326. specified by @var{dotted.name} is enabled,
  3327. and "0" if it is disabled.
  3328. @end deffn
  3329. @deffn Command {jtag tapisenabled} dotted.name
  3330. Returns the string "1" if the tap
  3331. specified by @var{dotted.name} is enabled,
  3332. and "0" if it is disabled.
  3333. @quotation Note
  3334. Humans will find the @command{scan_chain} command more helpful
  3335. for querying the state of the JTAG taps.
  3336. @end quotation
  3337. @end deffn
  3338. @anchor{autoprobing}
  3339. @section Autoprobing
  3340. @cindex autoprobe
  3341. @cindex JTAG autoprobe
  3342. TAP configuration is the first thing that needs to be done
  3343. after interface and reset configuration. Sometimes it's
  3344. hard finding out what TAPs exist, or how they are identified.
  3345. Vendor documentation is not always easy to find and use.
  3346. To help you get past such problems, OpenOCD has a limited
  3347. @emph{autoprobing} ability to look at the scan chain, doing
  3348. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  3349. To use this mechanism, start the OpenOCD server with only data
  3350. that configures your JTAG interface, and arranges to come up
  3351. with a slow clock (many devices don't support fast JTAG clocks
  3352. right when they come out of reset).
  3353. For example, your @file{openocd.cfg} file might have:
  3354. @example
  3355. source [find interface/olimex-arm-usb-tiny-h.cfg]
  3356. reset_config trst_and_srst
  3357. jtag_rclk 8
  3358. @end example
  3359. When you start the server without any TAPs configured, it will
  3360. attempt to autoconfigure the TAPs. There are two parts to this:
  3361. @enumerate
  3362. @item @emph{TAP discovery} ...
  3363. After a JTAG reset (sometimes a system reset may be needed too),
  3364. each TAP's data registers will hold the contents of either the
  3365. IDCODE or BYPASS register.
  3366. If JTAG communication is working, OpenOCD will see each TAP,
  3367. and report what @option{-expected-id} to use with it.
  3368. @item @emph{IR Length discovery} ...
  3369. Unfortunately JTAG does not provide a reliable way to find out
  3370. the value of the @option{-irlen} parameter to use with a TAP
  3371. that is discovered.
  3372. If OpenOCD can discover the length of a TAP's instruction
  3373. register, it will report it.
  3374. Otherwise you may need to consult vendor documentation, such
  3375. as chip data sheets or BSDL files.
  3376. @end enumerate
  3377. In many cases your board will have a simple scan chain with just
  3378. a single device. Here's what OpenOCD reported with one board
  3379. that's a bit more complex:
  3380. @example
  3381. clock speed 8 kHz
  3382. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  3383. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  3384. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  3385. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  3386. AUTO auto0.tap - use "... -irlen 4"
  3387. AUTO auto1.tap - use "... -irlen 4"
  3388. AUTO auto2.tap - use "... -irlen 6"
  3389. no gdb ports allocated as no target has been specified
  3390. @end example
  3391. Given that information, you should be able to either find some existing
  3392. config files to use, or create your own. If you create your own, you
  3393. would configure from the bottom up: first a @file{target.cfg} file
  3394. with these TAPs, any targets associated with them, and any on-chip
  3395. resources; then a @file{board.cfg} with off-chip resources, clocking,
  3396. and so forth.
  3397. @anchor{dapdeclaration}
  3398. @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
  3399. @cindex DAP declaration
  3400. Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
  3401. no longer implicitly created together with the target. It must be
  3402. explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
  3403. and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
  3404. instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
  3405. The @command{dap} command group supports the following sub-commands:
  3406. @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
  3407. Declare a DAP instance named @var{dap_name} linked to the JTAG tap
  3408. @var{dotted.name}. This also creates a new command (@command{dap_name})
  3409. which is used for various purposes including additional configuration.
  3410. There can only be one DAP for each JTAG tap in the system.
  3411. A DAP may also provide optional @var{configparams}:
  3412. @itemize @bullet
  3413. @item @code{-ignore-syspwrupack}
  3414. @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
  3415. register during initial examination and when checking the sticky error bit.
  3416. This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
  3417. devices do not set the ack bit until sometime later.
  3418. @end itemize
  3419. @end deffn
  3420. @deffn Command {dap names}
  3421. This command returns a list of all registered DAP objects. It it useful mainly
  3422. for TCL scripting.
  3423. @end deffn
  3424. @deffn Command {dap info} [num]
  3425. Displays the ROM table for MEM-AP @var{num},
  3426. defaulting to the currently selected AP of the currently selected target.
  3427. @end deffn
  3428. @deffn Command {dap init}
  3429. Initialize all registered DAPs. This command is used internally
  3430. during initialization. It can be issued at any time after the
  3431. initialization, too.
  3432. @end deffn
  3433. The following commands exist as subcommands of DAP instances:
  3434. @deffn Command {$dap_name info} [num]
  3435. Displays the ROM table for MEM-AP @var{num},
  3436. defaulting to the currently selected AP.
  3437. @end deffn
  3438. @deffn Command {$dap_name apid} [num]
  3439. Displays ID register from AP @var{num}, defaulting to the currently selected AP.
  3440. @end deffn
  3441. @anchor{DAP subcommand apreg}
  3442. @deffn Command {$dap_name apreg} ap_num reg [value]
  3443. Displays content of a register @var{reg} from AP @var{ap_num}
  3444. or set a new value @var{value}.
  3445. @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
  3446. @end deffn
  3447. @deffn Command {$dap_name apsel} [num]
  3448. Select AP @var{num}, defaulting to 0.
  3449. @end deffn
  3450. @deffn Command {$dap_name dpreg} reg [value]
  3451. Displays the content of DP register at address @var{reg}, or set it to a new
  3452. value @var{value}.
  3453. In case of SWD, @var{reg} is a value in packed format
  3454. @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
  3455. In case of JTAG it only assumes values 0, 4, 8 and 0xc.
  3456. @emph{Note:} Consider using @command{poll off} to avoid any disturbing
  3457. background activity by OpenOCD while you are operating at such low-level.
  3458. @end deffn
  3459. @deffn Command {$dap_name baseaddr} [num]
  3460. Displays debug base address from MEM-AP @var{num},
  3461. defaulting to the currently selected AP.
  3462. @end deffn
  3463. @deffn Command {$dap_name memaccess} [value]
  3464. Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
  3465. memory bus access [0-255], giving additional time to respond to reads.
  3466. If @var{value} is defined, first assigns that.
  3467. @end deffn
  3468. @deffn Command {$dap_name apcsw} [value [mask]]
  3469. Displays or changes CSW bit pattern for MEM-AP transfers.
  3470. At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
  3471. by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
  3472. and the result is written to the real CSW register. All bits except dynamically
  3473. updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
  3474. the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
  3475. for details.
  3476. Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
  3477. The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
  3478. the pattern:
  3479. @example
  3480. kx.dap apcsw 0x2000000
  3481. @end example
  3482. If @var{mask} is also used, the CSW pattern is changed only on bit positions
  3483. where the mask bit is 1. The following example sets HPROT3 (cacheable)
  3484. and leaves the rest of the pattern intact. It configures memory access through
  3485. DCache on Cortex-M7.
  3486. @example
  3487. set CSW_HPROT3_CACHEABLE [expr 1 << 27]
  3488. samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
  3489. @end example
  3490. Another example clears SPROT bit and leaves the rest of pattern intact:
  3491. @example
  3492. set CSW_SPROT [expr 1 << 30]
  3493. samv.dap apcsw 0 $CSW_SPROT
  3494. @end example
  3495. @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
  3496. @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
  3497. @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
  3498. If you set a wrong CSW pattern and MEM-AP stopped working, use the following
  3499. example with a proper dap name:
  3500. @example
  3501. xxx.dap apcsw default
  3502. @end example
  3503. @end deffn
  3504. @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
  3505. Set/get quirks mode for TI TMS450/TMS570 processors
  3506. Disabled by default
  3507. @end deffn
  3508. @node CPU Configuration
  3509. @chapter CPU Configuration
  3510. @cindex GDB target
  3511. This chapter discusses how to set up GDB debug targets for CPUs.
  3512. You can also access these targets without GDB
  3513. (@pxref{Architecture and Core Commands},
  3514. and @ref{targetstatehandling,,Target State handling}) and
  3515. through various kinds of NAND and NOR flash commands.
  3516. If you have multiple CPUs you can have multiple such targets.
  3517. We'll start by looking at how to examine the targets you have,
  3518. then look at how to add one more target and how to configure it.
  3519. @section Target List
  3520. @cindex target, current
  3521. @cindex target, list
  3522. All targets that have been set up are part of a list,
  3523. where each member has a name.
  3524. That name should normally be the same as the TAP name.
  3525. You can display the list with the @command{targets}
  3526. (plural!) command.
  3527. This display often has only one CPU; here's what it might
  3528. look like with more than one:
  3529. @verbatim
  3530. TargetName Type Endian TapName State
  3531. -- ------------------ ---------- ------ ------------------ ------------
  3532. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  3533. 1 MyTarget cortex_m little mychip.foo tap-disabled
  3534. @end verbatim
  3535. One member of that list is the @dfn{current target}, which
  3536. is implicitly referenced by many commands.
  3537. It's the one marked with a @code{*} near the target name.
  3538. In particular, memory addresses often refer to the address
  3539. space seen by that current target.
  3540. Commands like @command{mdw} (memory display words)
  3541. and @command{flash erase_address} (erase NOR flash blocks)
  3542. are examples; and there are many more.
  3543. Several commands let you examine the list of targets:
  3544. @deffn Command {target current}
  3545. Returns the name of the current target.
  3546. @end deffn
  3547. @deffn Command {target names}
  3548. Lists the names of all current targets in the list.
  3549. @example
  3550. foreach t [target names] @{
  3551. puts [format "Target: %s\n" $t]
  3552. @}
  3553. @end example
  3554. @end deffn
  3555. @c yep, "target list" would have been better.
  3556. @c plus maybe "target setdefault".
  3557. @deffn Command targets [name]
  3558. @emph{Note: the name of this command is plural. Other target
  3559. command names are singular.}
  3560. With no parameter, this command displays a table of all known
  3561. targets in a user friendly form.
  3562. With a parameter, this command sets the current target to
  3563. the given target with the given @var{name}; this is
  3564. only relevant on boards which have more than one target.
  3565. @end deffn
  3566. @section Target CPU Types
  3567. @cindex target type
  3568. @cindex CPU type
  3569. Each target has a @dfn{CPU type}, as shown in the output of
  3570. the @command{targets} command. You need to specify that type
  3571. when calling @command{target create}.
  3572. The CPU type indicates more than just the instruction set.
  3573. It also indicates how that instruction set is implemented,
  3574. what kind of debug support it integrates,
  3575. whether it has an MMU (and if so, what kind),
  3576. what core-specific commands may be available
  3577. (@pxref{Architecture and Core Commands}),
  3578. and more.
  3579. It's easy to see what target types are supported,
  3580. since there's a command to list them.
  3581. @anchor{targettypes}
  3582. @deffn Command {target types}
  3583. Lists all supported target types.
  3584. At this writing, the supported CPU types are:
  3585. @itemize @bullet
  3586. @item @code{arm11} -- this is a generation of ARMv6 cores
  3587. @item @code{arm720t} -- this is an ARMv4 core with an MMU
  3588. @item @code{arm7tdmi} -- this is an ARMv4 core
  3589. @item @code{arm920t} -- this is an ARMv4 core with an MMU
  3590. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
  3591. @item @code{arm966e} -- this is an ARMv5 core
  3592. @item @code{arm9tdmi} -- this is an ARMv4 core
  3593. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  3594. (Support for this is preliminary and incomplete.)
  3595. @item @code{cortex_a} -- this is an ARMv7 core with an MMU
  3596. @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
  3597. compact Thumb2 instruction set.
  3598. @item @code{aarch64} -- this is an ARMv8-A core with an MMU
  3599. @item @code{dragonite} -- resembles arm966e
  3600. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  3601. (Support for this is still incomplete.)
  3602. @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
  3603. The current implementation supports eSi-32xx cores.
  3604. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  3605. @item @code{feroceon} -- resembles arm926
  3606. @item @code{mips_m4k} -- a MIPS core
  3607. @item @code{xscale} -- this is actually an architecture,
  3608. not a CPU type. It is based on the ARMv5 architecture.
  3609. @item @code{openrisc} -- this is an OpenRISC 1000 core.
  3610. The current implementation supports three JTAG TAP cores:
  3611. @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
  3612. allowing access to physical memory addresses independently of CPU cores.
  3613. @itemize @minus
  3614. @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
  3615. @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
  3616. @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
  3617. @end itemize
  3618. And two debug interfaces cores:
  3619. @itemize @minus
  3620. @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
  3621. @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
  3622. @end itemize
  3623. @end itemize
  3624. @end deffn
  3625. To avoid being confused by the variety of ARM based cores, remember
  3626. this key point: @emph{ARM is a technology licencing company}.
  3627. (See: @url{http://www.arm.com}.)
  3628. The CPU name used by OpenOCD will reflect the CPU design that was
  3629. licensed, not a vendor brand which incorporates that design.
  3630. Name prefixes like arm7, arm9, arm11, and cortex
  3631. reflect design generations;
  3632. while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
  3633. reflect an architecture version implemented by a CPU design.
  3634. @anchor{targetconfiguration}
  3635. @section Target Configuration
  3636. Before creating a ``target'', you must have added its TAP to the scan chain.
  3637. When you've added that TAP, you will have a @code{dotted.name}
  3638. which is used to set up the CPU support.
  3639. The chip-specific configuration file will normally configure its CPU(s)
  3640. right after it adds all of the chip's TAPs to the scan chain.
  3641. Although you can set up a target in one step, it's often clearer if you
  3642. use shorter commands and do it in two steps: create it, then configure
  3643. optional parts.
  3644. All operations on the target after it's created will use a new
  3645. command, created as part of target creation.
  3646. The two main things to configure after target creation are
  3647. a work area, which usually has target-specific defaults even
  3648. if the board setup code overrides them later;
  3649. and event handlers (@pxref{targetevents,,Target Events}), which tend
  3650. to be much more board-specific.
  3651. The key steps you use might look something like this
  3652. @example
  3653. dap create mychip.dap -chain-position mychip.cpu
  3654. target create MyTarget cortex_m -dap mychip.dap
  3655. MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  3656. MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  3657. MyTarget configure -event reset-init @{ myboard_reinit @}
  3658. @end example
  3659. You should specify a working area if you can; typically it uses some
  3660. on-chip SRAM.
  3661. Such a working area can speed up many things, including bulk
  3662. writes to target memory;
  3663. flash operations like checking to see if memory needs to be erased;
  3664. GDB memory checksumming;
  3665. and more.
  3666. @quotation Warning
  3667. On more complex chips, the work area can become
  3668. inaccessible when application code
  3669. (such as an operating system)
  3670. enables or disables the MMU.
  3671. For example, the particular MMU context used to access the virtual
  3672. address will probably matter ... and that context might not have
  3673. easy access to other addresses needed.
  3674. At this writing, OpenOCD doesn't have much MMU intelligence.
  3675. @end quotation
  3676. It's often very useful to define a @code{reset-init} event handler.
  3677. For systems that are normally used with a boot loader,
  3678. common tasks include updating clocks and initializing memory
  3679. controllers.
  3680. That may be needed to let you write the boot loader into flash,
  3681. in order to ``de-brick'' your board; or to load programs into
  3682. external DDR memory without having run the boot loader.
  3683. @deffn Command {target create} target_name type configparams...
  3684. This command creates a GDB debug target that refers to a specific JTAG tap.
  3685. It enters that target into a list, and creates a new
  3686. command (@command{@var{target_name}}) which is used for various
  3687. purposes including additional configuration.
  3688. @itemize @bullet
  3689. @item @var{target_name} ... is the name of the debug target.
  3690. By convention this should be the same as the @emph{dotted.name}
  3691. of the TAP associated with this target, which must be specified here
  3692. using the @code{-chain-position @var{dotted.name}} configparam.
  3693. This name is also used to create the target object command,
  3694. referred to here as @command{$target_name},
  3695. and in other places the target needs to be identified.
  3696. @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
  3697. @item @var{configparams} ... all parameters accepted by
  3698. @command{$target_name configure} are permitted.
  3699. If the target is big-endian, set it here with @code{-endian big}.
  3700. You @emph{must} set the @code{-chain-position @var{dotted.name}} or
  3701. @code{-dap @var{dap_name}} here.
  3702. @end itemize
  3703. @end deffn
  3704. @deffn Command {$target_name configure} configparams...
  3705. The options accepted by this command may also be
  3706. specified as parameters to @command{target create}.
  3707. Their values can later be queried one at a time by
  3708. using the @command{$target_name cget} command.
  3709. @emph{Warning:} changing some of these after setup is dangerous.
  3710. For example, moving a target from one TAP to another;
  3711. and changing its endianness.
  3712. @itemize @bullet
  3713. @item @code{-chain-position} @var{dotted.name} -- names the TAP
  3714. used to access this target.
  3715. @item @code{-dap} @var{dap_name} -- names the DAP used to access
  3716. this target. @xref{dapdeclaration,,DAP declaration}, on how to
  3717. create and manage DAP instances.
  3718. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  3719. whether the CPU uses big or little endian conventions
  3720. @item @code{-event} @var{event_name} @var{event_body} --
  3721. @xref{targetevents,,Target Events}.
  3722. Note that this updates a list of named event handlers.
  3723. Calling this twice with two different event names assigns
  3724. two different handlers, but calling it twice with the
  3725. same event name assigns only one handler.
  3726. Current target is temporarily overridden to the event issuing target
  3727. before handler code starts and switched back after handler is done.
  3728. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  3729. whether the work area gets backed up; by default,
  3730. @emph{it is not backed up.}
  3731. When possible, use a working_area that doesn't need to be backed up,
  3732. since performing a backup slows down operations.
  3733. For example, the beginning of an SRAM block is likely to
  3734. be used by most build systems, but the end is often unused.
  3735. @item @code{-work-area-size} @var{size} -- specify work are size,
  3736. in bytes. The same size applies regardless of whether its physical
  3737. or virtual address is being used.
  3738. @item @code{-work-area-phys} @var{address} -- set the work area
  3739. base @var{address} to be used when no MMU is active.
  3740. @item @code{-work-area-virt} @var{address} -- set the work area
  3741. base @var{address} to be used when an MMU is active.
  3742. @emph{Do not specify a value for this except on targets with an MMU.}
  3743. The value should normally correspond to a static mapping for the
  3744. @code{-work-area-phys} address, set up by the current operating system.
  3745. @anchor{rtostype}
  3746. @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
  3747. @var{rtos_type} can be one of @option{auto}, @option{eCos},
  3748. @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
  3749. @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
  3750. @xref{gdbrtossupport,,RTOS Support}.
  3751. @item @code{-defer-examine} -- skip target examination at initial JTAG chain
  3752. scan and after a reset. A manual call to arp_examine is required to
  3753. access the target for debugging.
  3754. @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
  3755. @var{ap_number} is the numeric index of the DAP AP the target is connected to.
  3756. Use this option with systems where multiple, independent cores are connected
  3757. to separate access ports of the same DAP.
  3758. @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
  3759. to the target. Currently, only the @code{aarch64} target makes use of this option,
  3760. where it is a mandatory configuration for the target run control.
  3761. @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
  3762. for instruction on how to declare and control a CTI instance.
  3763. @anchor{gdbportoverride}
  3764. @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
  3765. possible values of the parameter @var{number}, which are not only numeric values.
  3766. Use this option to override, for this target only, the global parameter set with
  3767. command @command{gdb_port}.
  3768. @xref{gdb_port,,command gdb_port}.
  3769. @end itemize
  3770. @end deffn
  3771. @section Other $target_name Commands
  3772. @cindex object command
  3773. The Tcl/Tk language has the concept of object commands,
  3774. and OpenOCD adopts that same model for targets.
  3775. A good Tk example is a on screen button.
  3776. Once a button is created a button
  3777. has a name (a path in Tk terms) and that name is useable as a first
  3778. class command. For example in Tk, one can create a button and later
  3779. configure it like this:
  3780. @example
  3781. # Create
  3782. button .foobar -background red -command @{ foo @}
  3783. # Modify
  3784. .foobar configure -foreground blue
  3785. # Query
  3786. set x [.foobar cget -background]
  3787. # Report
  3788. puts [format "The button is %s" $x]
  3789. @end example
  3790. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  3791. button, and its object commands are invoked the same way.
  3792. @example
  3793. str912.cpu mww 0x1234 0x42
  3794. omap3530.cpu mww 0x5555 123
  3795. @end example
  3796. The commands supported by OpenOCD target objects are:
  3797. @deffn Command {$target_name arp_examine} @option{allow-defer}
  3798. @deffnx Command {$target_name arp_halt}
  3799. @deffnx Command {$target_name arp_poll}
  3800. @deffnx Command {$target_name arp_reset}
  3801. @deffnx Command {$target_name arp_waitstate}
  3802. Internal OpenOCD scripts (most notably @file{startup.tcl})
  3803. use these to deal with specific reset cases.
  3804. They are not otherwise documented here.
  3805. @end deffn
  3806. @deffn Command {$target_name array2mem} arrayname width address count
  3807. @deffnx Command {$target_name mem2array} arrayname width address count
  3808. These provide an efficient script-oriented interface to memory.
  3809. The @code{array2mem} primitive writes bytes, halfwords, or words;
  3810. while @code{mem2array} reads them.
  3811. In both cases, the TCL side uses an array, and
  3812. the target side uses raw memory.
  3813. The efficiency comes from enabling the use of
  3814. bulk JTAG data transfer operations.
  3815. The script orientation comes from working with data
  3816. values that are packaged for use by TCL scripts;
  3817. @command{mdw} type primitives only print data they retrieve,
  3818. and neither store nor return those values.
  3819. @itemize
  3820. @item @var{arrayname} ... is the name of an array variable
  3821. @item @var{width} ... is 8/16/32 - indicating the memory access size
  3822. @item @var{address} ... is the target memory address
  3823. @item @var{count} ... is the number of elements to process
  3824. @end itemize
  3825. @end deffn
  3826. @deffn Command {$target_name cget} queryparm
  3827. Each configuration parameter accepted by
  3828. @command{$target_name configure}
  3829. can be individually queried, to return its current value.
  3830. The @var{queryparm} is a parameter name
  3831. accepted by that command, such as @code{-work-area-phys}.
  3832. There are a few special cases:
  3833. @itemize @bullet
  3834. @item @code{-event} @var{event_name} -- returns the handler for the
  3835. event named @var{event_name}.
  3836. This is a special case because setting a handler requires
  3837. two parameters.
  3838. @item @code{-type} -- returns the target type.
  3839. This is a special case because this is set using
  3840. @command{target create} and can't be changed
  3841. using @command{$target_name configure}.
  3842. @end itemize
  3843. For example, if you wanted to summarize information about
  3844. all the targets you might use something like this:
  3845. @example
  3846. foreach name [target names] @{
  3847. set y [$name cget -endian]
  3848. set z [$name cget -type]
  3849. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  3850. $x $name $y $z]
  3851. @}
  3852. @end example
  3853. @end deffn
  3854. @anchor{targetcurstate}
  3855. @deffn Command {$target_name curstate}
  3856. Displays the current target state:
  3857. @code{debug-running},
  3858. @code{halted},
  3859. @code{reset},
  3860. @code{running}, or @code{unknown}.
  3861. (Also, @pxref{eventpolling,,Event Polling}.)
  3862. @end deffn
  3863. @deffn Command {$target_name eventlist}
  3864. Displays a table listing all event handlers
  3865. currently associated with this target.
  3866. @xref{targetevents,,Target Events}.
  3867. @end deffn
  3868. @deffn Command {$target_name invoke-event} event_name
  3869. Invokes the handler for the event named @var{event_name}.
  3870. (This is primarily intended for use by OpenOCD framework
  3871. code, for example by the reset code in @file{startup.tcl}.)
  3872. @end deffn
  3873. @deffn Command {$target_name mdw} addr [count]
  3874. @deffnx Command {$target_name mdh} addr [count]
  3875. @deffnx Command {$target_name mdb} addr [count]
  3876. Display contents of address @var{addr}, as
  3877. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  3878. or 8-bit bytes (@command{mdb}).
  3879. If @var{count} is specified, displays that many units.
  3880. (If you want to manipulate the data instead of displaying it,
  3881. see the @code{mem2array} primitives.)
  3882. @end deffn
  3883. @deffn Command {$target_name mww} addr word
  3884. @deffnx Command {$target_name mwh} addr halfword
  3885. @deffnx Command {$target_name mwb} addr byte
  3886. Writes the specified @var{word} (32 bits),
  3887. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3888. at the specified address @var{addr}.
  3889. @end deffn
  3890. @anchor{targetevents}
  3891. @section Target Events
  3892. @cindex target events
  3893. @cindex events
  3894. At various times, certain things can happen, or you want them to happen.
  3895. For example:
  3896. @itemize @bullet
  3897. @item What should happen when GDB connects? Should your target reset?
  3898. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  3899. @item Is using SRST appropriate (and possible) on your system?
  3900. Or instead of that, do you need to issue JTAG commands to trigger reset?
  3901. SRST usually resets everything on the scan chain, which can be inappropriate.
  3902. @item During reset, do you need to write to certain memory locations
  3903. to set up system clocks or
  3904. to reconfigure the SDRAM?
  3905. How about configuring the watchdog timer, or other peripherals,
  3906. to stop running while you hold the core stopped for debugging?
  3907. @end itemize
  3908. All of the above items can be addressed by target event handlers.
  3909. These are set up by @command{$target_name configure -event} or
  3910. @command{target create ... -event}.
  3911. The programmer's model matches the @code{-command} option used in Tcl/Tk
  3912. buttons and events. The two examples below act the same, but one creates
  3913. and invokes a small procedure while the other inlines it.
  3914. @example
  3915. proc my_init_proc @{ @} @{
  3916. echo "Disabling watchdog..."
  3917. mww 0xfffffd44 0x00008000
  3918. @}
  3919. mychip.cpu configure -event reset-init my_init_proc
  3920. mychip.cpu configure -event reset-init @{
  3921. echo "Disabling watchdog..."
  3922. mww 0xfffffd44 0x00008000
  3923. @}
  3924. @end example
  3925. The following target events are defined:
  3926. @itemize @bullet
  3927. @item @b{debug-halted}
  3928. @* The target has halted for debug reasons (i.e.: breakpoint)
  3929. @item @b{debug-resumed}
  3930. @* The target has resumed (i.e.: GDB said run)
  3931. @item @b{early-halted}
  3932. @* Occurs early in the halt process
  3933. @item @b{examine-start}
  3934. @* Before target examine is called.
  3935. @item @b{examine-end}
  3936. @* After target examine is called with no errors.
  3937. @item @b{gdb-attach}
  3938. @* When GDB connects. Issued before any GDB communication with the target
  3939. starts. GDB expects the target is halted during attachment.
  3940. @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
  3941. connect GDB to running target.
  3942. The event can be also used to set up the target so it is possible to probe flash.
  3943. Probing flash is necessary during GDB connect if you want to use
  3944. @pxref{programmingusinggdb,,programming using GDB}.
  3945. Another use of the flash memory map is for GDB to automatically choose
  3946. hardware or software breakpoints depending on whether the breakpoint
  3947. is in RAM or read only memory.
  3948. Default is @code{halt}
  3949. @item @b{gdb-detach}
  3950. @* When GDB disconnects
  3951. @item @b{gdb-end}
  3952. @* When the target has halted and GDB is not doing anything (see early halt)
  3953. @item @b{gdb-flash-erase-start}
  3954. @* Before the GDB flash process tries to erase the flash (default is
  3955. @code{reset init})
  3956. @item @b{gdb-flash-erase-end}
  3957. @* After the GDB flash process has finished erasing the flash
  3958. @item @b{gdb-flash-write-start}
  3959. @* Before GDB writes to the flash
  3960. @item @b{gdb-flash-write-end}
  3961. @* After GDB writes to the flash (default is @code{reset halt})
  3962. @item @b{gdb-start}
  3963. @* Before the target steps, GDB is trying to start/resume the target
  3964. @item @b{halted}
  3965. @* The target has halted
  3966. @item @b{reset-assert-pre}
  3967. @* Issued as part of @command{reset} processing
  3968. after @command{reset-start} was triggered
  3969. but before either SRST alone is asserted on the scan chain,
  3970. or @code{reset-assert} is triggered.
  3971. @item @b{reset-assert}
  3972. @* Issued as part of @command{reset} processing
  3973. after @command{reset-assert-pre} was triggered.
  3974. When such a handler is present, cores which support this event will use
  3975. it instead of asserting SRST.
  3976. This support is essential for debugging with JTAG interfaces which
  3977. don't include an SRST line (JTAG doesn't require SRST), and for
  3978. selective reset on scan chains that have multiple targets.
  3979. @item @b{reset-assert-post}
  3980. @* Issued as part of @command{reset} processing
  3981. after @code{reset-assert} has been triggered.
  3982. or the target asserted SRST on the entire scan chain.
  3983. @item @b{reset-deassert-pre}
  3984. @* Issued as part of @command{reset} processing
  3985. after @code{reset-assert-post} has been triggered.
  3986. @item @b{reset-deassert-post}
  3987. @* Issued as part of @command{reset} processing
  3988. after @code{reset-deassert-pre} has been triggered
  3989. and (if the target is using it) after SRST has been
  3990. released on the scan chain.
  3991. @item @b{reset-end}
  3992. @* Issued as the final step in @command{reset} processing.
  3993. @item @b{reset-init}
  3994. @* Used by @b{reset init} command for board-specific initialization.
  3995. This event fires after @emph{reset-deassert-post}.
  3996. This is where you would configure PLLs and clocking, set up DRAM so
  3997. you can download programs that don't fit in on-chip SRAM, set up pin
  3998. multiplexing, and so on.
  3999. (You may be able to switch to a fast JTAG clock rate here, after
  4000. the target clocks are fully set up.)
  4001. @item @b{reset-start}
  4002. @* Issued as the first step in @command{reset} processing
  4003. before @command{reset-assert-pre} is called.
  4004. This is the most robust place to use @command{jtag_rclk}
  4005. or @command{adapter_khz} to switch to a low JTAG clock rate,
  4006. when reset disables PLLs needed to use a fast clock.
  4007. @item @b{resume-start}
  4008. @* Before any target is resumed
  4009. @item @b{resume-end}
  4010. @* After all targets have resumed
  4011. @item @b{resumed}
  4012. @* Target has resumed
  4013. @item @b{trace-config}
  4014. @* After target hardware trace configuration was changed
  4015. @end itemize
  4016. @node Flash Commands
  4017. @chapter Flash Commands
  4018. OpenOCD has different commands for NOR and NAND flash;
  4019. the ``flash'' command works with NOR flash, while
  4020. the ``nand'' command works with NAND flash.
  4021. This partially reflects different hardware technologies:
  4022. NOR flash usually supports direct CPU instruction and data bus access,
  4023. while data from a NAND flash must be copied to memory before it can be
  4024. used. (SPI flash must also be copied to memory before use.)
  4025. However, the documentation also uses ``flash'' as a generic term;
  4026. for example, ``Put flash configuration in board-specific files''.
  4027. Flash Steps:
  4028. @enumerate
  4029. @item Configure via the command @command{flash bank}
  4030. @* Do this in a board-specific configuration file,
  4031. passing parameters as needed by the driver.
  4032. @item Operate on the flash via @command{flash subcommand}
  4033. @* Often commands to manipulate the flash are typed by a human, or run
  4034. via a script in some automated way. Common tasks include writing a
  4035. boot loader, operating system, or other data.
  4036. @item GDB Flashing
  4037. @* Flashing via GDB requires the flash be configured via ``flash
  4038. bank'', and the GDB flash features be enabled.
  4039. @xref{gdbconfiguration,,GDB Configuration}.
  4040. @end enumerate
  4041. Many CPUs have the ability to ``boot'' from the first flash bank.
  4042. This means that misprogramming that bank can ``brick'' a system,
  4043. so that it can't boot.
  4044. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  4045. board by (re)installing working boot firmware.
  4046. @anchor{norconfiguration}
  4047. @section Flash Configuration Commands
  4048. @cindex flash configuration
  4049. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  4050. Configures a flash bank which provides persistent storage
  4051. for addresses from @math{base} to @math{base + size - 1}.
  4052. These banks will often be visible to GDB through the target's memory map.
  4053. In some cases, configuring a flash bank will activate extra commands;
  4054. see the driver-specific documentation.
  4055. @itemize @bullet
  4056. @item @var{name} ... may be used to reference the flash bank
  4057. in other flash commands. A number is also available.
  4058. @item @var{driver} ... identifies the controller driver
  4059. associated with the flash bank being declared.
  4060. This is usually @code{cfi} for external flash, or else
  4061. the name of a microcontroller with embedded flash memory.
  4062. @xref{flashdriverlist,,Flash Driver List}.
  4063. @item @var{base} ... Base address of the flash chip.
  4064. @item @var{size} ... Size of the chip, in bytes.
  4065. For some drivers, this value is detected from the hardware.
  4066. @item @var{chip_width} ... Width of the flash chip, in bytes;
  4067. ignored for most microcontroller drivers.
  4068. @item @var{bus_width} ... Width of the data bus used to access the
  4069. chip, in bytes; ignored for most microcontroller drivers.
  4070. @item @var{target} ... Names the target used to issue
  4071. commands to the flash controller.
  4072. @comment Actually, it's currently a controller-specific parameter...
  4073. @item @var{driver_options} ... drivers may support, or require,
  4074. additional parameters. See the driver-specific documentation
  4075. for more information.
  4076. @end itemize
  4077. @quotation Note
  4078. This command is not available after OpenOCD initialization has completed.
  4079. Use it in board specific configuration files, not interactively.
  4080. @end quotation
  4081. @end deffn
  4082. @comment the REAL name for this command is "ocd_flash_banks"
  4083. @comment less confusing would be: "flash list" (like "nand list")
  4084. @deffn Command {flash banks}
  4085. Prints a one-line summary of each device that was
  4086. declared using @command{flash bank}, numbered from zero.
  4087. Note that this is the @emph{plural} form;
  4088. the @emph{singular} form is a very different command.
  4089. @end deffn
  4090. @deffn Command {flash list}
  4091. Retrieves a list of associative arrays for each device that was
  4092. declared using @command{flash bank}, numbered from zero.
  4093. This returned list can be manipulated easily from within scripts.
  4094. @end deffn
  4095. @deffn Command {flash probe} num
  4096. Identify the flash, or validate the parameters of the configured flash. Operation
  4097. depends on the flash type.
  4098. The @var{num} parameter is a value shown by @command{flash banks}.
  4099. Most flash commands will implicitly @emph{autoprobe} the bank;
  4100. flash drivers can distinguish between probing and autoprobing,
  4101. but most don't bother.
  4102. @end deffn
  4103. @section Erasing, Reading, Writing to Flash
  4104. @cindex flash erasing
  4105. @cindex flash reading
  4106. @cindex flash writing
  4107. @cindex flash programming
  4108. @anchor{flashprogrammingcommands}
  4109. One feature distinguishing NOR flash from NAND or serial flash technologies
  4110. is that for read access, it acts exactly like any other addressable memory.
  4111. This means you can use normal memory read commands like @command{mdw} or
  4112. @command{dump_image} with it, with no special @command{flash} subcommands.
  4113. @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
  4114. Write access works differently. Flash memory normally needs to be erased
  4115. before it's written. Erasing a sector turns all of its bits to ones, and
  4116. writing can turn ones into zeroes. This is why there are special commands
  4117. for interactive erasing and writing, and why GDB needs to know which parts
  4118. of the address space hold NOR flash memory.
  4119. @quotation Note
  4120. Most of these erase and write commands leverage the fact that NOR flash
  4121. chips consume target address space. They implicitly refer to the current
  4122. JTAG target, and map from an address in that target's address space
  4123. back to a flash bank.
  4124. @comment In May 2009, those mappings may fail if any bank associated
  4125. @comment with that target doesn't successfully autoprobe ... bug worth fixing?
  4126. A few commands use abstract addressing based on bank and sector numbers,
  4127. and don't depend on searching the current target and its address space.
  4128. Avoid confusing the two command models.
  4129. @end quotation
  4130. Some flash chips implement software protection against accidental writes,
  4131. since such buggy writes could in some cases ``brick'' a system.
  4132. For such systems, erasing and writing may require sector protection to be
  4133. disabled first.
  4134. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  4135. and AT91SAM7 on-chip flash.
  4136. @xref{flashprotect,,flash protect}.
  4137. @deffn Command {flash erase_sector} num first last
  4138. Erase sectors in bank @var{num}, starting at sector @var{first}
  4139. up to and including @var{last}.
  4140. Sector numbering starts at 0.
  4141. Providing a @var{last} sector of @option{last}
  4142. specifies "to the end of the flash bank".
  4143. The @var{num} parameter is a value shown by @command{flash banks}.
  4144. @end deffn
  4145. @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
  4146. Erase sectors starting at @var{address} for @var{length} bytes.
  4147. Unless @option{pad} is specified, @math{address} must begin a
  4148. flash sector, and @math{address + length - 1} must end a sector.
  4149. Specifying @option{pad} erases extra data at the beginning and/or
  4150. end of the specified region, as needed to erase only full sectors.
  4151. The flash bank to use is inferred from the @var{address}, and
  4152. the specified length must stay within that bank.
  4153. As a special case, when @var{length} is zero and @var{address} is
  4154. the start of the bank, the whole flash is erased.
  4155. If @option{unlock} is specified, then the flash is unprotected
  4156. before erase starts.
  4157. @end deffn
  4158. @deffn Command {flash fillw} address word length
  4159. @deffnx Command {flash fillh} address halfword length
  4160. @deffnx Command {flash fillb} address byte length
  4161. Fills flash memory with the specified @var{word} (32 bits),
  4162. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4163. starting at @var{address} and continuing
  4164. for @var{length} units (word/halfword/byte).
  4165. No erasure is done before writing; when needed, that must be done
  4166. before issuing this command.
  4167. Writes are done in blocks of up to 1024 bytes, and each write is
  4168. verified by reading back the data and comparing it to what was written.
  4169. The flash bank to use is inferred from the @var{address} of
  4170. each block, and the specified length must stay within that bank.
  4171. @end deffn
  4172. @comment no current checks for errors if fill blocks touch multiple banks!
  4173. @deffn Command {flash write_bank} num filename [offset]
  4174. Write the binary @file{filename} to flash bank @var{num},
  4175. starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
  4176. is omitted, start at the beginning of the flash bank.
  4177. The @var{num} parameter is a value shown by @command{flash banks}.
  4178. @end deffn
  4179. @deffn Command {flash read_bank} num filename [offset [length]]
  4180. Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
  4181. and write the contents to the binary @file{filename}. If @var{offset} is
  4182. omitted, start at the beginning of the flash bank. If @var{length} is omitted,
  4183. read the remaining bytes from the flash bank.
  4184. The @var{num} parameter is a value shown by @command{flash banks}.
  4185. @end deffn
  4186. @deffn Command {flash verify_bank} num filename [offset]
  4187. Compare the contents of the binary file @var{filename} with the contents of the
  4188. flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
  4189. start at the beginning of the flash bank. Fail if the contents do not match.
  4190. The @var{num} parameter is a value shown by @command{flash banks}.
  4191. @end deffn
  4192. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  4193. Write the image @file{filename} to the current target's flash bank(s).
  4194. Only loadable sections from the image are written.
  4195. A relocation @var{offset} may be specified, in which case it is added
  4196. to the base address for each section in the image.
  4197. The file [@var{type}] can be specified
  4198. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  4199. @option{elf} (ELF file), @option{s19} (Motorola s19).
  4200. @option{mem}, or @option{builder}.
  4201. The relevant flash sectors will be erased prior to programming
  4202. if the @option{erase} parameter is given. If @option{unlock} is
  4203. provided, then the flash banks are unlocked before erase and
  4204. program. The flash bank to use is inferred from the address of
  4205. each image section.
  4206. @quotation Warning
  4207. Be careful using the @option{erase} flag when the flash is holding
  4208. data you want to preserve.
  4209. Portions of the flash outside those described in the image's
  4210. sections might be erased with no notice.
  4211. @itemize
  4212. @item
  4213. When a section of the image being written does not fill out all the
  4214. sectors it uses, the unwritten parts of those sectors are necessarily
  4215. also erased, because sectors can't be partially erased.
  4216. @item
  4217. Data stored in sector "holes" between image sections are also affected.
  4218. For example, "@command{flash write_image erase ...}" of an image with
  4219. one byte at the beginning of a flash bank and one byte at the end
  4220. erases the entire bank -- not just the two sectors being written.
  4221. @end itemize
  4222. Also, when flash protection is important, you must re-apply it after
  4223. it has been removed by the @option{unlock} flag.
  4224. @end quotation
  4225. @end deffn
  4226. @section Other Flash commands
  4227. @cindex flash protection
  4228. @deffn Command {flash erase_check} num
  4229. Check erase state of sectors in flash bank @var{num},
  4230. and display that status.
  4231. The @var{num} parameter is a value shown by @command{flash banks}.
  4232. @end deffn
  4233. @deffn Command {flash info} num [sectors]
  4234. Print info about flash bank @var{num}, a list of protection blocks
  4235. and their status. Use @option{sectors} to show a list of sectors instead.
  4236. The @var{num} parameter is a value shown by @command{flash banks}.
  4237. This command will first query the hardware, it does not print cached
  4238. and possibly stale information.
  4239. @end deffn
  4240. @anchor{flashprotect}
  4241. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  4242. Enable (@option{on}) or disable (@option{off}) protection of flash blocks
  4243. in flash bank @var{num}, starting at protection block @var{first}
  4244. and continuing up to and including @var{last}.
  4245. Providing a @var{last} block of @option{last}
  4246. specifies "to the end of the flash bank".
  4247. The @var{num} parameter is a value shown by @command{flash banks}.
  4248. The protection block is usually identical to a flash sector.
  4249. Some devices may utilize a protection block distinct from flash sector.
  4250. See @command{flash info} for a list of protection blocks.
  4251. @end deffn
  4252. @deffn Command {flash padded_value} num value
  4253. Sets the default value used for padding any image sections, This should
  4254. normally match the flash bank erased value. If not specified by this
  4255. command or the flash driver then it defaults to 0xff.
  4256. @end deffn
  4257. @anchor{program}
  4258. @deffn Command {program} filename [verify] [reset] [exit] [offset]
  4259. This is a helper script that simplifies using OpenOCD as a standalone
  4260. programmer. The only required parameter is @option{filename}, the others are optional.
  4261. @xref{Flash Programming}.
  4262. @end deffn
  4263. @anchor{flashdriverlist}
  4264. @section Flash Driver List
  4265. As noted above, the @command{flash bank} command requires a driver name,
  4266. and allows driver-specific options and behaviors.
  4267. Some drivers also activate driver-specific commands.
  4268. @deffn {Flash Driver} virtual
  4269. This is a special driver that maps a previously defined bank to another
  4270. address. All bank settings will be copied from the master physical bank.
  4271. The @var{virtual} driver defines one mandatory parameters,
  4272. @itemize
  4273. @item @var{master_bank} The bank that this virtual address refers to.
  4274. @end itemize
  4275. So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
  4276. the flash bank defined at address 0x1fc00000. Any command executed on
  4277. the virtual banks is actually performed on the physical banks.
  4278. @example
  4279. flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4280. flash bank vbank0 virtual 0xbfc00000 0 0 0 \
  4281. $_TARGETNAME $_FLASHNAME
  4282. flash bank vbank1 virtual 0x9fc00000 0 0 0 \
  4283. $_TARGETNAME $_FLASHNAME
  4284. @end example
  4285. @end deffn
  4286. @subsection External Flash
  4287. @deffn {Flash Driver} cfi
  4288. @cindex Common Flash Interface
  4289. @cindex CFI
  4290. The ``Common Flash Interface'' (CFI) is the main standard for
  4291. external NOR flash chips, each of which connects to a
  4292. specific external chip select on the CPU.
  4293. Frequently the first such chip is used to boot the system.
  4294. Your board's @code{reset-init} handler might need to
  4295. configure additional chip selects using other commands (like: @command{mww} to
  4296. configure a bus and its timings), or
  4297. perhaps configure a GPIO pin that controls the ``write protect'' pin
  4298. on the flash chip.
  4299. The CFI driver can use a target-specific working area to significantly
  4300. speed up operation.
  4301. The CFI driver can accept the following optional parameters, in any order:
  4302. @itemize
  4303. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  4304. like AM29LV010 and similar types.
  4305. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  4306. @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
  4307. @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
  4308. swapped when writing data values (i.e. not CFI commands).
  4309. @end itemize
  4310. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  4311. wide on a sixteen bit bus:
  4312. @example
  4313. flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  4314. flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  4315. @end example
  4316. To configure one bank of 32 MBytes
  4317. built from two sixteen bit (two byte) wide parts wired in parallel
  4318. to create a thirty-two bit (four byte) bus with doubled throughput:
  4319. @example
  4320. flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  4321. @end example
  4322. @c "cfi part_id" disabled
  4323. @end deffn
  4324. @deffn {Flash Driver} jtagspi
  4325. @cindex Generic JTAG2SPI driver
  4326. @cindex SPI
  4327. @cindex jtagspi
  4328. @cindex bscan_spi
  4329. Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
  4330. SPI flash connected to them. To access this flash from the host, the device
  4331. is first programmed with a special proxy bitstream that
  4332. exposes the SPI flash on the device's JTAG interface. The flash can then be
  4333. accessed through JTAG.
  4334. Since signaling between JTAG and SPI is compatible, all that is required for
  4335. a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
  4336. the flash chip select when the JTAG state machine is in SHIFT-DR. Such
  4337. a bitstream for several Xilinx FPGAs can be found in
  4338. @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
  4339. @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
  4340. This flash bank driver requires a target on a JTAG tap and will access that
  4341. tap directly. Since no support from the target is needed, the target can be a
  4342. "testee" dummy. Since the target does not expose the flash memory
  4343. mapping, target commands that would otherwise be expected to access the flash
  4344. will not work. These include all @command{*_image} and
  4345. @command{$target_name m*} commands as well as @command{program}. Equivalent
  4346. functionality is available through the @command{flash write_bank},
  4347. @command{flash read_bank}, and @command{flash verify_bank} commands.
  4348. @itemize
  4349. @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
  4350. For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
  4351. @var{USER1} instruction.
  4352. @end itemize
  4353. @example
  4354. target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
  4355. set _XILINX_USER1 0x02
  4356. flash bank $_FLASHNAME spi 0x0 0 0 0 \
  4357. $_TARGETNAME $_XILINX_USER1
  4358. @end example
  4359. @end deffn
  4360. @deffn {Flash Driver} xcf
  4361. @cindex Xilinx Platform flash driver
  4362. @cindex xcf
  4363. Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
  4364. It is (almost) regular NOR flash with erase sectors, program pages, etc. The
  4365. only difference is special registers controlling its FPGA specific behavior.
  4366. They must be properly configured for successful FPGA loading using
  4367. additional @var{xcf} driver command:
  4368. @deffn Command {xcf ccb} <bank_id>
  4369. command accepts additional parameters:
  4370. @itemize
  4371. @item @var{external|internal} ... selects clock source.
  4372. @item @var{serial|parallel} ... selects serial or parallel data bus mode.
  4373. @item @var{slave|master} ... selects slave of master mode for flash device.
  4374. @item @var{40|20} ... selects clock frequency in MHz for internal clock
  4375. in master mode.
  4376. @end itemize
  4377. @example
  4378. xcf ccb 0 external parallel slave 40
  4379. @end example
  4380. All of them must be specified even if clock frequency is pointless
  4381. in slave mode. If only bank id specified than command prints current
  4382. CCB register value. Note: there is no need to write this register
  4383. every time you erase/program data sectors because it stores in
  4384. dedicated sector.
  4385. @end deffn
  4386. @deffn Command {xcf configure} <bank_id>
  4387. Initiates FPGA loading procedure. Useful if your board has no "configure"
  4388. button.
  4389. @example
  4390. xcf configure 0
  4391. @end example
  4392. @end deffn
  4393. Additional driver notes:
  4394. @itemize
  4395. @item Only single revision supported.
  4396. @item Driver automatically detects need of bit reverse, but
  4397. only "bin" (raw binary, do not confuse it with "bit") and "mcs"
  4398. (Intel hex) file types supported.
  4399. @item For additional info check xapp972.pdf and ug380.pdf.
  4400. @end itemize
  4401. @end deffn
  4402. @deffn {Flash Driver} lpcspifi
  4403. @cindex NXP SPI Flash Interface
  4404. @cindex SPIFI
  4405. @cindex lpcspifi
  4406. NXP's LPC43xx and LPC18xx families include a proprietary SPI
  4407. Flash Interface (SPIFI) peripheral that can drive and provide
  4408. memory mapped access to external SPI flash devices.
  4409. The lpcspifi driver initializes this interface and provides
  4410. program and erase functionality for these serial flash devices.
  4411. Use of this driver @b{requires} a working area of at least 1kB
  4412. to be configured on the target device; more than this will
  4413. significantly reduce flash programming times.
  4414. The setup command only requires the @var{base} parameter. All
  4415. other parameters are ignored, and the flash size and layout
  4416. are configured by the driver.
  4417. @example
  4418. flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
  4419. @end example
  4420. @end deffn
  4421. @deffn {Flash Driver} stmsmi
  4422. @cindex STMicroelectronics Serial Memory Interface
  4423. @cindex SMI
  4424. @cindex stmsmi
  4425. Some devices from STMicroelectronics (e.g. STR75x MCU family,
  4426. SPEAr MPU family) include a proprietary
  4427. ``Serial Memory Interface'' (SMI) controller able to drive external
  4428. SPI flash devices.
  4429. Depending on specific device and board configuration, up to 4 external
  4430. flash devices can be connected.
  4431. SMI makes the flash content directly accessible in the CPU address
  4432. space; each external device is mapped in a memory bank.
  4433. CPU can directly read data, execute code and boot from SMI banks.
  4434. Normal OpenOCD commands like @command{mdw} can be used to display
  4435. the flash content.
  4436. The setup command only requires the @var{base} parameter in order
  4437. to identify the memory bank.
  4438. All other parameters are ignored. Additional information, like
  4439. flash size, are detected automatically.
  4440. @example
  4441. flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  4442. @end example
  4443. @end deffn
  4444. @deffn {Flash Driver} mrvlqspi
  4445. This driver supports QSPI flash controller of Marvell's Wireless
  4446. Microcontroller platform.
  4447. The flash size is autodetected based on the table of known JEDEC IDs
  4448. hardcoded in the OpenOCD sources.
  4449. @example
  4450. flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
  4451. @end example
  4452. @end deffn
  4453. @deffn {Flash Driver} ath79
  4454. @cindex Atheros ath79 SPI driver
  4455. @cindex ath79
  4456. Members of ATH79 SoC family from Atheros include a SPI interface with 3
  4457. chip selects.
  4458. On reset a SPI flash connected to the first chip select (CS0) is made
  4459. directly read-accessible in the CPU address space (up to 16MBytes)
  4460. and is usually used to store the bootloader and operating system.
  4461. Normal OpenOCD commands like @command{mdw} can be used to display
  4462. the flash content while it is in memory-mapped mode (only the first
  4463. 4MBytes are accessible without additional configuration on reset).
  4464. The setup command only requires the @var{base} parameter in order
  4465. to identify the memory bank. The actual value for the base address
  4466. is not otherwise used by the driver. However the mapping is passed
  4467. to gdb. Thus for the memory mapped flash (chipselect CS0) the base
  4468. address should be the actual memory mapped base address. For unmapped
  4469. chipselects (CS1 and CS2) care should be taken to use a base address
  4470. that does not overlap with real memory regions.
  4471. Additional information, like flash size, are detected automatically.
  4472. An optional additional parameter sets the chipselect for the bank,
  4473. with the default CS0.
  4474. CS1 and CS2 require additional GPIO setup before they can be used
  4475. since the alternate function must be enabled on the GPIO pin
  4476. CS1/CS2 is routed to on the given SoC.
  4477. @example
  4478. flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
  4479. # When using multiple chipselects the base should be different for each,
  4480. # otherwise the write_image command is not able to distinguish the
  4481. # banks.
  4482. flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
  4483. flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
  4484. flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
  4485. @end example
  4486. @end deffn
  4487. @deffn {Flash Driver} fespi
  4488. @cindex Freedom E SPI
  4489. @cindex fespi
  4490. SiFive's Freedom E SPI controller, used in HiFive and other boards.
  4491. @example
  4492. flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
  4493. @end example
  4494. @end deffn
  4495. @subsection Internal Flash (Microcontrollers)
  4496. @deffn {Flash Driver} aduc702x
  4497. The ADUC702x analog microcontrollers from Analog Devices
  4498. include internal flash and use ARM7TDMI cores.
  4499. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  4500. The setup command only requires the @var{target} argument
  4501. since all devices in this family have the same memory layout.
  4502. @example
  4503. flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
  4504. @end example
  4505. @end deffn
  4506. @deffn {Flash Driver} ambiqmicro
  4507. @cindex ambiqmicro
  4508. @cindex apollo
  4509. All members of the Apollo microcontroller family from
  4510. Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
  4511. The host connects over USB to an FTDI interface that communicates
  4512. with the target using SWD.
  4513. The @var{ambiqmicro} driver reads the Chip Information Register detect
  4514. the device class of the MCU.
  4515. The Flash and SRAM sizes directly follow device class, and are used
  4516. to set up the flash banks.
  4517. If this fails, the driver will use default values set to the minimum
  4518. sizes of an Apollo chip.
  4519. All Apollo chips have two flash banks of the same size.
  4520. In all cases the first flash bank starts at location 0,
  4521. and the second bank starts after the first.
  4522. @example
  4523. # Flash bank 0
  4524. flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
  4525. # Flash bank 1 - same size as bank0, starts after bank 0.
  4526. flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
  4527. $_TARGETNAME
  4528. @end example
  4529. Flash is programmed using custom entry points into the bootloader.
  4530. This is the only way to program the flash as no flash control registers
  4531. are available to the user.
  4532. The @var{ambiqmicro} driver adds some additional commands:
  4533. @deffn Command {ambiqmicro mass_erase} <bank>
  4534. Erase entire bank.
  4535. @end deffn
  4536. @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
  4537. Erase device pages.
  4538. @end deffn
  4539. @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
  4540. Program OTP is a one time operation to create write protected flash.
  4541. The user writes sectors to SRAM starting at 0x10000010.
  4542. Program OTP will write these sectors from SRAM to flash, and write protect
  4543. the flash.
  4544. @end deffn
  4545. @end deffn
  4546. @anchor{at91samd}
  4547. @deffn {Flash Driver} at91samd
  4548. @cindex at91samd
  4549. All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
  4550. families from Atmel include internal flash and use ARM's Cortex-M0+ core.
  4551. This driver uses the same command names/syntax as @xref{at91sam3}.
  4552. @deffn Command {at91samd chip-erase}
  4553. Issues a complete Flash erase via the Device Service Unit (DSU). This can be
  4554. used to erase a chip back to its factory state and does not require the
  4555. processor to be halted.
  4556. @end deffn
  4557. @deffn Command {at91samd set-security}
  4558. Secures the Flash via the Set Security Bit (SSB) command. This prevents access
  4559. to the Flash and can only be undone by using the chip-erase command which
  4560. erases the Flash contents and turns off the security bit. Warning: at this
  4561. time, openocd will not be able to communicate with a secured chip and it is
  4562. therefore not possible to chip-erase it without using another tool.
  4563. @example
  4564. at91samd set-security enable
  4565. @end example
  4566. @end deffn
  4567. @deffn Command {at91samd eeprom}
  4568. Shows or sets the EEPROM emulation size configuration, stored in the User Row
  4569. of the Flash. When setting, the EEPROM size must be specified in bytes and it
  4570. must be one of the permitted sizes according to the datasheet. Settings are
  4571. written immediately but only take effect on MCU reset. EEPROM emulation
  4572. requires additional firmware support and the minimum EEPROM size may not be
  4573. the same as the minimum that the hardware supports. Set the EEPROM size to 0
  4574. in order to disable this feature.
  4575. @example
  4576. at91samd eeprom
  4577. at91samd eeprom 1024
  4578. @end example
  4579. @end deffn
  4580. @deffn Command {at91samd bootloader}
  4581. Shows or sets the bootloader size configuration, stored in the User Row of the
  4582. Flash. This is called the BOOTPROT region. When setting, the bootloader size
  4583. must be specified in bytes and it must be one of the permitted sizes according
  4584. to the datasheet. Settings are written immediately but only take effect on
  4585. MCU reset. Setting the bootloader size to 0 disables bootloader protection.
  4586. @example
  4587. at91samd bootloader
  4588. at91samd bootloader 16384
  4589. @end example
  4590. @end deffn
  4591. @deffn Command {at91samd dsu_reset_deassert}
  4592. This command releases internal reset held by DSU
  4593. and prepares reset vector catch in case of reset halt.
  4594. Command is used internally in event event reset-deassert-post.
  4595. @end deffn
  4596. @deffn Command {at91samd nvmuserrow}
  4597. Writes or reads the entire 64 bit wide NVM user row register which is located at
  4598. 0x804000. This register includes various fuses lock-bits and factory calibration
  4599. data. Reading the register is done by invoking this command without any
  4600. arguments. Writing is possible by giving 1 or 2 hex values. The first argument
  4601. is the register value to be written and the second one is an optional changemask.
  4602. Every bit which value in changemask is 0 will stay unchanged. The lock- and
  4603. reserved-bits are masked out and cannot be changed.
  4604. @example
  4605. # Read user row
  4606. >at91samd nvmuserrow
  4607. NVMUSERROW: 0xFFFFFC5DD8E0C788
  4608. # Write 0xFFFFFC5DD8E0C788 to user row
  4609. >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
  4610. # Write 0x12300 to user row but leave other bits and low byte unchanged
  4611. >at91samd nvmuserrow 0x12345 0xFFF00
  4612. @end example
  4613. @end deffn
  4614. @end deffn
  4615. @anchor{at91sam3}
  4616. @deffn {Flash Driver} at91sam3
  4617. @cindex at91sam3
  4618. All members of the AT91SAM3 microcontroller family from
  4619. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  4620. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  4621. that the driver was orginaly developed and tested using the
  4622. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  4623. the family was cribbed from the data sheet. @emph{Note to future
  4624. readers/updaters: Please remove this worrisome comment after other
  4625. chips are confirmed.}
  4626. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  4627. have one flash bank. In all cases the flash banks are at
  4628. the following fixed locations:
  4629. @example
  4630. # Flash bank 0 - all chips
  4631. flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
  4632. # Flash bank 1 - only 256K chips
  4633. flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
  4634. @end example
  4635. Internally, the AT91SAM3 flash memory is organized as follows.
  4636. Unlike the AT91SAM7 chips, these are not used as parameters
  4637. to the @command{flash bank} command:
  4638. @itemize
  4639. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  4640. @item @emph{Bank Size:} 128K/64K Per flash bank
  4641. @item @emph{Sectors:} 16 or 8 per bank
  4642. @item @emph{SectorSize:} 8K Per Sector
  4643. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  4644. @end itemize
  4645. The AT91SAM3 driver adds some additional commands:
  4646. @deffn Command {at91sam3 gpnvm}
  4647. @deffnx Command {at91sam3 gpnvm clear} number
  4648. @deffnx Command {at91sam3 gpnvm set} number
  4649. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  4650. With no parameters, @command{show} or @command{show all},
  4651. shows the status of all GPNVM bits.
  4652. With @command{show} @var{number}, displays that bit.
  4653. With @command{set} @var{number} or @command{clear} @var{number},
  4654. modifies that GPNVM bit.
  4655. @end deffn
  4656. @deffn Command {at91sam3 info}
  4657. This command attempts to display information about the AT91SAM3
  4658. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  4659. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  4660. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  4661. various clock configuration registers and attempts to display how it
  4662. believes the chip is configured. By default, the SLOWCLK is assumed to
  4663. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  4664. @end deffn
  4665. @deffn Command {at91sam3 slowclk} [value]
  4666. This command shows/sets the slow clock frequency used in the
  4667. @command{at91sam3 info} command calculations above.
  4668. @end deffn
  4669. @end deffn
  4670. @deffn {Flash Driver} at91sam4
  4671. @cindex at91sam4
  4672. All members of the AT91SAM4 microcontroller family from
  4673. Atmel include internal flash and use ARM's Cortex-M4 core.
  4674. This driver uses the same command names/syntax as @xref{at91sam3}.
  4675. @end deffn
  4676. @deffn {Flash Driver} at91sam4l
  4677. @cindex at91sam4l
  4678. All members of the AT91SAM4L microcontroller family from
  4679. Atmel include internal flash and use ARM's Cortex-M4 core.
  4680. This driver uses the same command names/syntax as @xref{at91sam3}.
  4681. The AT91SAM4L driver adds some additional commands:
  4682. @deffn Command {at91sam4l smap_reset_deassert}
  4683. This command releases internal reset held by SMAP
  4684. and prepares reset vector catch in case of reset halt.
  4685. Command is used internally in event event reset-deassert-post.
  4686. @end deffn
  4687. @end deffn
  4688. @deffn {Flash Driver} atsamv
  4689. @cindex atsamv
  4690. All members of the ATSAMV, ATSAMS, and ATSAME families from
  4691. Atmel include internal flash and use ARM's Cortex-M7 core.
  4692. This driver uses the same command names/syntax as @xref{at91sam3}.
  4693. @end deffn
  4694. @deffn {Flash Driver} at91sam7
  4695. All members of the AT91SAM7 microcontroller family from Atmel include
  4696. internal flash and use ARM7TDMI cores. The driver automatically
  4697. recognizes a number of these chips using the chip identification
  4698. register, and autoconfigures itself.
  4699. @example
  4700. flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
  4701. @end example
  4702. For chips which are not recognized by the controller driver, you must
  4703. provide additional parameters in the following order:
  4704. @itemize
  4705. @item @var{chip_model} ... label used with @command{flash info}
  4706. @item @var{banks}
  4707. @item @var{sectors_per_bank}
  4708. @item @var{pages_per_sector}
  4709. @item @var{pages_size}
  4710. @item @var{num_nvm_bits}
  4711. @item @var{freq_khz} ... required if an external clock is provided,
  4712. optional (but recommended) when the oscillator frequency is known
  4713. @end itemize
  4714. It is recommended that you provide zeroes for all of those values
  4715. except the clock frequency, so that everything except that frequency
  4716. will be autoconfigured.
  4717. Knowing the frequency helps ensure correct timings for flash access.
  4718. The flash controller handles erases automatically on a page (128/256 byte)
  4719. basis, so explicit erase commands are not necessary for flash programming.
  4720. However, there is an ``EraseAll`` command that can erase an entire flash
  4721. plane (of up to 256KB), and it will be used automatically when you issue
  4722. @command{flash erase_sector} or @command{flash erase_address} commands.
  4723. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  4724. Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
  4725. bit for the processor. Each processor has a number of such bits,
  4726. used for controlling features such as brownout detection (so they
  4727. are not truly general purpose).
  4728. @quotation Note
  4729. This assumes that the first flash bank (number 0) is associated with
  4730. the appropriate at91sam7 target.
  4731. @end quotation
  4732. @end deffn
  4733. @end deffn
  4734. @deffn {Flash Driver} avr
  4735. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  4736. @emph{The current implementation is incomplete.}
  4737. @comment - defines mass_erase ... pointless given flash_erase_address
  4738. @end deffn
  4739. @deffn {Flash Driver} bluenrg-x
  4740. STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
  4741. The driver automatically recognizes these chips using
  4742. the chip identification registers, and autoconfigures itself.
  4743. @example
  4744. flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
  4745. @end example
  4746. Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
  4747. each single sector one by one.
  4748. @example
  4749. flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
  4750. @end example
  4751. @example
  4752. flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
  4753. @end example
  4754. Triggering a mass erase is also useful when users want to disable readout protection.
  4755. @end deffn
  4756. @deffn {Flash Driver} cc26xx
  4757. All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
  4758. Instruments include internal flash. The cc26xx flash driver supports both the
  4759. CC13xx and CC26xx family of devices. The driver automatically recognizes the
  4760. specific version's flash parameters and autoconfigures itself. The flash bank
  4761. starts at address 0.
  4762. @example
  4763. flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
  4764. @end example
  4765. @end deffn
  4766. @deffn {Flash Driver} cc3220sf
  4767. The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
  4768. Instruments includes 1MB of internal flash. The cc3220sf flash driver only
  4769. supports the internal flash. The serial flash on SimpleLink boards is
  4770. programmed via the bootloader over a UART connection. Security features of
  4771. the CC3220SF may erase the internal flash during power on reset. Refer to
  4772. documentation at @url{www.ti.com/cc3220sf} for details on security features
  4773. and programming the serial flash.
  4774. @example
  4775. flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
  4776. @end example
  4777. @end deffn
  4778. @deffn {Flash Driver} efm32
  4779. All members of the EFM32 microcontroller family from Energy Micro include
  4780. internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
  4781. a number of these chips using the chip identification register, and
  4782. autoconfigures itself.
  4783. @example
  4784. flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
  4785. @end example
  4786. A special feature of efm32 controllers is that it is possible to completely disable the
  4787. debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
  4788. this via the following command:
  4789. @example
  4790. efm32 debuglock num
  4791. @end example
  4792. The @var{num} parameter is a value shown by @command{flash banks}.
  4793. Note that in order for this command to take effect, the target needs to be reset.
  4794. @emph{The current implementation is incomplete. Unprotecting flash pages is not
  4795. supported.}
  4796. @end deffn
  4797. @deffn {Flash Driver} esirisc
  4798. Members of the eSi-RISC family may optionally include internal flash programmed
  4799. via the eSi-TSMC Flash interface. Additional parameters are required to
  4800. configure the driver: @option{cfg_address} is the base address of the
  4801. configuration register interface, @option{clock_hz} is the expected clock
  4802. frequency, and @option{wait_states} is the number of configured read wait states.
  4803. @example
  4804. flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
  4805. $_TARGETNAME cfg_address clock_hz wait_states
  4806. @end example
  4807. @deffn Command {esirisc flash mass_erase} bank_id
  4808. Erase all pages in data memory for the bank identified by @option{bank_id}.
  4809. @end deffn
  4810. @deffn Command {esirisc flash ref_erase} bank_id
  4811. Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
  4812. is an uncommon operation.}
  4813. @end deffn
  4814. @end deffn
  4815. @deffn {Flash Driver} fm3
  4816. All members of the FM3 microcontroller family from Fujitsu
  4817. include internal flash and use ARM Cortex-M3 cores.
  4818. The @var{fm3} driver uses the @var{target} parameter to select the
  4819. correct bank config, it can currently be one of the following:
  4820. @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
  4821. @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
  4822. @example
  4823. flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
  4824. @end example
  4825. @end deffn
  4826. @deffn {Flash Driver} fm4
  4827. All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
  4828. include internal flash and use ARM Cortex-M4 cores.
  4829. The @var{fm4} driver uses a @var{family} parameter to select the
  4830. correct bank config, it can currently be one of the following:
  4831. @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
  4832. @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
  4833. with @code{x} treated as wildcard and otherwise case (and any trailing
  4834. characters) ignored.
  4835. @example
  4836. flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
  4837. $_TARGETNAME S6E2CCAJ0A
  4838. flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
  4839. $_TARGETNAME S6E2CCAJ0A
  4840. @end example
  4841. @emph{The current implementation is incomplete. Protection is not supported,
  4842. nor is Chip Erase (only Sector Erase is implemented).}
  4843. @end deffn
  4844. @deffn {Flash Driver} kinetis
  4845. @cindex kinetis
  4846. Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
  4847. from NXP (former Freescale) include
  4848. internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
  4849. recognizes flash size and a number of flash banks (1-4) using the chip
  4850. identification register, and autoconfigures itself.
  4851. Use kinetis_ke driver for KE0x and KEAx devices.
  4852. The @var{kinetis} driver defines option:
  4853. @itemize
  4854. @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
  4855. @end itemize
  4856. @example
  4857. flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
  4858. @end example
  4859. @deffn Command {kinetis create_banks}
  4860. Configuration command enables automatic creation of additional flash banks
  4861. based on real flash layout of device. Banks are created during device probe.
  4862. Use 'flash probe 0' to force probe.
  4863. @end deffn
  4864. @deffn Command {kinetis fcf_source} [protection|write]
  4865. Select what source is used when writing to a Flash Configuration Field.
  4866. @option{protection} mode builds FCF content from protection bits previously
  4867. set by 'flash protect' command.
  4868. This mode is default. MCU is protected from unwanted locking by immediate
  4869. writing FCF after erase of relevant sector.
  4870. @option{write} mode enables direct write to FCF.
  4871. Protection cannot be set by 'flash protect' command. FCF is written along
  4872. with the rest of a flash image.
  4873. @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
  4874. @end deffn
  4875. @deffn Command {kinetis fopt} [num]
  4876. Set value to write to FOPT byte of Flash Configuration Field.
  4877. Used in kinetis 'fcf_source protection' mode only.
  4878. @end deffn
  4879. @deffn Command {kinetis mdm check_security}
  4880. Checks status of device security lock. Used internally in examine-end event.
  4881. @end deffn
  4882. @deffn Command {kinetis mdm halt}
  4883. Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
  4884. loop when connecting to an unsecured target.
  4885. @end deffn
  4886. @deffn Command {kinetis mdm mass_erase}
  4887. Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
  4888. back to its factory state, removing security. It does not require the processor
  4889. to be halted, however the target will remain in a halted state after this
  4890. command completes.
  4891. @end deffn
  4892. @deffn Command {kinetis nvm_partition}
  4893. For FlexNVM devices only (KxxDX and KxxFX).
  4894. Command shows or sets data flash or EEPROM backup size in kilobytes,
  4895. sets two EEPROM blocks sizes in bytes and enables/disables loading
  4896. of EEPROM contents to FlexRAM during reset.
  4897. For details see device reference manual, Flash Memory Module,
  4898. Program Partition command.
  4899. Setting is possible only once after mass_erase.
  4900. Reset the device after partition setting.
  4901. Show partition size:
  4902. @example
  4903. kinetis nvm_partition info
  4904. @end example
  4905. Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
  4906. of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
  4907. @example
  4908. kinetis nvm_partition dataflash 32 512 1536 on
  4909. @end example
  4910. Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
  4911. of 1024 bytes and its contents is not loaded to FlexRAM during reset:
  4912. @example
  4913. kinetis nvm_partition eebkp 16 1024 1024 off
  4914. @end example
  4915. @end deffn
  4916. @deffn Command {kinetis mdm reset}
  4917. Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
  4918. RESET pin, which can be used to reset other hardware on board.
  4919. @end deffn
  4920. @deffn Command {kinetis disable_wdog}
  4921. For Kx devices only (KLx has different COP watchdog, it is not supported).
  4922. Command disables watchdog timer.
  4923. @end deffn
  4924. @end deffn
  4925. @deffn {Flash Driver} kinetis_ke
  4926. @cindex kinetis_ke
  4927. KE0x and KEAx members of the Kinetis microcontroller family from NXP include
  4928. internal flash and use ARM Cortex-M0+. The driver automatically recognizes
  4929. the KE0x sub-family using the chip identification register, and
  4930. autoconfigures itself.
  4931. Use kinetis (not kinetis_ke) driver for KE1x devices.
  4932. @example
  4933. flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
  4934. @end example
  4935. @deffn Command {kinetis_ke mdm check_security}
  4936. Checks status of device security lock. Used internally in examine-end event.
  4937. @end deffn
  4938. @deffn Command {kinetis_ke mdm mass_erase}
  4939. Issues a complete Flash erase via the MDM-AP.
  4940. This can be used to erase a chip back to its factory state.
  4941. Command removes security lock from a device (use of SRST highly recommended).
  4942. It does not require the processor to be halted.
  4943. @end deffn
  4944. @deffn Command {kinetis_ke disable_wdog}
  4945. Command disables watchdog timer.
  4946. @end deffn
  4947. @end deffn
  4948. @deffn {Flash Driver} lpc2000
  4949. This is the driver to support internal flash of all members of the
  4950. LPC11(x)00 and LPC1300 microcontroller families and most members of
  4951. the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
  4952. LPC8Nxx and NHS31xx microcontroller families from NXP.
  4953. @quotation Note
  4954. There are LPC2000 devices which are not supported by the @var{lpc2000}
  4955. driver:
  4956. The LPC2888 is supported by the @var{lpc288x} driver.
  4957. The LPC29xx family is supported by the @var{lpc2900} driver.
  4958. @end quotation
  4959. The @var{lpc2000} driver defines two mandatory and two optional parameters,
  4960. which must appear in the following order:
  4961. @itemize
  4962. @item @var{variant} ... required, may be
  4963. @option{lpc2000_v1} (older LPC21xx and LPC22xx)
  4964. @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  4965. @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
  4966. @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
  4967. LPC43x[2357])
  4968. @option{lpc800} (LPC8xx)
  4969. @option{lpc1100} (LPC11(x)xx and LPC13xx)
  4970. @option{lpc1500} (LPC15xx)
  4971. @option{lpc54100} (LPC541xx)
  4972. @option{lpc4000} (LPC40xx)
  4973. or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
  4974. LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
  4975. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  4976. at which the core is running
  4977. @item @option{calc_checksum} ... optional (but you probably want to provide this!),
  4978. telling the driver to calculate a valid checksum for the exception vector table.
  4979. @quotation Note
  4980. If you don't provide @option{calc_checksum} when you're writing the vector
  4981. table, the boot ROM will almost certainly ignore your flash image.
  4982. However, if you do provide it,
  4983. with most tool chains @command{verify_image} will fail.
  4984. @end quotation
  4985. @item @option{iap_entry} ... optional telling the driver to use a different
  4986. ROM IAP entry point.
  4987. @end itemize
  4988. LPC flashes don't require the chip and bus width to be specified.
  4989. @example
  4990. flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  4991. lpc2000_v2 14765 calc_checksum
  4992. @end example
  4993. @deffn {Command} {lpc2000 part_id} bank
  4994. Displays the four byte part identifier associated with
  4995. the specified flash @var{bank}.
  4996. @end deffn
  4997. @end deffn
  4998. @deffn {Flash Driver} lpc288x
  4999. The LPC2888 microcontroller from NXP needs slightly different flash
  5000. support from its lpc2000 siblings.
  5001. The @var{lpc288x} driver defines one mandatory parameter,
  5002. the programming clock rate in Hz.
  5003. LPC flashes don't require the chip and bus width to be specified.
  5004. @example
  5005. flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
  5006. @end example
  5007. @end deffn
  5008. @deffn {Flash Driver} lpc2900
  5009. This driver supports the LPC29xx ARM968E based microcontroller family
  5010. from NXP.
  5011. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  5012. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  5013. sector layout are auto-configured by the driver.
  5014. The driver has one additional mandatory parameter: The CPU clock rate
  5015. (in kHz) at the time the flash operations will take place. Most of the time this
  5016. will not be the crystal frequency, but a higher PLL frequency. The
  5017. @code{reset-init} event handler in the board script is usually the place where
  5018. you start the PLL.
  5019. The driver rejects flashless devices (currently the LPC2930).
  5020. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  5021. It must be handled much more like NAND flash memory, and will therefore be
  5022. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  5023. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  5024. sector needs to be erased or programmed, it is automatically unprotected.
  5025. What is shown as protection status in the @code{flash info} command, is
  5026. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  5027. sector from ever being erased or programmed again. As this is an irreversible
  5028. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  5029. and not by the standard @code{flash protect} command.
  5030. Example for a 125 MHz clock frequency:
  5031. @example
  5032. flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
  5033. @end example
  5034. Some @code{lpc2900}-specific commands are defined. In the following command list,
  5035. the @var{bank} parameter is the bank number as obtained by the
  5036. @code{flash banks} command.
  5037. @deffn Command {lpc2900 signature} bank
  5038. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  5039. content. This is a hardware feature of the flash block, hence the calculation is
  5040. very fast. You may use this to verify the content of a programmed device against
  5041. a known signature.
  5042. Example:
  5043. @example
  5044. lpc2900 signature 0
  5045. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  5046. @end example
  5047. @end deffn
  5048. @deffn Command {lpc2900 read_custom} bank filename
  5049. Reads the 912 bytes of customer information from the flash index sector, and
  5050. saves it to a file in binary format.
  5051. Example:
  5052. @example
  5053. lpc2900 read_custom 0 /path_to/customer_info.bin
  5054. @end example
  5055. @end deffn
  5056. The index sector of the flash is a @emph{write-only} sector. It cannot be
  5057. erased! In order to guard against unintentional write access, all following
  5058. commands need to be preceded by a successful call to the @code{password}
  5059. command:
  5060. @deffn Command {lpc2900 password} bank password
  5061. You need to use this command right before each of the following commands:
  5062. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  5063. @code{lpc2900 secure_jtag}.
  5064. The password string is fixed to "I_know_what_I_am_doing".
  5065. Example:
  5066. @example
  5067. lpc2900 password 0 I_know_what_I_am_doing
  5068. Potentially dangerous operation allowed in next command!
  5069. @end example
  5070. @end deffn
  5071. @deffn Command {lpc2900 write_custom} bank filename type
  5072. Writes the content of the file into the customer info space of the flash index
  5073. sector. The filetype can be specified with the @var{type} field. Possible values
  5074. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  5075. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  5076. contain a single section, and the contained data length must be exactly
  5077. 912 bytes.
  5078. @quotation Attention
  5079. This cannot be reverted! Be careful!
  5080. @end quotation
  5081. Example:
  5082. @example
  5083. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  5084. @end example
  5085. @end deffn
  5086. @deffn Command {lpc2900 secure_sector} bank first last
  5087. Secures the sector range from @var{first} to @var{last} (including) against
  5088. further program and erase operations. The sector security will be effective
  5089. after the next power cycle.
  5090. @quotation Attention
  5091. This cannot be reverted! Be careful!
  5092. @end quotation
  5093. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  5094. Example:
  5095. @example
  5096. lpc2900 secure_sector 0 1 1
  5097. flash info 0
  5098. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  5099. # 0: 0x00000000 (0x2000 8kB) not protected
  5100. # 1: 0x00002000 (0x2000 8kB) protected
  5101. # 2: 0x00004000 (0x2000 8kB) not protected
  5102. @end example
  5103. @end deffn
  5104. @deffn Command {lpc2900 secure_jtag} bank
  5105. Irreversibly disable the JTAG port. The new JTAG security setting will be
  5106. effective after the next power cycle.
  5107. @quotation Attention
  5108. This cannot be reverted! Be careful!
  5109. @end quotation
  5110. Examples:
  5111. @example
  5112. lpc2900 secure_jtag 0
  5113. @end example
  5114. @end deffn
  5115. @end deffn
  5116. @deffn {Flash Driver} mdr
  5117. This drivers handles the integrated NOR flash on Milandr Cortex-M
  5118. based controllers. A known limitation is that the Info memory can't be
  5119. read or verified as it's not memory mapped.
  5120. @example
  5121. flash bank <name> mdr <base> <size> \
  5122. 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
  5123. @end example
  5124. @itemize @bullet
  5125. @item @var{type} - 0 for main memory, 1 for info memory
  5126. @item @var{page_count} - total number of pages
  5127. @item @var{sec_count} - number of sector per page count
  5128. @end itemize
  5129. Example usage:
  5130. @example
  5131. if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
  5132. flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
  5133. 0 0 $_TARGETNAME 1 1 4
  5134. @} else @{
  5135. flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
  5136. 0 0 $_TARGETNAME 0 32 4
  5137. @}
  5138. @end example
  5139. @end deffn
  5140. @deffn {Flash Driver} msp432
  5141. All versions of the SimpleLink MSP432 microcontrollers from Texas
  5142. Instruments include internal flash. The msp432 flash driver automatically
  5143. recognizes the specific version's flash parameters and autoconfigures itself.
  5144. Main program flash (starting at address 0) is flash bank 0. Information flash
  5145. region on MSP432P4 versions (starting at address 0x200000) is flash bank 1.
  5146. @example
  5147. flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
  5148. @end example
  5149. @deffn Command {msp432 mass_erase} [main|all]
  5150. Performs a complete erase of flash. By default, @command{mass_erase} will erase
  5151. only the main program flash.
  5152. On MSP432P4 versions, using @command{mass_erase all} will erase both the
  5153. main program and information flash regions. To also erase the BSL in information
  5154. flash, the user must first use the @command{bsl} command.
  5155. @end deffn
  5156. @deffn Command {msp432 bsl} [unlock|lock]
  5157. On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
  5158. region in information flash so that flash commands can erase or write the BSL.
  5159. Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
  5160. To erase and program the BSL:
  5161. @example
  5162. msp432 bsl unlock
  5163. flash erase_address 0x202000 0x2000
  5164. flash write_image bsl.bin 0x202000
  5165. msp432 bsl lock
  5166. @end example
  5167. @end deffn
  5168. @end deffn
  5169. @deffn {Flash Driver} niietcm4
  5170. This drivers handles the integrated NOR flash on NIIET Cortex-M4
  5171. based controllers. Flash size and sector layout are auto-configured by the driver.
  5172. Main flash memory is called "Bootflash" and has main region and info region.
  5173. Info region is NOT memory mapped by default,
  5174. but it can replace first part of main region if needed.
  5175. Full erase, single and block writes are supported for both main and info regions.
  5176. There is additional not memory mapped flash called "Userflash", which
  5177. also have division into regions: main and info.
  5178. Purpose of userflash - to store system and user settings.
  5179. Driver has special commands to perform operations with this memory.
  5180. @example
  5181. flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
  5182. @end example
  5183. Some niietcm4-specific commands are defined:
  5184. @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
  5185. Read byte from main or info userflash region.
  5186. @end deffn
  5187. @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
  5188. Write byte to main or info userflash region.
  5189. @end deffn
  5190. @deffn Command {niietcm4 uflash_full_erase} bank
  5191. Erase all userflash including info region.
  5192. @end deffn
  5193. @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
  5194. Erase sectors of main or info userflash region, starting at sector first up to and including last.
  5195. @end deffn
  5196. @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
  5197. Check sectors protect.
  5198. @end deffn
  5199. @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
  5200. Protect sectors of main or info userflash region, starting at sector first up to and including last.
  5201. @end deffn
  5202. @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
  5203. Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
  5204. @end deffn
  5205. @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
  5206. Configure external memory interface for boot.
  5207. @end deffn
  5208. @deffn Command {niietcm4 service_mode_erase} bank
  5209. Perform emergency erase of all flash (bootflash and userflash).
  5210. @end deffn
  5211. @deffn Command {niietcm4 driver_info} bank
  5212. Show information about flash driver.
  5213. @end deffn
  5214. @end deffn
  5215. @deffn {Flash Driver} nrf5
  5216. All members of the nRF51 microcontroller families from Nordic Semiconductor
  5217. include internal flash and use ARM Cortex-M0 core.
  5218. Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
  5219. internal flash and use an ARM Cortex-M4F core.
  5220. @example
  5221. flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
  5222. @end example
  5223. Some nrf5-specific commands are defined:
  5224. @deffn Command {nrf5 mass_erase}
  5225. Erases the contents of the code memory and user information
  5226. configuration registers as well. It must be noted that this command
  5227. works only for chips that do not have factory pre-programmed region 0
  5228. code.
  5229. @end deffn
  5230. @end deffn
  5231. @deffn {Flash Driver} ocl
  5232. This driver is an implementation of the ``on chip flash loader''
  5233. protocol proposed by Pavel Chromy.
  5234. It is a minimalistic command-response protocol intended to be used
  5235. over a DCC when communicating with an internal or external flash
  5236. loader running from RAM. An example implementation for AT91SAM7x is
  5237. available in @file{contrib/loaders/flash/at91sam7x/}.
  5238. @example
  5239. flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
  5240. @end example
  5241. @end deffn
  5242. @deffn {Flash Driver} pic32mx
  5243. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  5244. and integrate flash memory.
  5245. @example
  5246. flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
  5247. flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
  5248. @end example
  5249. @comment numerous *disabled* commands are defined:
  5250. @comment - chip_erase ... pointless given flash_erase_address
  5251. @comment - lock, unlock ... pointless given protect on/off (yes?)
  5252. @comment - pgm_word ... shouldn't bank be deduced from address??
  5253. Some pic32mx-specific commands are defined:
  5254. @deffn Command {pic32mx pgm_word} address value bank
  5255. Programs the specified 32-bit @var{value} at the given @var{address}
  5256. in the specified chip @var{bank}.
  5257. @end deffn
  5258. @deffn Command {pic32mx unlock} bank
  5259. Unlock and erase specified chip @var{bank}.
  5260. This will remove any Code Protection.
  5261. @end deffn
  5262. @end deffn
  5263. @deffn {Flash Driver} psoc4
  5264. All members of the PSoC 41xx/42xx microcontroller family from Cypress
  5265. include internal flash and use ARM Cortex-M0 cores.
  5266. The driver automatically recognizes a number of these chips using
  5267. the chip identification register, and autoconfigures itself.
  5268. Note: Erased internal flash reads as 00.
  5269. System ROM of PSoC 4 does not implement erase of a flash sector.
  5270. @example
  5271. flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
  5272. @end example
  5273. psoc4-specific commands
  5274. @deffn Command {psoc4 flash_autoerase} num (on|off)
  5275. Enables or disables autoerase mode for a flash bank.
  5276. If flash_autoerase is off, use mass_erase before flash programming.
  5277. Flash erase command fails if region to erase is not whole flash memory.
  5278. If flash_autoerase is on, a sector is both erased and programmed in one
  5279. system ROM call. Flash erase command is ignored.
  5280. This mode is suitable for gdb load.
  5281. The @var{num} parameter is a value shown by @command{flash banks}.
  5282. @end deffn
  5283. @deffn Command {psoc4 mass_erase} num
  5284. Erases the contents of the flash memory, protection and security lock.
  5285. The @var{num} parameter is a value shown by @command{flash banks}.
  5286. @end deffn
  5287. @end deffn
  5288. @deffn {Flash Driver} psoc5lp
  5289. All members of the PSoC 5LP microcontroller family from Cypress
  5290. include internal program flash and use ARM Cortex-M3 cores.
  5291. The driver probes for a number of these chips and autoconfigures itself,
  5292. apart from the base address.
  5293. @example
  5294. flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
  5295. @end example
  5296. @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
  5297. @quotation Attention
  5298. If flash operations are performed in ECC-disabled mode, they will also affect
  5299. the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
  5300. then also erase the corresponding 2k data bytes in the 0x48000000 area.
  5301. Writing to the ECC data bytes in ECC-disabled mode is not implemented.
  5302. @end quotation
  5303. Commands defined in the @var{psoc5lp} driver:
  5304. @deffn Command {psoc5lp mass_erase}
  5305. Erases all flash data and ECC/configuration bytes, all flash protection rows,
  5306. and all row latches in all flash arrays on the device.
  5307. @end deffn
  5308. @end deffn
  5309. @deffn {Flash Driver} psoc5lp_eeprom
  5310. All members of the PSoC 5LP microcontroller family from Cypress
  5311. include internal EEPROM and use ARM Cortex-M3 cores.
  5312. The driver probes for a number of these chips and autoconfigures itself,
  5313. apart from the base address.
  5314. @example
  5315. flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
  5316. @end example
  5317. @end deffn
  5318. @deffn {Flash Driver} psoc5lp_nvl
  5319. All members of the PSoC 5LP microcontroller family from Cypress
  5320. include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
  5321. The driver probes for a number of these chips and autoconfigures itself.
  5322. @example
  5323. flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
  5324. @end example
  5325. PSoC 5LP chips have multiple NV Latches:
  5326. @itemize
  5327. @item Device Configuration NV Latch - 4 bytes
  5328. @item Write Once (WO) NV Latch - 4 bytes
  5329. @end itemize
  5330. @b{Note:} This driver only implements the Device Configuration NVL.
  5331. The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
  5332. @quotation Attention
  5333. Switching ECC mode via write to Device Configuration NVL will require a reset
  5334. after successful write.
  5335. @end quotation
  5336. @end deffn
  5337. @deffn {Flash Driver} psoc6
  5338. Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
  5339. PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
  5340. the same Flash/RAM/MMIO address space.
  5341. Flash in PSoC6 is split into three regions:
  5342. @itemize @bullet
  5343. @item Main Flash - this is the main storage for user application.
  5344. Total size varies among devices, sector size: 256 kBytes, row size:
  5345. 512 bytes. Supports erase operation on individual rows.
  5346. @item Work Flash - intended to be used as storage for user data
  5347. (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
  5348. row size: 512 bytes.
  5349. @item Supervisory Flash - special region which contains device-specific
  5350. service data. This region does not support erase operation. Only few rows can
  5351. be programmed by the user, most of the rows are read only. Programming
  5352. operation will erase row automatically.
  5353. @end itemize
  5354. All three flash regions are supported by the driver. Flash geometry is detected
  5355. automatically by parsing data in SPCIF_GEOMETRY register.
  5356. PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
  5357. @example
  5358. flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
  5359. flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
  5360. flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
  5361. flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
  5362. flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
  5363. flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
  5364. flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
  5365. flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
  5366. flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
  5367. flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
  5368. flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
  5369. flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
  5370. @end example
  5371. psoc6-specific commands
  5372. @deffn Command {psoc6 reset_halt}
  5373. Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
  5374. When invoked for CM0+ target, it will set break point at application entry point
  5375. and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
  5376. reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
  5377. instead of SYSRESETREQ to avoid unwanted reset of CM0+;
  5378. @end deffn
  5379. @deffn Command {psoc6 mass_erase} num
  5380. Erases the contents given flash bank. The @var{num} parameter is a value shown
  5381. by @command{flash banks}.
  5382. Note: only Main and Work flash regions support Erase operation.
  5383. @end deffn
  5384. @end deffn
  5385. @deffn {Flash Driver} sim3x
  5386. All members of the SiM3 microcontroller family from Silicon Laboratories
  5387. include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
  5388. and SWD interface.
  5389. The @var{sim3x} driver tries to probe the device to auto detect the MCU.
  5390. If this fails, it will use the @var{size} parameter as the size of flash bank.
  5391. @example
  5392. flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
  5393. @end example
  5394. There are 2 commands defined in the @var{sim3x} driver:
  5395. @deffn Command {sim3x mass_erase}
  5396. Erases the complete flash. This is used to unlock the flash.
  5397. And this command is only possible when using the SWD interface.
  5398. @end deffn
  5399. @deffn Command {sim3x lock}
  5400. Lock the flash. To unlock use the @command{sim3x mass_erase} command.
  5401. @end deffn
  5402. @end deffn
  5403. @deffn {Flash Driver} stellaris
  5404. All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
  5405. families from Texas Instruments include internal flash. The driver
  5406. automatically recognizes a number of these chips using the chip
  5407. identification register, and autoconfigures itself.
  5408. @example
  5409. flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
  5410. @end example
  5411. @deffn Command {stellaris recover}
  5412. Performs the @emph{Recovering a "Locked" Device} procedure to restore
  5413. the flash and its associated nonvolatile registers to their factory
  5414. default values (erased). This is the only way to remove flash
  5415. protection or re-enable debugging if that capability has been
  5416. disabled.
  5417. Note that the final "power cycle the chip" step in this procedure
  5418. must be performed by hand, since OpenOCD can't do it.
  5419. @quotation Warning
  5420. if more than one Stellaris chip is connected, the procedure is
  5421. applied to all of them.
  5422. @end quotation
  5423. @end deffn
  5424. @end deffn
  5425. @deffn {Flash Driver} stm32f1x
  5426. All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
  5427. from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
  5428. The driver automatically recognizes a number of these chips using
  5429. the chip identification register, and autoconfigures itself.
  5430. @example
  5431. flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  5432. @end example
  5433. Note that some devices have been found that have a flash size register that contains
  5434. an invalid value, to workaround this issue you can override the probed value used by
  5435. the flash driver.
  5436. @example
  5437. flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
  5438. @end example
  5439. If you have a target with dual flash banks then define the second bank
  5440. as per the following example.
  5441. @example
  5442. flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
  5443. @end example
  5444. Some stm32f1x-specific commands are defined:
  5445. @deffn Command {stm32f1x lock} num
  5446. Locks the entire stm32 device against reading.
  5447. The @var{num} parameter is a value shown by @command{flash banks}.
  5448. @end deffn
  5449. @deffn Command {stm32f1x unlock} num
  5450. Unlocks the entire stm32 device for reading. This command will cause
  5451. a mass erase of the entire stm32 device if previously locked.
  5452. The @var{num} parameter is a value shown by @command{flash banks}.
  5453. @end deffn
  5454. @deffn Command {stm32f1x mass_erase} num
  5455. Mass erases the entire stm32 device.
  5456. The @var{num} parameter is a value shown by @command{flash banks}.
  5457. @end deffn
  5458. @deffn Command {stm32f1x options_read} num
  5459. Reads and displays active stm32 option bytes loaded during POR
  5460. or upon executing the @command{stm32f1x options_load} command.
  5461. The @var{num} parameter is a value shown by @command{flash banks}.
  5462. @end deffn
  5463. @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  5464. Writes the stm32 option byte with the specified values.
  5465. The @var{num} parameter is a value shown by @command{flash banks}.
  5466. @end deffn
  5467. @deffn Command {stm32f1x options_load} num
  5468. Generates a special kind of reset to re-load the stm32 option bytes written
  5469. by the @command{stm32f1x options_write} or @command{flash protect} commands
  5470. without having to power cycle the target. Not applicable to stm32f1x devices.
  5471. The @var{num} parameter is a value shown by @command{flash banks}.
  5472. @end deffn
  5473. @end deffn
  5474. @deffn {Flash Driver} stm32f2x
  5475. All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
  5476. include internal flash and use ARM Cortex-M3/M4/M7 cores.
  5477. The driver automatically recognizes a number of these chips using
  5478. the chip identification register, and autoconfigures itself.
  5479. @example
  5480. flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  5481. @end example
  5482. Note that some devices have been found that have a flash size register that contains
  5483. an invalid value, to workaround this issue you can override the probed value used by
  5484. the flash driver.
  5485. @example
  5486. flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
  5487. @end example
  5488. Some stm32f2x-specific commands are defined:
  5489. @deffn Command {stm32f2x lock} num
  5490. Locks the entire stm32 device.
  5491. The @var{num} parameter is a value shown by @command{flash banks}.
  5492. @end deffn
  5493. @deffn Command {stm32f2x unlock} num
  5494. Unlocks the entire stm32 device.
  5495. The @var{num} parameter is a value shown by @command{flash banks}.
  5496. @end deffn
  5497. @deffn Command {stm32f2x mass_erase} num
  5498. Mass erases the entire stm32f2x device.
  5499. The @var{num} parameter is a value shown by @command{flash banks}.
  5500. @end deffn
  5501. @deffn Command {stm32f2x options_read} num
  5502. Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
  5503. The @var{num} parameter is a value shown by @command{flash banks}.
  5504. @end deffn
  5505. @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
  5506. Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
  5507. Warning: The meaning of the various bits depends on the device, always check datasheet!
  5508. The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
  5509. 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
  5510. @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
  5511. @end deffn
  5512. @deffn Command {stm32f2x optcr2_write} num optcr2
  5513. Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
  5514. The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
  5515. @end deffn
  5516. @end deffn
  5517. @deffn {Flash Driver} stm32h7x
  5518. All members of the STM32H7 microcontroller families from STMicroelectronics
  5519. include internal flash and use ARM Cortex-M7 core.
  5520. The driver automatically recognizes a number of these chips using
  5521. the chip identification register, and autoconfigures itself.
  5522. @example
  5523. flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
  5524. @end example
  5525. Note that some devices have been found that have a flash size register that contains
  5526. an invalid value, to workaround this issue you can override the probed value used by
  5527. the flash driver.
  5528. @example
  5529. flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
  5530. @end example
  5531. Some stm32h7x-specific commands are defined:
  5532. @deffn Command {stm32h7x lock} num
  5533. Locks the entire stm32 device.
  5534. The @var{num} parameter is a value shown by @command{flash banks}.
  5535. @end deffn
  5536. @deffn Command {stm32h7x unlock} num
  5537. Unlocks the entire stm32 device.
  5538. The @var{num} parameter is a value shown by @command{flash banks}.
  5539. @end deffn
  5540. @deffn Command {stm32h7x mass_erase} num
  5541. Mass erases the entire stm32h7x device.
  5542. The @var{num} parameter is a value shown by @command{flash banks}.
  5543. @end deffn
  5544. @end deffn
  5545. @deffn {Flash Driver} stm32lx
  5546. All members of the STM32L microcontroller families from STMicroelectronics
  5547. include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
  5548. The driver automatically recognizes a number of these chips using
  5549. the chip identification register, and autoconfigures itself.
  5550. @example
  5551. flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
  5552. @end example
  5553. Note that some devices have been found that have a flash size register that contains
  5554. an invalid value, to workaround this issue you can override the probed value used by
  5555. the flash driver. If you use 0 as the bank base address, it tells the
  5556. driver to autodetect the bank location assuming you're configuring the
  5557. second bank.
  5558. @example
  5559. flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
  5560. @end example
  5561. Some stm32lx-specific commands are defined:
  5562. @deffn Command {stm32lx lock} num
  5563. Locks the entire stm32 device.
  5564. The @var{num} parameter is a value shown by @command{flash banks}.
  5565. @end deffn
  5566. @deffn Command {stm32lx unlock} num
  5567. Unlocks the entire stm32 device.
  5568. The @var{num} parameter is a value shown by @command{flash banks}.
  5569. @end deffn
  5570. @deffn Command {stm32lx mass_erase} num
  5571. Mass erases the entire stm32lx device (all flash banks and EEPROM
  5572. data). This is the only way to unlock a protected flash (unless RDP
  5573. Level is 2 which can't be unlocked at all).
  5574. The @var{num} parameter is a value shown by @command{flash banks}.
  5575. @end deffn
  5576. @end deffn
  5577. @deffn {Flash Driver} stm32l4x
  5578. All members of the STM32L4 microcontroller families from STMicroelectronics
  5579. include internal flash and use ARM Cortex-M4 cores.
  5580. The driver automatically recognizes a number of these chips using
  5581. the chip identification register, and autoconfigures itself.
  5582. @example
  5583. flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
  5584. @end example
  5585. Note that some devices have been found that have a flash size register that contains
  5586. an invalid value, to workaround this issue you can override the probed value used by
  5587. the flash driver.
  5588. @example
  5589. flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
  5590. @end example
  5591. Some stm32l4x-specific commands are defined:
  5592. @deffn Command {stm32l4x lock} num
  5593. Locks the entire stm32 device.
  5594. The @var{num} parameter is a value shown by @command{flash banks}.
  5595. @end deffn
  5596. @deffn Command {stm32l4x unlock} num
  5597. Unlocks the entire stm32 device.
  5598. The @var{num} parameter is a value shown by @command{flash banks}.
  5599. @end deffn
  5600. @deffn Command {stm32l4x mass_erase} num
  5601. Mass erases the entire stm32l4x device.
  5602. The @var{num} parameter is a value shown by @command{flash banks}.
  5603. @end deffn
  5604. @deffn Command {stm32l4x option_read} num reg_offset
  5605. Reads an option byte register from the stm32l4x device.
  5606. The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
  5607. is the register offset of the Option byte to read.
  5608. For example to read the FLASH_OPTR register:
  5609. @example
  5610. stm32l4x option_read 0 0x20
  5611. # Option Register: <0x40022020> = 0xffeff