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  1. /***************************************************************************
  2. * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
  3. * Modified by Megan Wachs <megan@sifive.com> from the original stmsmi.c *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>. *
  17. ***************************************************************************/
  18. /* The Freedom E SPI controller is a SPI bus controller
  19. * specifically designed for SPI Flash Memories on Freedom E platforms.
  20. *
  21. * Two working modes are available:
  22. * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  23. * on the bus. Writes are only possible in this mode.
  24. * - HW mode: Memory content is directly
  25. * accessible in CPU memory space. CPU can read and execute memory content.
  26. */
  27. /* ATTENTION:
  28. * To have flash memory mapped in CPU memory space, the controller
  29. * must have "HW mode" enabled.
  30. * 1) The command "reset init" has to initialize the controller and put
  31. * it in HW mode (this is actually the default out of reset for Freedom E systems).
  32. * 2) every command in this file have to return to prompt in HW mode. */
  33. #ifdef HAVE_CONFIG_H
  34. #include "config.h"
  35. #endif
  36. #include "imp.h"
  37. #include "spi.h"
  38. #include <jtag/jtag.h>
  39. #include <helper/time_support.h>
  40. #include <target/algorithm.h>
  41. #include "target/riscv/riscv.h"
  42. /* Register offsets */
  43. #define FESPI_REG_SCKDIV 0x00
  44. #define FESPI_REG_SCKMODE 0x04
  45. #define FESPI_REG_CSID 0x10
  46. #define FESPI_REG_CSDEF 0x14
  47. #define FESPI_REG_CSMODE 0x18
  48. #define FESPI_REG_DCSSCK 0x28
  49. #define FESPI_REG_DSCKCS 0x2a
  50. #define FESPI_REG_DINTERCS 0x2c
  51. #define FESPI_REG_DINTERXFR 0x2e
  52. #define FESPI_REG_FMT 0x40
  53. #define FESPI_REG_TXFIFO 0x48
  54. #define FESPI_REG_RXFIFO 0x4c
  55. #define FESPI_REG_TXCTRL 0x50
  56. #define FESPI_REG_RXCTRL 0x54
  57. #define FESPI_REG_FCTRL 0x60
  58. #define FESPI_REG_FFMT 0x64
  59. #define FESPI_REG_IE 0x70
  60. #define FESPI_REG_IP 0x74
  61. /* Fields */
  62. #define FESPI_SCK_POL 0x1
  63. #define FESPI_SCK_PHA 0x2
  64. #define FESPI_FMT_PROTO(x) ((x) & 0x3)
  65. #define FESPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
  66. #define FESPI_FMT_DIR(x) (((x) & 0x1) << 3)
  67. #define FESPI_FMT_LEN(x) (((x) & 0xf) << 16)
  68. /* TXCTRL register */
  69. #define FESPI_TXWM(x) ((x) & 0xffff)
  70. /* RXCTRL register */
  71. #define FESPI_RXWM(x) ((x) & 0xffff)
  72. #define FESPI_IP_TXWM 0x1
  73. #define FESPI_IP_RXWM 0x2
  74. #define FESPI_FCTRL_EN 0x1
  75. #define FESPI_INSN_CMD_EN 0x1
  76. #define FESPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
  77. #define FESPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
  78. #define FESPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
  79. #define FESPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
  80. #define FESPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
  81. #define FESPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
  82. #define FESPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
  83. /* Values */
  84. #define FESPI_CSMODE_AUTO 0
  85. #define FESPI_CSMODE_HOLD 2
  86. #define FESPI_CSMODE_OFF 3
  87. #define FESPI_DIR_RX 0
  88. #define FESPI_DIR_TX 1
  89. #define FESPI_PROTO_S 0
  90. #define FESPI_PROTO_D 1
  91. #define FESPI_PROTO_Q 2
  92. #define FESPI_ENDIAN_MSB 0
  93. #define FESPI_ENDIAN_LSB 1
  94. /* Timeout in ms */
  95. #define FESPI_CMD_TIMEOUT (100)
  96. #define FESPI_PROBE_TIMEOUT (100)
  97. #define FESPI_MAX_TIMEOUT (3000)
  98. struct fespi_flash_bank {
  99. int probed;
  100. target_addr_t ctrl_base;
  101. const struct flash_device *dev;
  102. };
  103. struct fespi_target {
  104. char *name;
  105. uint32_t tap_idcode;
  106. uint32_t ctrl_base;
  107. };
  108. /* TODO !!! What is the right naming convention here? */
  109. static const struct fespi_target target_devices[] = {
  110. /* name, tap_idcode, ctrl_base */
  111. { "Freedom E300 SPI Flash", 0x10e31913 , 0x10014000 },
  112. { NULL, 0, 0 }
  113. };
  114. FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
  115. {
  116. struct fespi_flash_bank *fespi_info;
  117. LOG_DEBUG("%s", __func__);
  118. if (CMD_ARGC < 6)
  119. return ERROR_COMMAND_SYNTAX_ERROR;
  120. fespi_info = malloc(sizeof(struct fespi_flash_bank));
  121. if (fespi_info == NULL) {
  122. LOG_ERROR("not enough memory");
  123. return ERROR_FAIL;
  124. }
  125. bank->driver_priv = fespi_info;
  126. fespi_info->probed = 0;
  127. fespi_info->ctrl_base = 0;
  128. if (CMD_ARGC >= 7) {
  129. int temp;
  130. COMMAND_PARSE_NUMBER(int, CMD_ARGV[6], temp);
  131. fespi_info->ctrl_base = (uint32_t) temp;
  132. LOG_DEBUG("ASSUMING FESPI device at ctrl_base = 0x%" TARGET_PRIxADDR,
  133. fespi_info->ctrl_base);
  134. }
  135. return ERROR_OK;
  136. }
  137. static int fespi_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_t address)
  138. {
  139. struct target *target = bank->target;
  140. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  141. int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
  142. if (result != ERROR_OK) {
  143. LOG_ERROR("fespi_read_reg() error at 0x%" TARGET_PRIxADDR,
  144. fespi_info->ctrl_base + address);
  145. return result;
  146. }
  147. return ERROR_OK;
  148. }
  149. static int fespi_write_reg(struct flash_bank *bank, target_addr_t address, uint32_t value)
  150. { \
  151. struct target *target = bank->target;
  152. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  153. int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
  154. if (result != ERROR_OK) {
  155. LOG_ERROR("fespi_write_reg() error writing 0x%x to 0x%" TARGET_PRIxADDR,
  156. value, fespi_info->ctrl_base + address);
  157. return result;
  158. }
  159. return ERROR_OK;
  160. }
  161. static int fespi_disable_hw_mode(struct flash_bank *bank)
  162. {
  163. uint32_t fctrl;
  164. if (fespi_read_reg(bank, &fctrl, FESPI_REG_FCTRL) != ERROR_OK)
  165. return ERROR_FAIL;
  166. return fespi_write_reg(bank, FESPI_REG_FCTRL, fctrl & ~FESPI_FCTRL_EN);
  167. }
  168. static int fespi_enable_hw_mode(struct flash_bank *bank)
  169. {
  170. uint32_t fctrl;
  171. if (fespi_read_reg(bank, &fctrl, FESPI_REG_FCTRL) != ERROR_OK)
  172. return ERROR_FAIL;
  173. return fespi_write_reg(bank, FESPI_REG_FCTRL, fctrl | FESPI_FCTRL_EN);
  174. }
  175. static int fespi_set_dir(struct flash_bank *bank, bool dir)
  176. {
  177. uint32_t fmt;
  178. if (fespi_read_reg(bank, &fmt, FESPI_REG_FMT) != ERROR_OK)
  179. return ERROR_FAIL;
  180. return fespi_write_reg(bank, FESPI_REG_FMT,
  181. (fmt & ~(FESPI_FMT_DIR(0xFFFFFFFF))) | FESPI_FMT_DIR(dir));
  182. }
  183. static int fespi_txwm_wait(struct flash_bank *bank)
  184. {
  185. int64_t start = timeval_ms();
  186. while (1) {
  187. uint32_t ip;
  188. if (fespi_read_reg(bank, &ip, FESPI_REG_IP) != ERROR_OK)
  189. return ERROR_FAIL;
  190. if (ip & FESPI_IP_TXWM)
  191. break;
  192. int64_t now = timeval_ms();
  193. if (now - start > 1000) {
  194. LOG_ERROR("ip.txwm didn't get set.");
  195. return ERROR_TARGET_TIMEOUT;
  196. }
  197. }
  198. return ERROR_OK;
  199. }
  200. static int fespi_tx(struct flash_bank *bank, uint8_t in)
  201. {
  202. int64_t start = timeval_ms();
  203. while (1) {
  204. uint32_t txfifo;
  205. if (fespi_read_reg(bank, &txfifo, FESPI_REG_TXFIFO) != ERROR_OK)
  206. return ERROR_FAIL;
  207. if (!(txfifo >> 31))
  208. break;
  209. int64_t now = timeval_ms();
  210. if (now - start > 1000) {
  211. LOG_ERROR("txfifo stayed negative.");
  212. return ERROR_TARGET_TIMEOUT;
  213. }
  214. }
  215. return fespi_write_reg(bank, FESPI_REG_TXFIFO, in);
  216. }
  217. static int fespi_rx(struct flash_bank *bank, uint8_t *out)
  218. {
  219. int64_t start = timeval_ms();
  220. uint32_t value;
  221. while (1) {
  222. if (fespi_read_reg(bank, &value, FESPI_REG_RXFIFO) != ERROR_OK)
  223. return ERROR_FAIL;
  224. if (!(value >> 31))
  225. break;
  226. int64_t now = timeval_ms();
  227. if (now - start > 1000) {
  228. LOG_ERROR("rxfifo didn't go positive (value=0x%x).", value);
  229. return ERROR_TARGET_TIMEOUT;
  230. }
  231. }
  232. if (out)
  233. *out = value & 0xff;
  234. return ERROR_OK;
  235. }
  236. /* TODO!!! Why don't we need to call this after writing? */
  237. static int fespi_wip(struct flash_bank *bank, int timeout)
  238. {
  239. int64_t endtime;
  240. fespi_set_dir(bank, FESPI_DIR_RX);
  241. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
  242. return ERROR_FAIL;
  243. endtime = timeval_ms() + timeout;
  244. fespi_tx(bank, SPIFLASH_READ_STATUS);
  245. if (fespi_rx(bank, NULL) != ERROR_OK)
  246. return ERROR_FAIL;
  247. do {
  248. alive_sleep(1);
  249. fespi_tx(bank, 0);
  250. uint8_t rx;
  251. if (fespi_rx(bank, &rx) != ERROR_OK)
  252. return ERROR_FAIL;
  253. if ((rx & SPIFLASH_BSY_BIT) == 0) {
  254. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
  255. return ERROR_FAIL;
  256. fespi_set_dir(bank, FESPI_DIR_TX);
  257. return ERROR_OK;
  258. }
  259. } while (timeval_ms() < endtime);
  260. LOG_ERROR("timeout");
  261. return ERROR_FAIL;
  262. }
  263. static int fespi_erase_sector(struct flash_bank *bank, int sector)
  264. {
  265. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  266. int retval;
  267. retval = fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
  268. if (retval != ERROR_OK)
  269. return retval;
  270. retval = fespi_txwm_wait(bank);
  271. if (retval != ERROR_OK)
  272. return retval;
  273. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
  274. return ERROR_FAIL;
  275. retval = fespi_tx(bank, fespi_info->dev->erase_cmd);
  276. if (retval != ERROR_OK)
  277. return retval;
  278. sector = bank->sectors[sector].offset;
  279. retval = fespi_tx(bank, sector >> 16);
  280. if (retval != ERROR_OK)
  281. return retval;
  282. retval = fespi_tx(bank, sector >> 8);
  283. if (retval != ERROR_OK)
  284. return retval;
  285. retval = fespi_tx(bank, sector);
  286. if (retval != ERROR_OK)
  287. return retval;
  288. retval = fespi_txwm_wait(bank);
  289. if (retval != ERROR_OK)
  290. return retval;
  291. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
  292. return ERROR_FAIL;
  293. retval = fespi_wip(bank, FESPI_MAX_TIMEOUT);
  294. if (retval != ERROR_OK)
  295. return retval;
  296. return ERROR_OK;
  297. }
  298. static int fespi_erase(struct flash_bank *bank, int first, int last)
  299. {
  300. struct target *target = bank->target;
  301. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  302. int retval = ERROR_OK;
  303. int sector;
  304. LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
  305. if (target->state != TARGET_HALTED) {
  306. LOG_ERROR("Target not halted");
  307. return ERROR_TARGET_NOT_HALTED;
  308. }
  309. if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
  310. LOG_ERROR("Flash sector invalid");
  311. return ERROR_FLASH_SECTOR_INVALID;
  312. }
  313. if (!(fespi_info->probed)) {
  314. LOG_ERROR("Flash bank not probed");
  315. return ERROR_FLASH_BANK_NOT_PROBED;
  316. }
  317. for (sector = first; sector <= last; sector++) {
  318. if (bank->sectors[sector].is_protected) {
  319. LOG_ERROR("Flash sector %d protected", sector);
  320. return ERROR_FAIL;
  321. }
  322. }
  323. if (fespi_info->dev->erase_cmd == 0x00)
  324. return ERROR_FLASH_OPER_UNSUPPORTED;
  325. if (fespi_write_reg(bank, FESPI_REG_TXCTRL, FESPI_TXWM(1)) != ERROR_OK)
  326. return ERROR_FAIL;
  327. retval = fespi_txwm_wait(bank);
  328. if (retval != ERROR_OK) {
  329. LOG_ERROR("WM Didn't go high before attempting.");
  330. return retval;
  331. }
  332. /* Disable Hardware accesses*/
  333. if (fespi_disable_hw_mode(bank) != ERROR_OK)
  334. return ERROR_FAIL;
  335. /* poll WIP */
  336. retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
  337. if (retval != ERROR_OK)
  338. goto done;
  339. for (sector = first; sector <= last; sector++) {
  340. retval = fespi_erase_sector(bank, sector);
  341. if (retval != ERROR_OK)
  342. goto done;
  343. keep_alive();
  344. }
  345. /* Switch to HW mode before return to prompt */
  346. done:
  347. if (fespi_enable_hw_mode(bank) != ERROR_OK)
  348. return ERROR_FAIL;
  349. return retval;
  350. }
  351. static int fespi_protect(struct flash_bank *bank, int set,
  352. int first, int last)
  353. {
  354. int sector;
  355. for (sector = first; sector <= last; sector++)
  356. bank->sectors[sector].is_protected = set;
  357. return ERROR_OK;
  358. }
  359. static int slow_fespi_write_buffer(struct flash_bank *bank,
  360. const uint8_t *buffer, uint32_t offset, uint32_t len)
  361. {
  362. uint32_t ii;
  363. if (offset & 0xFF000000) {
  364. LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x",
  365. offset);
  366. return ERROR_FAIL;
  367. }
  368. /* TODO!!! assert that len < page size */
  369. fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
  370. fespi_txwm_wait(bank);
  371. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
  372. return ERROR_FAIL;
  373. fespi_tx(bank, SPIFLASH_PAGE_PROGRAM);
  374. fespi_tx(bank, offset >> 16);
  375. fespi_tx(bank, offset >> 8);
  376. fespi_tx(bank, offset);
  377. for (ii = 0; ii < len; ii++)
  378. fespi_tx(bank, buffer[ii]);
  379. fespi_txwm_wait(bank);
  380. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
  381. return ERROR_FAIL;
  382. keep_alive();
  383. return ERROR_OK;
  384. }
  385. static const uint8_t algorithm_bin[] = {
  386. #include "../../../contrib/loaders/flash/fespi/fespi.inc"
  387. };
  388. #define STEP_EXIT 4
  389. #define STEP_TX 8
  390. #define STEP_TXWM_WAIT 12
  391. #define STEP_WRITE_REG 16
  392. #define STEP_WIP_WAIT 20
  393. #define STEP_SET_DIR 24
  394. #define STEP_NOP 0xff
  395. struct algorithm_steps {
  396. unsigned size;
  397. unsigned used;
  398. uint8_t **steps;
  399. };
  400. static struct algorithm_steps *as_new(void)
  401. {
  402. struct algorithm_steps *as = calloc(1, sizeof(struct algorithm_steps));
  403. as->size = 8;
  404. as->steps = malloc(as->size * sizeof(as->steps[0]));
  405. return as;
  406. }
  407. static struct algorithm_steps *as_delete(struct algorithm_steps *as)
  408. {
  409. for (unsigned step = 0; step < as->used; step++) {
  410. free(as->steps[step]);
  411. as->steps[step] = NULL;
  412. }
  413. free(as->steps);
  414. free(as);
  415. return NULL;
  416. }
  417. static int as_empty(struct algorithm_steps *as)
  418. {
  419. for (unsigned s = 0; s < as->used; s++) {
  420. if (as->steps[s][0] != STEP_NOP)
  421. return 0;
  422. }
  423. return 1;
  424. }
  425. /* Return size of compiled program. */
  426. static unsigned as_compile(struct algorithm_steps *as, uint8_t *target,
  427. unsigned target_size)
  428. {
  429. unsigned offset = 0;
  430. bool finish_early = false;
  431. for (unsigned s = 0; s < as->used && !finish_early; s++) {
  432. unsigned bytes_left = target_size - offset;
  433. switch (as->steps[s][0]) {
  434. case STEP_NOP:
  435. break;
  436. case STEP_TX:
  437. {
  438. unsigned size = as->steps[s][1];
  439. if (size + 3 > bytes_left) {
  440. finish_early = true;
  441. break;
  442. }
  443. memcpy(target + offset, as->steps[s], size + 2);
  444. offset += size + 2;
  445. break;
  446. }
  447. case STEP_WRITE_REG:
  448. if (4 > bytes_left) {
  449. finish_early = true;
  450. break;
  451. }
  452. memcpy(target + offset, as->steps[s], 3);
  453. offset += 3;
  454. break;
  455. case STEP_SET_DIR:
  456. if (3 > bytes_left) {
  457. finish_early = true;
  458. break;
  459. }
  460. memcpy(target + offset, as->steps[s], 2);
  461. offset += 2;
  462. break;
  463. case STEP_TXWM_WAIT:
  464. case STEP_WIP_WAIT:
  465. if (2 > bytes_left) {
  466. finish_early = true;
  467. break;
  468. }
  469. memcpy(target + offset, as->steps[s], 1);
  470. offset += 1;
  471. break;
  472. default:
  473. assert(0);
  474. }
  475. if (!finish_early)
  476. as->steps[s][0] = STEP_NOP;
  477. }
  478. assert(offset + 1 <= target_size);
  479. target[offset++] = STEP_EXIT;
  480. LOG_DEBUG("%d-byte program:", offset);
  481. for (unsigned i = 0; i < offset;) {
  482. char buf[80];
  483. for (unsigned x = 0; i < offset && x < 16; x++, i++)
  484. sprintf(buf + x*3, "%02x ", target[i]);
  485. LOG_DEBUG("%s", buf);
  486. }
  487. return offset;
  488. }
  489. static void as_add_step(struct algorithm_steps *as, uint8_t *step)
  490. {
  491. if (as->used == as->size) {
  492. as->size *= 2;
  493. as->steps = realloc(as->steps, sizeof(as->steps[0]) * as->size);
  494. LOG_DEBUG("Increased size to 0x%x", as->size);
  495. }
  496. as->steps[as->used] = step;
  497. as->used++;
  498. }
  499. static void as_add_tx(struct algorithm_steps *as, unsigned count, const uint8_t *data)
  500. {
  501. LOG_DEBUG("count=%d", count);
  502. while (count > 0) {
  503. unsigned step_count = MIN(count, 255);
  504. uint8_t *step = malloc(step_count + 2);
  505. step[0] = STEP_TX;
  506. step[1] = step_count;
  507. memcpy(step + 2, data, step_count);
  508. as_add_step(as, step);
  509. data += step_count;
  510. count -= step_count;
  511. }
  512. }
  513. static void as_add_tx1(struct algorithm_steps *as, uint8_t byte)
  514. {
  515. uint8_t data[1];
  516. data[0] = byte;
  517. as_add_tx(as, 1, data);
  518. }
  519. static void as_add_write_reg(struct algorithm_steps *as, uint8_t offset, uint8_t data)
  520. {
  521. uint8_t *step = malloc(3);
  522. step[0] = STEP_WRITE_REG;
  523. step[1] = offset;
  524. step[2] = data;
  525. as_add_step(as, step);
  526. }
  527. static void as_add_txwm_wait(struct algorithm_steps *as)
  528. {
  529. uint8_t *step = malloc(1);
  530. step[0] = STEP_TXWM_WAIT;
  531. as_add_step(as, step);
  532. }
  533. static void as_add_wip_wait(struct algorithm_steps *as)
  534. {
  535. uint8_t *step = malloc(1);
  536. step[0] = STEP_WIP_WAIT;
  537. as_add_step(as, step);
  538. }
  539. static void as_add_set_dir(struct algorithm_steps *as, bool dir)
  540. {
  541. uint8_t *step = malloc(2);
  542. step[0] = STEP_SET_DIR;
  543. step[1] = FESPI_FMT_DIR(dir);
  544. as_add_step(as, step);
  545. }
  546. /* This should write something less than or equal to a page.*/
  547. static int steps_add_buffer_write(struct algorithm_steps *as,
  548. const uint8_t *buffer, uint32_t chip_offset, uint32_t len)
  549. {
  550. if (chip_offset & 0xFF000000) {
  551. LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x",
  552. chip_offset);
  553. return ERROR_FAIL;
  554. }
  555. as_add_tx1(as, SPIFLASH_WRITE_ENABLE);
  556. as_add_txwm_wait(as);
  557. as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
  558. uint8_t setup[] = {
  559. SPIFLASH_PAGE_PROGRAM,
  560. chip_offset >> 16,
  561. chip_offset >> 8,
  562. chip_offset,
  563. };
  564. as_add_tx(as, sizeof(setup), setup);
  565. as_add_tx(as, len, buffer);
  566. as_add_txwm_wait(as);
  567. as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
  568. /* fespi_wip() */
  569. as_add_set_dir(as, FESPI_DIR_RX);
  570. as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
  571. as_add_wip_wait(as);
  572. as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
  573. as_add_set_dir(as, FESPI_DIR_TX);
  574. return ERROR_OK;
  575. }
  576. static int steps_execute(struct algorithm_steps *as,
  577. struct flash_bank *bank, struct working_area *algorithm_wa,
  578. struct working_area *data_wa)
  579. {
  580. struct target *target = bank->target;
  581. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  582. uint32_t ctrl_base = fespi_info->ctrl_base;
  583. int xlen = riscv_xlen(target);
  584. struct reg_param reg_params[2];
  585. init_reg_param(&reg_params[0], "a0", xlen, PARAM_OUT);
  586. init_reg_param(&reg_params[1], "a1", xlen, PARAM_OUT);
  587. buf_set_u64(reg_params[0].value, 0, xlen, ctrl_base);
  588. buf_set_u64(reg_params[1].value, 0, xlen, data_wa->address);
  589. int retval = ERROR_OK;
  590. while (!as_empty(as)) {
  591. keep_alive();
  592. uint8_t *data_buf = malloc(data_wa->size);
  593. unsigned bytes = as_compile(as, data_buf, data_wa->size);
  594. retval = target_write_buffer(target, data_wa->address, bytes,
  595. data_buf);
  596. free(data_buf);
  597. if (retval != ERROR_OK) {
  598. LOG_ERROR("Failed to write data to 0x%" TARGET_PRIxADDR ": %d",
  599. data_wa->address, retval);
  600. goto exit;
  601. }
  602. retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
  603. algorithm_wa->address, algorithm_wa->address + 4,
  604. 10000, NULL);
  605. if (retval != ERROR_OK) {
  606. LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
  607. algorithm_wa->address, retval);
  608. goto exit;
  609. }
  610. }
  611. exit:
  612. destroy_reg_param(&reg_params[1]);
  613. destroy_reg_param(&reg_params[0]);
  614. return retval;
  615. }
  616. static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
  617. uint32_t offset, uint32_t count)
  618. {
  619. struct target *target = bank->target;
  620. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  621. uint32_t cur_count, page_size, page_offset;
  622. int sector;
  623. int retval = ERROR_OK;
  624. LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
  625. __func__, offset, count);
  626. if (target->state != TARGET_HALTED) {
  627. LOG_ERROR("Target not halted");
  628. return ERROR_TARGET_NOT_HALTED;
  629. }
  630. if (offset + count > fespi_info->dev->size_in_bytes) {
  631. LOG_WARNING("Write past end of flash. Extra data discarded.");
  632. count = fespi_info->dev->size_in_bytes - offset;
  633. }
  634. /* Check sector protection */
  635. for (sector = 0; sector < bank->num_sectors; sector++) {
  636. /* Start offset in or before this sector? */
  637. /* End offset in or behind this sector? */
  638. if ((offset <
  639. (bank->sectors[sector].offset + bank->sectors[sector].size))
  640. && ((offset + count - 1) >= bank->sectors[sector].offset)
  641. && bank->sectors[sector].is_protected) {
  642. LOG_ERROR("Flash sector %d protected", sector);
  643. return ERROR_FAIL;
  644. }
  645. }
  646. struct working_area *algorithm_wa;
  647. if (target_alloc_working_area(target, sizeof(algorithm_bin),
  648. &algorithm_wa) != ERROR_OK) {
  649. LOG_WARNING("Couldn't allocate %zd-byte working area.",
  650. sizeof(algorithm_bin));
  651. algorithm_wa = NULL;
  652. } else {
  653. retval = target_write_buffer(target, algorithm_wa->address,
  654. sizeof(algorithm_bin), algorithm_bin);
  655. if (retval != ERROR_OK) {
  656. LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
  657. algorithm_wa->address, retval);
  658. target_free_working_area(target, algorithm_wa);
  659. algorithm_wa = NULL;
  660. }
  661. }
  662. struct working_area *data_wa = NULL;
  663. unsigned data_wa_size = 2 * count;
  664. while (1) {
  665. if (data_wa_size < 128) {
  666. LOG_WARNING("Couldn't allocate data working area.");
  667. target_free_working_area(target, algorithm_wa);
  668. algorithm_wa = NULL;
  669. }
  670. if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
  671. ERROR_OK) {
  672. break;
  673. }
  674. data_wa_size /= 2;
  675. }
  676. /* If no valid page_size, use reasonable default. */
  677. page_size = fespi_info->dev->pagesize ?
  678. fespi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
  679. fespi_txwm_wait(bank);
  680. /* Disable Hardware accesses*/
  681. if (fespi_disable_hw_mode(bank) != ERROR_OK)
  682. return ERROR_FAIL;
  683. struct algorithm_steps *as = as_new();
  684. /* poll WIP */
  685. retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
  686. if (retval != ERROR_OK)
  687. goto err;
  688. page_offset = offset % page_size;
  689. /* central part, aligned words */
  690. while (count > 0) {
  691. /* clip block at page boundary */
  692. if (page_offset + count > page_size)
  693. cur_count = page_size - page_offset;
  694. else
  695. cur_count = count;
  696. if (algorithm_wa)
  697. retval = steps_add_buffer_write(as, buffer, offset, cur_count);
  698. else
  699. retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
  700. if (retval != ERROR_OK)
  701. goto err;
  702. page_offset = 0;
  703. buffer += cur_count;
  704. offset += cur_count;
  705. count -= cur_count;
  706. }
  707. if (algorithm_wa)
  708. retval = steps_execute(as, bank, algorithm_wa, data_wa);
  709. err:
  710. if (algorithm_wa) {
  711. target_free_working_area(target, data_wa);
  712. target_free_working_area(target, algorithm_wa);
  713. }
  714. as_delete(as);
  715. /* Switch to HW mode before return to prompt */
  716. if (fespi_enable_hw_mode(bank) != ERROR_OK)
  717. return ERROR_FAIL;
  718. return retval;
  719. }
  720. /* Return ID of flash device */
  721. /* On exit, SW mode is kept */
  722. static int fespi_read_flash_id(struct flash_bank *bank, uint32_t *id)
  723. {
  724. struct target *target = bank->target;
  725. int retval;
  726. if (target->state != TARGET_HALTED) {
  727. LOG_ERROR("Target not halted");
  728. return ERROR_TARGET_NOT_HALTED;
  729. }
  730. fespi_txwm_wait(bank);
  731. /* poll WIP */
  732. retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
  733. if (retval != ERROR_OK)
  734. return retval;
  735. fespi_set_dir(bank, FESPI_DIR_RX);
  736. /* Send SPI command "read ID" */
  737. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
  738. return ERROR_FAIL;
  739. fespi_tx(bank, SPIFLASH_READ_ID);
  740. /* Send dummy bytes to actually read the ID.*/
  741. fespi_tx(bank, 0);
  742. fespi_tx(bank, 0);
  743. fespi_tx(bank, 0);
  744. /* read ID from Receive Register */
  745. *id = 0;
  746. if (fespi_rx(bank, NULL) != ERROR_OK)
  747. return ERROR_FAIL;
  748. uint8_t rx;
  749. if (fespi_rx(bank, &rx) != ERROR_OK)
  750. return ERROR_FAIL;
  751. *id = rx;
  752. if (fespi_rx(bank, &rx) != ERROR_OK)
  753. return ERROR_FAIL;
  754. *id |= (rx << 8);
  755. if (fespi_rx(bank, &rx) != ERROR_OK)
  756. return ERROR_FAIL;
  757. *id |= (rx << 16);
  758. if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
  759. return ERROR_FAIL;
  760. fespi_set_dir(bank, FESPI_DIR_TX);
  761. return ERROR_OK;
  762. }
  763. static int fespi_probe(struct flash_bank *bank)
  764. {
  765. struct target *target = bank->target;
  766. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  767. struct flash_sector *sectors;
  768. uint32_t id = 0; /* silence uninitialized warning */
  769. const struct fespi_target *target_device;
  770. int retval;
  771. uint32_t sectorsize;
  772. if (fespi_info->probed)
  773. free(bank->sectors);
  774. fespi_info->probed = 0;
  775. if (fespi_info->ctrl_base == 0) {
  776. for (target_device = target_devices ; target_device->name ; ++target_device)
  777. if (target_device->tap_idcode == target->tap->idcode)
  778. break;
  779. if (!target_device->name) {
  780. LOG_ERROR("Device ID 0x%" PRIx32 " is not known as FESPI capable",
  781. target->tap->idcode);
  782. return ERROR_FAIL;
  783. }
  784. fespi_info->ctrl_base = target_device->ctrl_base;
  785. LOG_DEBUG("Valid FESPI on device %s at address 0x%" PRIx32,
  786. target_device->name, bank->base);
  787. } else {
  788. LOG_DEBUG("Assuming FESPI as specified at address 0x%" TARGET_PRIxADDR
  789. " with ctrl at 0x%x", fespi_info->ctrl_base, bank->base);
  790. }
  791. /* read and decode flash ID; returns in SW mode */
  792. if (fespi_write_reg(bank, FESPI_REG_TXCTRL, FESPI_TXWM(1)) != ERROR_OK)
  793. return ERROR_FAIL;
  794. fespi_set_dir(bank, FESPI_DIR_TX);
  795. /* Disable Hardware accesses*/
  796. if (fespi_disable_hw_mode(bank) != ERROR_OK)
  797. return ERROR_FAIL;
  798. retval = fespi_read_flash_id(bank, &id);
  799. if (fespi_enable_hw_mode(bank) != ERROR_OK)
  800. return ERROR_FAIL;
  801. if (retval != ERROR_OK)
  802. return retval;
  803. fespi_info->dev = NULL;
  804. for (const struct flash_device *p = flash_devices; p->name ; p++)
  805. if (p->device_id == id) {
  806. fespi_info->dev = p;
  807. break;
  808. }
  809. if (!fespi_info->dev) {
  810. LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
  811. return ERROR_FAIL;
  812. }
  813. LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
  814. fespi_info->dev->name, fespi_info->dev->device_id);
  815. /* Set correct size value */
  816. bank->size = fespi_info->dev->size_in_bytes;
  817. if (bank->size <= (1UL << 16))
  818. LOG_WARNING("device needs 2-byte addresses - not implemented");
  819. if (bank->size > (1UL << 24))
  820. LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
  821. /* if no sectors, treat whole bank as single sector */
  822. sectorsize = fespi_info->dev->sectorsize ?
  823. fespi_info->dev->sectorsize : fespi_info->dev->size_in_bytes;
  824. /* create and fill sectors array */
  825. bank->num_sectors = fespi_info->dev->size_in_bytes / sectorsize;
  826. sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
  827. if (sectors == NULL) {
  828. LOG_ERROR("not enough memory");
  829. return ERROR_FAIL;
  830. }
  831. for (int sector = 0; sector < bank->num_sectors; sector++) {
  832. sectors[sector].offset = sector * sectorsize;
  833. sectors[sector].size = sectorsize;
  834. sectors[sector].is_erased = -1;
  835. sectors[sector].is_protected = 0;
  836. }
  837. bank->sectors = sectors;
  838. fespi_info->probed = 1;
  839. return ERROR_OK;
  840. }
  841. static int fespi_auto_probe(struct flash_bank *bank)
  842. {
  843. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  844. if (fespi_info->probed)
  845. return ERROR_OK;
  846. return fespi_probe(bank);
  847. }
  848. static int fespi_protect_check(struct flash_bank *bank)
  849. {
  850. /* Nothing to do. Protection is only handled in SW. */
  851. return ERROR_OK;
  852. }
  853. static int get_fespi_info(struct flash_bank *bank, char *buf, int buf_size)
  854. {
  855. struct fespi_flash_bank *fespi_info = bank->driver_priv;
  856. if (!(fespi_info->probed)) {
  857. snprintf(buf, buf_size,
  858. "\nFESPI flash bank not probed yet\n");
  859. return ERROR_OK;
  860. }
  861. snprintf(buf, buf_size, "\nFESPI flash information:\n"
  862. " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
  863. fespi_info->dev->name, fespi_info->dev->device_id);
  864. return ERROR_OK;
  865. }
  866. struct flash_driver fespi_flash = {
  867. .name = "fespi",
  868. .flash_bank_command = fespi_flash_bank_command,
  869. .erase = fespi_erase,
  870. .protect = fespi_protect,
  871. .write = fespi_write,
  872. .read = default_flash_read,
  873. .probe = fespi_probe,
  874. .auto_probe = fespi_auto_probe,
  875. .erase_check = default_flash_blank_check,
  876. .protect_check = fespi_protect_check,
  877. .info = get_fespi_info,
  878. .free_driver_priv = default_flash_free_driver_priv
  879. };