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76 lines
3.0 KiB

  1. ################################################################################
  2. #
  3. # Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
  4. #
  5. # Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
  6. # OSCSEL configured for external 32.768 kHz crystal
  7. #
  8. # 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
  9. #
  10. ################################################################################
  11. # We add to the minimal configuration.
  12. source [find target/at91sam9rl.cfg]
  13. $_TARGETNAME configure -event reset-start {
  14. # At reset CPU runs at 32.768 kHz.
  15. # JTAG Frequency must be 6 times slower if RCLK is not supported.
  16. jtag_rclk 5
  17. halt
  18. # RSTC_MR : enable user reset, MMU may be enabled... use physical address
  19. mww phys 0xfffffd08 0xa5000501
  20. }
  21. $_TARGETNAME configure -event reset-init {
  22. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
  23. mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
  24. sleep 20 # wait 20 ms
  25. mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
  26. sleep 10 # wait 10 ms
  27. mww 0xfffffc28 0x2031bf03 # CKGR_PLLR: Set PLL Register for 200 MHz
  28. sleep 20 # wait 20 ms
  29. mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
  30. sleep 10 # wait 10 ms
  31. mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLL is selected (100 MHz)
  32. sleep 10 # wait 10 ms
  33. # Increase JTAG Speed to 6 MHz if RCLK is not supported
  34. jtag_rclk 6000
  35. arm7_9 dcc_downloads enable # Enable faster DCC downloads
  36. mww 0xfffff670 0xffff0000 # PIO_ASR : Select peripheral function for D16..D31 (PIOB)
  37. mww 0xfffff604 0xffff0000 # PIO_PDR : Disable PIO function for D16..D31 (PIOB)
  38. mww 0xffffef20 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
  39. mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
  40. mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
  41. mww 0x20000000 0
  42. mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
  43. mww 0x20000000 0
  44. mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  45. mww 0x20000000 0
  46. mww 0xffffea00 0x4
  47. mww 0x20000000 0
  48. mww 0xffffea00 0x4
  49. mww 0x20000000 0
  50. mww 0xffffea00 0x4
  51. mww 0x20000000 0
  52. mww 0xffffea00 0x4
  53. mww 0x20000000 0
  54. mww 0xffffea00 0x4
  55. mww 0x20000000 0
  56. mww 0xffffea00 0x4
  57. mww 0x20000000 0
  58. mww 0xffffea00 0x4
  59. mww 0x20000000 0
  60. mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
  61. mww 0x20000000 0
  62. mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
  63. mww 0x20000000 0
  64. mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
  65. }