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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "etm.h"
  24. #include "etb.h"
  25. #include "image.h"
  26. #include "arm7_9_common.h"
  27. #include "arm_disassembler.h"
  28. /*
  29. * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  30. *
  31. * ETM modules collect instruction and/or data trace information, compress
  32. * it, and transfer it to a debugging host through either a (buffered) trace
  33. * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  34. *
  35. * There are several generations of these modules. Original versions have
  36. * JTAG access through a dedicated scan chain. Recent versions have added
  37. * access via coprocessor instructions, memory addressing, and the ARM Debug
  38. * Interface v5 (ADIv5); and phased out direct JTAG access.
  39. *
  40. * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  41. * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
  42. * implying non-JTAG connectivity options.
  43. *
  44. * Relevant documentation includes:
  45. * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  46. * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  47. * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  48. */
  49. #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
  50. enum {
  51. RO, /* read/only */
  52. WO, /* write/only */
  53. RW, /* read/write */
  54. };
  55. struct etm_reg_info {
  56. uint8_t addr;
  57. uint8_t size; /* low-N of 32 bits */
  58. uint8_t mode; /* RO, WO, RW */
  59. uint8_t bcd_vers; /* 1.0, 2.0, etc */
  60. char *name;
  61. };
  62. /*
  63. * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  64. * (Or on some processors, through coprocessor operations.)
  65. * Newer versions of ETM make some W/O registers R/W, and
  66. * provide definitions for some previously-unused bits.
  67. */
  68. /* basic registers that are always there given the right ETM version */
  69. static const struct etm_reg_info etm_core[] = {
  70. /* NOTE: we "know" ETM_CONFIG is listed first */
  71. { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  72. /* ETM Trace Registers */
  73. { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  74. { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  75. { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
  76. { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
  77. { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
  78. /* TraceEnable configuration */
  79. { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  80. { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  81. { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  82. { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  83. /* ViewData configuration (data trace) */
  84. { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  85. { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
  86. { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
  87. { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
  88. /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
  89. { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
  90. { 0x79, 32, RO, 0x20, "ETM_id", },
  91. };
  92. static const struct etm_reg_info etm_fifofull[] = {
  93. /* FIFOFULL configuration */
  94. { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
  95. { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
  96. };
  97. static const struct etm_reg_info etm_addr_comp[] = {
  98. /* Address comparator register pairs */
  99. #define ADDR_COMPARATOR(i) \
  100. { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
  101. "ETM_addr_" #i "_comparator_value", }, \
  102. { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
  103. "ETM_addr_" #i "_access_type", }
  104. ADDR_COMPARATOR(1),
  105. ADDR_COMPARATOR(2),
  106. ADDR_COMPARATOR(3),
  107. ADDR_COMPARATOR(4),
  108. ADDR_COMPARATOR(5),
  109. ADDR_COMPARATOR(6),
  110. ADDR_COMPARATOR(7),
  111. ADDR_COMPARATOR(8),
  112. ADDR_COMPARATOR(9),
  113. ADDR_COMPARATOR(10),
  114. ADDR_COMPARATOR(11),
  115. ADDR_COMPARATOR(12),
  116. ADDR_COMPARATOR(13),
  117. ADDR_COMPARATOR(14),
  118. ADDR_COMPARATOR(15),
  119. ADDR_COMPARATOR(16),
  120. #undef ADDR_COMPARATOR
  121. };
  122. static const struct etm_reg_info etm_data_comp[] = {
  123. /* Data Value Comparators (NOTE: odd addresses are reserved) */
  124. #define DATA_COMPARATOR(i) \
  125. { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
  126. "ETM_data_" #i "_comparator_value", }, \
  127. { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
  128. "ETM_data_" #i "_comparator_mask", }
  129. DATA_COMPARATOR(1),
  130. DATA_COMPARATOR(2),
  131. DATA_COMPARATOR(3),
  132. DATA_COMPARATOR(4),
  133. DATA_COMPARATOR(5),
  134. DATA_COMPARATOR(6),
  135. DATA_COMPARATOR(7),
  136. DATA_COMPARATOR(8),
  137. #undef DATA_COMPARATOR
  138. };
  139. static const struct etm_reg_info etm_counters[] = {
  140. #define ETM_COUNTER(i) \
  141. { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
  142. "ETM_counter_" #i "_reload_value", }, \
  143. { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
  144. "ETM_counter_" #i "_enable", }, \
  145. { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
  146. "ETM_counter_" #i "_reload_event", }, \
  147. { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
  148. "ETM_counter_" #i "_value", }
  149. ETM_COUNTER(1),
  150. ETM_COUNTER(2),
  151. ETM_COUNTER(3),
  152. ETM_COUNTER(4),
  153. #undef ETM_COUNTER
  154. };
  155. static const struct etm_reg_info etm_sequencer[] = {
  156. #define ETM_SEQ(i) \
  157. { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
  158. "ETM_sequencer_event" #i, }
  159. ETM_SEQ(0), /* 1->2 */
  160. ETM_SEQ(1), /* 2->1 */
  161. ETM_SEQ(2), /* 2->3 */
  162. ETM_SEQ(3), /* 3->1 */
  163. ETM_SEQ(4), /* 3->2 */
  164. ETM_SEQ(5), /* 1->3 */
  165. #undef ETM_SEQ
  166. /* 0x66 reserved */
  167. { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
  168. };
  169. static const struct etm_reg_info etm_outputs[] = {
  170. #define ETM_OUTPUT(i) \
  171. { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
  172. "ETM_external_output" #i, }
  173. ETM_OUTPUT(1),
  174. ETM_OUTPUT(2),
  175. ETM_OUTPUT(3),
  176. ETM_OUTPUT(4),
  177. #undef ETM_OUTPUT
  178. };
  179. #if 0
  180. /* registers from 0x6c..0x7f were added after ETMv1.3 */
  181. /* Context ID Comparators */
  182. { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
  183. { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
  184. { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
  185. { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
  186. #endif
  187. static int etm_reg_arch_type = -1;
  188. static int etm_get_reg(reg_t *reg);
  189. static int etm_read_reg_w_check(reg_t *reg,
  190. uint8_t* check_value, uint8_t* check_mask);
  191. static int etm_register_user_commands(struct command_context_s *cmd_ctx);
  192. static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
  193. static int etm_write_reg(reg_t *reg, uint32_t value);
  194. static command_t *etm_cmd;
  195. /* Look up register by ID ... most ETM instances only
  196. * support a subset of the possible registers.
  197. */
  198. static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
  199. {
  200. reg_cache_t *cache = etm_ctx->reg_cache;
  201. int i;
  202. for (i = 0; i < cache->num_regs; i++) {
  203. struct etm_reg_s *reg = cache->reg_list[i].arch_info;
  204. if (reg->reg_info->addr == id)
  205. return &cache->reg_list[i];
  206. }
  207. /* caller asking for nonexistent register is a bug! */
  208. /* REVISIT say which of the N targets was involved */
  209. LOG_ERROR("ETM: register 0x%02x not available", id);
  210. return NULL;
  211. }
  212. static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
  213. reg_cache_t *cache, etm_reg_t *ereg,
  214. const struct etm_reg_info *r, unsigned nreg)
  215. {
  216. reg_t *reg = cache->reg_list;
  217. reg += cache->num_regs;
  218. ereg += cache->num_regs;
  219. /* add up to "nreg" registers from "r", if supported by this
  220. * version of the ETM, to the specified cache.
  221. */
  222. for (; nreg--; r++) {
  223. /* this ETM may be too old to have some registers */
  224. if (r->bcd_vers > bcd_vers)
  225. continue;
  226. reg->name = r->name;
  227. reg->size = r->size;
  228. reg->value = &ereg->value;
  229. reg->arch_info = ereg;
  230. reg->arch_type = etm_reg_arch_type;
  231. reg++;
  232. cache->num_regs++;
  233. ereg->reg_info = r;
  234. ereg->jtag_info = jtag_info;
  235. ereg++;
  236. }
  237. }
  238. reg_cache_t *etm_build_reg_cache(target_t *target,
  239. arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
  240. {
  241. reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  242. reg_t *reg_list = NULL;
  243. etm_reg_t *arch_info = NULL;
  244. unsigned bcd_vers, config;
  245. /* register a register arch-type for etm registers only once */
  246. if (etm_reg_arch_type == -1)
  247. etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
  248. etm_set_reg_w_exec);
  249. /* the actual registers are kept in two arrays */
  250. reg_list = calloc(128, sizeof(reg_t));
  251. arch_info = calloc(128, sizeof(etm_reg_t));
  252. /* fill in values for the reg cache */
  253. reg_cache->name = "etm registers";
  254. reg_cache->next = NULL;
  255. reg_cache->reg_list = reg_list;
  256. reg_cache->num_regs = 0;
  257. /* add ETM_CONFIG, then parse its values to see
  258. * which other registers exist in this ETM
  259. */
  260. etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
  261. etm_core, 1);
  262. etm_get_reg(reg_list);
  263. etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
  264. config = etm_ctx->config;
  265. /* figure ETM version then add base registers */
  266. if (config & (1 << 31)) {
  267. bcd_vers = 0x20;
  268. LOG_WARNING("ETMv2+ support is incomplete");
  269. /* REVISIT read ID register, distinguish ETMv3.3 etc;
  270. * don't presume trace start/stop support is present;
  271. * and include any context ID comparator registers.
  272. */
  273. } else {
  274. switch (config >> 28) {
  275. case 7:
  276. case 5:
  277. case 3:
  278. bcd_vers = 0x13;
  279. break;
  280. case 4:
  281. case 2:
  282. bcd_vers = 0x12;
  283. break;
  284. case 1:
  285. bcd_vers = 0x11;
  286. break;
  287. case 0:
  288. bcd_vers = 0x10;
  289. break;
  290. default:
  291. LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
  292. free(reg_cache);
  293. free(reg_list);
  294. free(arch_info);
  295. return ERROR_OK;
  296. }
  297. }
  298. etm_ctx->bcd_vers = bcd_vers;
  299. LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
  300. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  301. etm_core + 1, ARRAY_SIZE(etm_core) - 1);
  302. /* address and data comparators; counters; outputs */
  303. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  304. etm_addr_comp, 4 * (0x0f & (config >> 0)));
  305. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  306. etm_data_comp, 2 * (0x0f & (config >> 4)));
  307. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  308. etm_counters, 4 * (0x07 & (config >> 13)));
  309. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  310. etm_outputs, (0x07 & (config >> 20)));
  311. /* FIFOFULL presence is optional
  312. * REVISIT for ETMv1.2 and later, don't bother adding this
  313. * unless ETM_SYS_CONFIG says it's also *supported* ...
  314. */
  315. if (config & (1 << 23))
  316. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  317. etm_fifofull, ARRAY_SIZE(etm_fifofull));
  318. /* sequencer is optional (for state-dependant triggering) */
  319. if (config & (1 << 16))
  320. etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
  321. etm_sequencer, ARRAY_SIZE(etm_sequencer));
  322. /* REVISIT could realloc and likely save half the memory
  323. * in the two chunks we allocated...
  324. */
  325. /* the ETM might have an ETB connected */
  326. if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
  327. {
  328. etb_t *etb = etm_ctx->capture_driver_priv;
  329. if (!etb)
  330. {
  331. LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
  332. free(reg_cache);
  333. free(reg_list);
  334. free(arch_info);
  335. return ERROR_OK;
  336. }
  337. reg_cache->next = etb_build_reg_cache(etb);
  338. etb->reg_cache = reg_cache->next;
  339. }
  340. return reg_cache;
  341. }
  342. static int etm_read_reg(reg_t *reg)
  343. {
  344. return etm_read_reg_w_check(reg, NULL, NULL);
  345. }
  346. static int etm_store_reg(reg_t *reg)
  347. {
  348. return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
  349. }
  350. int etm_setup(target_t *target)
  351. {
  352. int retval;
  353. uint32_t etm_ctrl_value;
  354. armv4_5_common_t *armv4_5 = target->arch_info;
  355. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  356. etm_context_t *etm_ctx = arm7_9->etm_ctx;
  357. reg_t *etm_ctrl_reg;
  358. etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
  359. if (!etm_ctrl_reg)
  360. return ERROR_OK;
  361. /* initialize some ETM control register settings */
  362. etm_get_reg(etm_ctrl_reg);
  363. etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
  364. /* clear the ETM powerdown bit (0) */
  365. etm_ctrl_value &= ~0x1;
  366. /* configure port width (6:4), mode (17:16) and clocking (13) */
  367. etm_ctrl_value = (etm_ctrl_value &
  368. ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
  369. | etm_ctx->portmode;
  370. buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
  371. etm_store_reg(etm_ctrl_reg);
  372. if ((retval = jtag_execute_queue()) != ERROR_OK)
  373. return retval;
  374. if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
  375. {
  376. LOG_ERROR("ETM capture driver initialization failed");
  377. return retval;
  378. }
  379. return ERROR_OK;
  380. }
  381. static int etm_get_reg(reg_t *reg)
  382. {
  383. int retval;
  384. if ((retval = etm_read_reg(reg)) != ERROR_OK)
  385. {
  386. LOG_ERROR("BUG: error scheduling etm register read");
  387. return retval;
  388. }
  389. if ((retval = jtag_execute_queue()) != ERROR_OK)
  390. {
  391. LOG_ERROR("register read failed");
  392. return retval;
  393. }
  394. return ERROR_OK;
  395. }
  396. static int etm_read_reg_w_check(reg_t *reg,
  397. uint8_t* check_value, uint8_t* check_mask)
  398. {
  399. etm_reg_t *etm_reg = reg->arch_info;
  400. const struct etm_reg_info *r = etm_reg->reg_info;
  401. uint8_t reg_addr = r->addr & 0x7f;
  402. scan_field_t fields[3];
  403. if (etm_reg->reg_info->mode == WO) {
  404. LOG_ERROR("BUG: can't read write-only register %s", r->name);
  405. return ERROR_INVALID_ARGUMENTS;
  406. }
  407. LOG_DEBUG("%s (%u)", r->name, reg_addr);
  408. jtag_set_end_state(TAP_IDLE);
  409. arm_jtag_scann(etm_reg->jtag_info, 0x6);
  410. arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
  411. fields[0].tap = etm_reg->jtag_info->tap;
  412. fields[0].num_bits = 32;
  413. fields[0].out_value = reg->value;
  414. fields[0].in_value = NULL;
  415. fields[0].check_value = NULL;
  416. fields[0].check_mask = NULL;
  417. fields[1].tap = etm_reg->jtag_info->tap;
  418. fields[1].num_bits = 7;
  419. fields[1].out_value = malloc(1);
  420. buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
  421. fields[1].in_value = NULL;
  422. fields[1].check_value = NULL;
  423. fields[1].check_mask = NULL;
  424. fields[2].tap = etm_reg->jtag_info->tap;
  425. fields[2].num_bits = 1;
  426. fields[2].out_value = malloc(1);
  427. buf_set_u32(fields[2].out_value, 0, 1, 0);
  428. fields[2].in_value = NULL;
  429. fields[2].check_value = NULL;
  430. fields[2].check_mask = NULL;
  431. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  432. fields[0].in_value = reg->value;
  433. fields[0].check_value = check_value;
  434. fields[0].check_mask = check_mask;
  435. jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
  436. free(fields[1].out_value);
  437. free(fields[2].out_value);
  438. return ERROR_OK;
  439. }
  440. static int etm_set_reg(reg_t *reg, uint32_t value)
  441. {
  442. int retval;
  443. if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
  444. {
  445. LOG_ERROR("BUG: error scheduling etm register write");
  446. return retval;
  447. }
  448. buf_set_u32(reg->value, 0, reg->size, value);
  449. reg->valid = 1;
  450. reg->dirty = 0;
  451. return ERROR_OK;
  452. }
  453. static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
  454. {
  455. int retval;
  456. etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
  457. if ((retval = jtag_execute_queue()) != ERROR_OK)
  458. {
  459. LOG_ERROR("register write failed");
  460. return retval;
  461. }
  462. return ERROR_OK;
  463. }
  464. static int etm_write_reg(reg_t *reg, uint32_t value)
  465. {
  466. etm_reg_t *etm_reg = reg->arch_info;
  467. const struct etm_reg_info *r = etm_reg->reg_info;
  468. uint8_t reg_addr = r->addr & 0x7f;
  469. scan_field_t fields[3];
  470. if (etm_reg->reg_info->mode == RO) {
  471. LOG_ERROR("BUG: can't write read--only register %s", r->name);
  472. return ERROR_INVALID_ARGUMENTS;
  473. }
  474. LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
  475. jtag_set_end_state(TAP_IDLE);
  476. arm_jtag_scann(etm_reg->jtag_info, 0x6);
  477. arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
  478. fields[0].tap = etm_reg->jtag_info->tap;
  479. fields[0].num_bits = 32;
  480. uint8_t tmp1[4];
  481. fields[0].out_value = tmp1;
  482. buf_set_u32(fields[0].out_value, 0, 32, value);
  483. fields[0].in_value = NULL;
  484. fields[1].tap = etm_reg->jtag_info->tap;
  485. fields[1].num_bits = 7;
  486. uint8_t tmp2;
  487. fields[1].out_value = &tmp2;
  488. buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
  489. fields[1].in_value = NULL;
  490. fields[2].tap = etm_reg->jtag_info->tap;
  491. fields[2].num_bits = 1;
  492. uint8_t tmp3;
  493. fields[2].out_value = &tmp3;
  494. buf_set_u32(fields[2].out_value, 0, 1, 1);
  495. fields[2].in_value = NULL;
  496. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  497. return ERROR_OK;
  498. }
  499. /* ETM trace analysis functionality
  500. *
  501. */
  502. extern etm_capture_driver_t etm_dummy_capture_driver;
  503. #if BUILD_OOCD_TRACE == 1
  504. extern etm_capture_driver_t oocd_trace_capture_driver;
  505. #endif
  506. static etm_capture_driver_t *etm_capture_drivers[] =
  507. {
  508. &etb_capture_driver,
  509. &etm_dummy_capture_driver,
  510. #if BUILD_OOCD_TRACE == 1
  511. &oocd_trace_capture_driver,
  512. #endif
  513. NULL
  514. };
  515. static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
  516. {
  517. int i;
  518. int section = -1;
  519. uint32_t size_read;
  520. uint32_t opcode;
  521. int retval;
  522. if (!ctx->image)
  523. return ERROR_TRACE_IMAGE_UNAVAILABLE;
  524. /* search for the section the current instruction belongs to */
  525. for (i = 0; i < ctx->image->num_sections; i++)
  526. {
  527. if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
  528. (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
  529. {
  530. section = i;
  531. break;
  532. }
  533. }
  534. if (section == -1)
  535. {
  536. /* current instruction couldn't be found in the image */
  537. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  538. }
  539. if (ctx->core_state == ARMV4_5_STATE_ARM)
  540. {
  541. uint8_t buf[4];
  542. if ((retval = image_read_section(ctx->image, section,
  543. ctx->current_pc - ctx->image->sections[section].base_address,
  544. 4, buf, &size_read)) != ERROR_OK)
  545. {
  546. LOG_ERROR("error while reading instruction: %i", retval);
  547. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  548. }
  549. opcode = target_buffer_get_u32(ctx->target, buf);
  550. arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
  551. }
  552. else if (ctx->core_state == ARMV4_5_STATE_THUMB)
  553. {
  554. uint8_t buf[2];
  555. if ((retval = image_read_section(ctx->image, section,
  556. ctx->current_pc - ctx->image->sections[section].base_address,
  557. 2, buf, &size_read)) != ERROR_OK)
  558. {
  559. LOG_ERROR("error while reading instruction: %i", retval);
  560. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  561. }
  562. opcode = target_buffer_get_u16(ctx->target, buf);
  563. thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
  564. }
  565. else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
  566. {
  567. LOG_ERROR("BUG: tracing of jazelle code not supported");
  568. exit(-1);
  569. }
  570. else
  571. {
  572. LOG_ERROR("BUG: unknown core state encountered");
  573. exit(-1);
  574. }
  575. return ERROR_OK;
  576. }
  577. static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
  578. {
  579. while (ctx->data_index < ctx->trace_depth)
  580. {
  581. /* if the caller specified an address packet offset, skip until the
  582. * we reach the n-th cycle marked with tracesync */
  583. if (apo > 0)
  584. {
  585. if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
  586. apo--;
  587. if (apo > 0)
  588. {
  589. ctx->data_index++;
  590. ctx->data_half = 0;
  591. }
  592. continue;
  593. }
  594. /* no tracedata output during a TD cycle
  595. * or in a trigger cycle */
  596. if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
  597. || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
  598. {
  599. ctx->data_index++;
  600. ctx->data_half = 0;
  601. continue;
  602. }
  603. if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
  604. {
  605. if (ctx->data_half == 0)
  606. {
  607. *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
  608. ctx->data_half = 1;
  609. }
  610. else
  611. {
  612. *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
  613. ctx->data_half = 0;
  614. ctx->data_index++;
  615. }
  616. }
  617. else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
  618. {
  619. *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
  620. ctx->data_index++;
  621. }
  622. else
  623. {
  624. /* on a 4-bit port, a packet will be output during two consecutive cycles */
  625. if (ctx->data_index > (ctx->trace_depth - 2))
  626. return -1;
  627. *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
  628. *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
  629. ctx->data_index += 2;
  630. }
  631. return 0;
  632. }
  633. return -1;
  634. }
  635. static int etmv1_branch_address(etm_context_t *ctx)
  636. {
  637. int retval;
  638. uint8_t packet;
  639. int shift = 0;
  640. int apo;
  641. uint32_t i;
  642. /* quit analysis if less than two cycles are left in the trace
  643. * because we can't extract the APO */
  644. if (ctx->data_index > (ctx->trace_depth - 2))
  645. return -1;
  646. /* a BE could be output during an APO cycle, skip the current
  647. * and continue with the new one */
  648. if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
  649. return 1;
  650. if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
  651. return 2;
  652. /* address packet offset encoded in the next two cycles' pipestat bits */
  653. apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
  654. apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
  655. /* count number of tracesync cycles between current pipe_index and data_index
  656. * i.e. the number of tracesyncs that data_index already passed by
  657. * to subtract them from the APO */
  658. for (i = ctx->pipe_index; i < ctx->data_index; i++)
  659. {
  660. if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
  661. apo--;
  662. }
  663. /* extract up to four 7-bit packets */
  664. do {
  665. if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
  666. return -1;
  667. ctx->last_branch &= ~(0x7f << shift);
  668. ctx->last_branch |= (packet & 0x7f) << shift;
  669. shift += 7;
  670. } while ((packet & 0x80) && (shift < 28));
  671. /* one last packet holding 4 bits of the address, plus the branch reason code */
  672. if ((shift == 28) && (packet & 0x80))
  673. {
  674. if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
  675. return -1;
  676. ctx->last_branch &= 0x0fffffff;
  677. ctx->last_branch |= (packet & 0x0f) << 28;
  678. ctx->last_branch_reason = (packet & 0x70) >> 4;
  679. shift += 4;
  680. }
  681. else
  682. {
  683. ctx->last_branch_reason = 0;
  684. }
  685. if (shift == 32)
  686. {
  687. ctx->pc_ok = 1;
  688. }
  689. /* if a full address was output, we might have branched into Jazelle state */
  690. if ((shift == 32) && (packet & 0x80))
  691. {
  692. ctx->core_state = ARMV4_5_STATE_JAZELLE;
  693. }
  694. else
  695. {
  696. /* if we didn't branch into Jazelle state, the current processor state is
  697. * encoded in bit 0 of the branch target address */
  698. if (ctx->last_branch & 0x1)
  699. {
  700. ctx->core_state = ARMV4_5_STATE_THUMB;
  701. ctx->last_branch &= ~0x1;
  702. }
  703. else
  704. {
  705. ctx->core_state = ARMV4_5_STATE_ARM;
  706. ctx->last_branch &= ~0x3;
  707. }
  708. }
  709. return 0;
  710. }
  711. static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
  712. {
  713. int j;
  714. uint8_t buf[4];
  715. int retval;
  716. for (j = 0; j < size; j++)
  717. {
  718. if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
  719. return -1;
  720. }
  721. if (size == 8)
  722. {
  723. LOG_ERROR("TODO: add support for 64-bit values");
  724. return -1;
  725. }
  726. else if (size == 4)
  727. *data = target_buffer_get_u32(ctx->target, buf);
  728. else if (size == 2)
  729. *data = target_buffer_get_u16(ctx->target, buf);
  730. else if (size == 1)
  731. *data = buf[0];
  732. else
  733. return -1;
  734. return 0;
  735. }
  736. static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
  737. {
  738. int retval;
  739. arm_instruction_t instruction;
  740. /* read the trace data if it wasn't read already */
  741. if (ctx->trace_depth == 0)
  742. ctx->capture_driver->read_trace(ctx);
  743. /* start at the beginning of the captured trace */
  744. ctx->pipe_index = 0;
  745. ctx->data_index = 0;
  746. ctx->data_half = 0;
  747. /* neither the PC nor the data pointer are valid */
  748. ctx->pc_ok = 0;
  749. ctx->ptr_ok = 0;
  750. while (ctx->pipe_index < ctx->trace_depth)
  751. {
  752. uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
  753. uint32_t next_pc = ctx->current_pc;
  754. uint32_t old_data_index = ctx->data_index;
  755. uint32_t old_data_half = ctx->data_half;
  756. uint32_t old_index = ctx->pipe_index;
  757. uint32_t last_instruction = ctx->last_instruction;
  758. uint32_t cycles = 0;
  759. int current_pc_ok = ctx->pc_ok;
  760. if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
  761. {
  762. command_print(cmd_ctx, "--- trigger ---");
  763. }
  764. /* instructions execute in IE/D or BE/D cycles */
  765. if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
  766. ctx->last_instruction = ctx->pipe_index;
  767. /* if we don't have a valid pc skip until we reach an indirect branch */
  768. if ((!ctx->pc_ok) && (pipestat != STAT_BE))
  769. {
  770. ctx->pipe_index++;
  771. continue;
  772. }
  773. /* any indirect branch could have interrupted instruction flow
  774. * - the branch reason code could indicate a trace discontinuity
  775. * - a branch to the exception vectors indicates an exception
  776. */
  777. if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
  778. {
  779. /* backup current data index, to be able to consume the branch address
  780. * before examining data address and values
  781. */
  782. old_data_index = ctx->data_index;
  783. old_data_half = ctx->data_half;
  784. ctx->last_instruction = ctx->pipe_index;
  785. if ((retval = etmv1_branch_address(ctx)) != 0)
  786. {
  787. /* negative return value from etmv1_branch_address means we ran out of packets,
  788. * quit analysing the trace */
  789. if (retval < 0)
  790. break;
  791. /* a positive return values means the current branch was abandoned,
  792. * and a new branch was encountered in cycle ctx->pipe_index + retval;
  793. */
  794. LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
  795. ctx->pipe_index += retval;
  796. continue;
  797. }
  798. /* skip over APO cycles */
  799. ctx->pipe_index += 2;
  800. switch (ctx->last_branch_reason)
  801. {
  802. case 0x0: /* normal PC change */
  803. next_pc = ctx->last_branch;
  804. break;
  805. case 0x1: /* tracing enabled */
  806. command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
  807. ctx->current_pc = ctx->last_branch;
  808. ctx->pipe_index++;
  809. continue;
  810. break;
  811. case 0x2: /* trace restarted after FIFO overflow */
  812. command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
  813. ctx->current_pc = ctx->last_branch;
  814. ctx->pipe_index++;
  815. continue;
  816. break;
  817. case 0x3: /* exit from debug state */
  818. command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
  819. ctx->current_pc = ctx->last_branch;
  820. ctx->pipe_index++;
  821. continue;
  822. break;
  823. case 0x4: /* periodic synchronization point */
  824. next_pc = ctx->last_branch;
  825. /* if we had no valid PC prior to this synchronization point,
  826. * we have to move on with the next trace cycle
  827. */
  828. if (!current_pc_ok)
  829. {
  830. command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
  831. ctx->current_pc = next_pc;
  832. ctx->pipe_index++;
  833. continue;
  834. }
  835. break;
  836. default: /* reserved */
  837. LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
  838. exit(-1);
  839. break;
  840. }
  841. /* if we got here the branch was a normal PC change
  842. * (or a periodic synchronization point, which means the same for that matter)
  843. * if we didn't accquire a complete PC continue with the next cycle
  844. */
  845. if (!ctx->pc_ok)
  846. continue;
  847. /* indirect branch to the exception vector means an exception occured */
  848. if ((ctx->last_branch <= 0x20)
  849. || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
  850. {
  851. if ((ctx->last_branch & 0xff) == 0x10)
  852. {
  853. command_print(cmd_ctx, "data abort");
  854. }
  855. else
  856. {
  857. command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
  858. ctx->current_pc = ctx->last_branch;
  859. ctx->pipe_index++;
  860. continue;
  861. }
  862. }
  863. }
  864. /* an instruction was executed (or not, depending on the condition flags)
  865. * retrieve it from the image for displaying */
  866. if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
  867. !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
  868. ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
  869. {
  870. if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
  871. {
  872. /* can't continue tracing with no image available */
  873. if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
  874. {
  875. return retval;
  876. }
  877. else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
  878. {
  879. /* TODO: handle incomplete images
  880. * for now we just quit the analsysis*/
  881. return retval;
  882. }
  883. }
  884. cycles = old_index - last_instruction;
  885. }
  886. if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
  887. {
  888. uint32_t new_data_index = ctx->data_index;
  889. uint32_t new_data_half = ctx->data_half;
  890. /* in case of a branch with data, the branch target address was consumed before
  891. * we temporarily go back to the saved data index */
  892. if (pipestat == STAT_BD)
  893. {
  894. ctx->data_index = old_data_index;
  895. ctx->data_half = old_data_half;
  896. }
  897. if (ctx->tracemode & ETMV1_TRACE_ADDR)
  898. {
  899. uint8_t packet;
  900. int shift = 0;
  901. do {
  902. if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
  903. return ERROR_ETM_ANALYSIS_FAILED;
  904. ctx->last_ptr &= ~(0x7f << shift);
  905. ctx->last_ptr |= (packet & 0x7f) << shift;
  906. shift += 7;
  907. } while ((packet & 0x80) && (shift < 32));
  908. if (shift >= 32)
  909. ctx->ptr_ok = 1;
  910. if (ctx->ptr_ok)
  911. {
  912. command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
  913. }
  914. }
  915. if (ctx->tracemode & ETMV1_TRACE_DATA)
  916. {
  917. if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
  918. {
  919. int i;
  920. for (i = 0; i < 16; i++)
  921. {
  922. if (instruction.info.load_store_multiple.register_list & (1 << i))
  923. {
  924. uint32_t data;
  925. if (etmv1_data(ctx, 4, &data) != 0)
  926. return ERROR_ETM_ANALYSIS_FAILED;
  927. command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
  928. }
  929. }
  930. }
  931. else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
  932. {
  933. uint32_t data;
  934. if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
  935. return ERROR_ETM_ANALYSIS_FAILED;
  936. command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
  937. }
  938. }
  939. /* restore data index after consuming BD address and data */
  940. if (pipestat == STAT_BD)
  941. {
  942. ctx->data_index = new_data_index;
  943. ctx->data_half = new_data_half;
  944. }
  945. }
  946. /* adjust PC */
  947. if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
  948. {
  949. if (((instruction.type == ARM_B) ||
  950. (instruction.type == ARM_BL) ||
  951. (instruction.type == ARM_BLX)) &&
  952. (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
  953. {
  954. next_pc = instruction.info.b_bl_bx_blx.target_address;
  955. }
  956. else
  957. {
  958. next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
  959. }
  960. }
  961. else if (pipestat == STAT_IN)
  962. {
  963. next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
  964. }
  965. if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
  966. {
  967. char cycles_text[32] = "";
  968. /* if the trace was captured with cycle accurate tracing enabled,
  969. * output the number of cycles since the last executed instruction
  970. */
  971. if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
  972. {
  973. snprintf(cycles_text, 32, " (%i %s)",
  974. (int)cycles,
  975. (cycles == 1) ? "cycle" : "cycles");
  976. }
  977. command_print(cmd_ctx, "%s%s%s",
  978. instruction.text,
  979. (pipestat == STAT_IN) ? " (not executed)" : "",
  980. cycles_text);
  981. ctx->current_pc = next_pc;
  982. /* packets for an instruction don't start on or before the preceding
  983. * functional pipestat (i.e. other than WT or TD)
  984. */
  985. if (ctx->data_index <= ctx->pipe_index)
  986. {
  987. ctx->data_index = ctx->pipe_index + 1;
  988. ctx->data_half = 0;
  989. }
  990. }
  991. ctx->pipe_index += 1;
  992. }
  993. return ERROR_OK;
  994. }
  995. static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  996. {
  997. target_t *target;
  998. armv4_5_common_t *armv4_5;
  999. arm7_9_common_t *arm7_9;
  1000. etmv1_tracemode_t tracemode;
  1001. target = get_current_target(cmd_ctx);
  1002. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1003. {
  1004. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1005. return ERROR_OK;
  1006. }
  1007. if (!arm7_9->etm_ctx)
  1008. {
  1009. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1010. return ERROR_OK;
  1011. }
  1012. tracemode = arm7_9->etm_ctx->tracemode;
  1013. if (argc == 4)
  1014. {
  1015. /* what parts of data access are traced? */
  1016. if (strcmp(args[0], "none") == 0)
  1017. {
  1018. tracemode = ETMV1_TRACE_NONE;
  1019. }
  1020. else if (strcmp(args[0], "data") == 0)
  1021. {
  1022. tracemode = ETMV1_TRACE_DATA;
  1023. }
  1024. else if (strcmp(args[0], "address") == 0)
  1025. {
  1026. tracemode = ETMV1_TRACE_ADDR;
  1027. }
  1028. else if (strcmp(args[0], "all") == 0)
  1029. {
  1030. tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
  1031. }
  1032. else
  1033. {
  1034. command_print(cmd_ctx, "invalid option '%s'", args[0]);
  1035. return ERROR_OK;
  1036. }
  1037. switch (strtol(args[1], NULL, 0))
  1038. {
  1039. case 0:
  1040. tracemode |= ETMV1_CONTEXTID_NONE;
  1041. break;
  1042. case 8:
  1043. tracemode |= ETMV1_CONTEXTID_8;
  1044. break;
  1045. case 16:
  1046. tracemode |= ETMV1_CONTEXTID_16;
  1047. break;
  1048. case 32:
  1049. tracemode |= ETMV1_CONTEXTID_32;
  1050. break;
  1051. default:
  1052. command_print(cmd_ctx, "invalid option '%s'", args[1]);
  1053. return ERROR_OK;
  1054. }
  1055. if (strcmp(args[2], "enable") == 0)
  1056. {
  1057. tracemode |= ETMV1_CYCLE_ACCURATE;
  1058. }
  1059. else if (strcmp(args[2], "disable") == 0)
  1060. {
  1061. tracemode |= 0;
  1062. }
  1063. else
  1064. {
  1065. command_print(cmd_ctx, "invalid option '%s'", args[2]);
  1066. return ERROR_OK;
  1067. }
  1068. if (strcmp(args[3], "enable") == 0)
  1069. {
  1070. tracemode |= ETMV1_BRANCH_OUTPUT;
  1071. }
  1072. else if (strcmp(args[3], "disable") == 0)
  1073. {
  1074. tracemode |= 0;
  1075. }
  1076. else
  1077. {
  1078. command_print(cmd_ctx, "invalid option '%s'", args[2]);
  1079. return ERROR_OK;
  1080. }
  1081. /* IGNORED:
  1082. * - CPRT tracing (coprocessor register transfers)
  1083. * - debug request (causes debug entry on trigger)
  1084. * - stall on FIFOFULL (preventing tracedata lossage)
  1085. */
  1086. }
  1087. else if (argc != 0)
  1088. {
  1089. command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
  1090. return ERROR_OK;
  1091. }
  1092. command_print(cmd_ctx, "current tracemode configuration:");
  1093. switch (tracemode & ETMV1_TRACE_MASK)
  1094. {
  1095. case ETMV1_TRACE_NONE:
  1096. command_print(cmd_ctx, "data tracing: none");
  1097. break;
  1098. case ETMV1_TRACE_DATA:
  1099. command_print(cmd_ctx, "data tracing: data only");
  1100. break;
  1101. case ETMV1_TRACE_ADDR:
  1102. command_print(cmd_ctx, "data tracing: address only");
  1103. break;
  1104. case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
  1105. command_print(cmd_ctx, "data tracing: address and data");
  1106. break;
  1107. }
  1108. switch (tracemode & ETMV1_CONTEXTID_MASK)
  1109. {
  1110. case ETMV1_CONTEXTID_NONE:
  1111. command_print(cmd_ctx, "contextid tracing: none");
  1112. break;
  1113. case ETMV1_CONTEXTID_8:
  1114. command_print(cmd_ctx, "contextid tracing: 8 bit");
  1115. break;
  1116. case ETMV1_CONTEXTID_16:
  1117. command_print(cmd_ctx, "contextid tracing: 16 bit");
  1118. break;
  1119. case ETMV1_CONTEXTID_32:
  1120. command_print(cmd_ctx, "contextid tracing: 32 bit");
  1121. break;
  1122. }
  1123. if (tracemode & ETMV1_CYCLE_ACCURATE)
  1124. {
  1125. command_print(cmd_ctx, "cycle-accurate tracing enabled");
  1126. }
  1127. else
  1128. {
  1129. command_print(cmd_ctx, "cycle-accurate tracing disabled");
  1130. }
  1131. if (tracemode & ETMV1_BRANCH_OUTPUT)
  1132. {
  1133. command_print(cmd_ctx, "full branch address output enabled");
  1134. }
  1135. else
  1136. {
  1137. command_print(cmd_ctx, "full branch address output disabled");
  1138. }
  1139. /* only update ETM_CTRL register if tracemode changed */
  1140. if (arm7_9->etm_ctx->tracemode != tracemode)
  1141. {
  1142. reg_t *etm_ctrl_reg;
  1143. etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
  1144. if (!etm_ctrl_reg)
  1145. return ERROR_OK;
  1146. etm_get_reg(etm_ctrl_reg);
  1147. buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
  1148. buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
  1149. buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
  1150. buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
  1151. etm_store_reg(etm_ctrl_reg);
  1152. arm7_9->etm_ctx->tracemode = tracemode;
  1153. /* invalidate old trace data */
  1154. arm7_9->etm_ctx->capture_status = TRACE_IDLE;
  1155. if (arm7_9->etm_ctx->trace_depth > 0)
  1156. {
  1157. free(arm7_9->etm_ctx->trace_data);
  1158. arm7_9->etm_ctx->trace_data = NULL;
  1159. }
  1160. arm7_9->etm_ctx->trace_depth = 0;
  1161. }
  1162. return ERROR_OK;
  1163. }
  1164. static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1165. {
  1166. target_t *target;
  1167. armv4_5_common_t *armv4_5;
  1168. arm7_9_common_t *arm7_9;
  1169. etm_portmode_t portmode = 0x0;
  1170. etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
  1171. int i;
  1172. if (argc != 5)
  1173. {
  1174. free(etm_ctx);
  1175. return ERROR_COMMAND_SYNTAX_ERROR;
  1176. }
  1177. target = get_target(args[0]);
  1178. if (!target)
  1179. {
  1180. LOG_ERROR("target '%s' not defined", args[0]);
  1181. free(etm_ctx);
  1182. return ERROR_FAIL;
  1183. }
  1184. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1185. {
  1186. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1187. free(etm_ctx);
  1188. return ERROR_FAIL;
  1189. }
  1190. switch (strtoul(args[1], NULL, 0))
  1191. {
  1192. case 4:
  1193. portmode |= ETM_PORT_4BIT;
  1194. break;
  1195. case 8:
  1196. portmode |= ETM_PORT_8BIT;
  1197. break;
  1198. case 16:
  1199. portmode |= ETM_PORT_16BIT;
  1200. break;
  1201. default:
  1202. command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
  1203. free(etm_ctx);
  1204. return ERROR_FAIL;
  1205. }
  1206. if (strcmp("normal", args[2]) == 0)
  1207. {
  1208. portmode |= ETM_PORT_NORMAL;
  1209. }
  1210. else if (strcmp("multiplexed", args[2]) == 0)
  1211. {
  1212. portmode |= ETM_PORT_MUXED;
  1213. }
  1214. else if (strcmp("demultiplexed", args[2]) == 0)
  1215. {
  1216. portmode |= ETM_PORT_DEMUXED;
  1217. }
  1218. else
  1219. {
  1220. command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
  1221. free(etm_ctx);
  1222. return ERROR_FAIL;
  1223. }
  1224. if (strcmp("half", args[3]) == 0)
  1225. {
  1226. portmode |= ETM_PORT_HALF_CLOCK;
  1227. }
  1228. else if (strcmp("full", args[3]) == 0)
  1229. {
  1230. portmode |= ETM_PORT_FULL_CLOCK;
  1231. }
  1232. else
  1233. {
  1234. command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
  1235. free(etm_ctx);
  1236. return ERROR_FAIL;
  1237. }
  1238. for (i = 0; etm_capture_drivers[i]; i++)
  1239. {
  1240. if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
  1241. {
  1242. int retval;
  1243. if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
  1244. {
  1245. free(etm_ctx);
  1246. return retval;
  1247. }
  1248. etm_ctx->capture_driver = etm_capture_drivers[i];
  1249. break;
  1250. }
  1251. }
  1252. if (!etm_capture_drivers[i])
  1253. {
  1254. /* no supported capture driver found, don't register an ETM */
  1255. free(etm_ctx);
  1256. LOG_ERROR("trace capture driver '%s' not found", args[4]);
  1257. return ERROR_FAIL;
  1258. }
  1259. etm_ctx->target = target;
  1260. etm_ctx->trigger_percent = 50;
  1261. etm_ctx->trace_data = NULL;
  1262. etm_ctx->trace_depth = 0;
  1263. etm_ctx->portmode = portmode;
  1264. etm_ctx->tracemode = 0x0;
  1265. etm_ctx->core_state = ARMV4_5_STATE_ARM;
  1266. etm_ctx->image = NULL;
  1267. etm_ctx->pipe_index = 0;
  1268. etm_ctx->data_index = 0;
  1269. etm_ctx->current_pc = 0x0;
  1270. etm_ctx->pc_ok = 0;
  1271. etm_ctx->last_branch = 0x0;
  1272. etm_ctx->last_branch_reason = 0x0;
  1273. etm_ctx->last_ptr = 0x0;
  1274. etm_ctx->ptr_ok = 0x0;
  1275. etm_ctx->last_instruction = 0;
  1276. arm7_9->etm_ctx = etm_ctx;
  1277. return etm_register_user_commands(cmd_ctx);
  1278. }
  1279. static int handle_etm_info_command(struct command_context_s *cmd_ctx,
  1280. char *cmd, char **args, int argc)
  1281. {
  1282. target_t *target;
  1283. armv4_5_common_t *armv4_5;
  1284. arm7_9_common_t *arm7_9;
  1285. etm_context_t *etm;
  1286. reg_t *etm_sys_config_reg;
  1287. int max_port_size;
  1288. target = get_current_target(cmd_ctx);
  1289. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1290. {
  1291. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1292. return ERROR_OK;
  1293. }
  1294. etm = arm7_9->etm_ctx;
  1295. if (!etm)
  1296. {
  1297. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1298. return ERROR_OK;
  1299. }
  1300. command_print(cmd_ctx, "ETM v%d.%d",
  1301. etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
  1302. command_print(cmd_ctx, "pairs of address comparators: %i",
  1303. (int) (etm->config >> 0) & 0x0f);
  1304. command_print(cmd_ctx, "data comparators: %i",
  1305. (int) (etm->config >> 4) & 0x0f);
  1306. command_print(cmd_ctx, "memory map decoders: %i",
  1307. (int) (etm->config >> 8) & 0x1f);
  1308. command_print(cmd_ctx, "number of counters: %i",
  1309. (int) (etm->config >> 13) & 0x07);
  1310. command_print(cmd_ctx, "sequencer %spresent",
  1311. (int) (etm->config & (1 << 16)) ? "" : "not ");
  1312. command_print(cmd_ctx, "number of ext. inputs: %i",
  1313. (int) (etm->config >> 17) & 0x07);
  1314. command_print(cmd_ctx, "number of ext. outputs: %i",
  1315. (int) (etm->config >> 20) & 0x07);
  1316. command_print(cmd_ctx, "FIFO full %spresent",
  1317. (int) (etm->config & (1 << 23)) ? "" : "not ");
  1318. if (etm->bcd_vers < 0x20)
  1319. command_print(cmd_ctx, "protocol version: %i",
  1320. (int) (etm->config >> 28) & 0x07);
  1321. else {
  1322. command_print(cmd_ctx, "trace start/stop %spresent",
  1323. (etm->config & (1 << 26)) ? "" : "not ");
  1324. command_print(cmd_ctx, "number of context comparators: %i",
  1325. (int) (etm->config >> 24) & 0x03);
  1326. }
  1327. /* SYS_CONFIG isn't present before ETMv1.2 */
  1328. etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
  1329. if (!etm_sys_config_reg)
  1330. return ERROR_OK;
  1331. etm_get_reg(etm_sys_config_reg);
  1332. switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
  1333. {
  1334. case 0:
  1335. max_port_size = 4;
  1336. break;
  1337. case 1:
  1338. max_port_size = 8;
  1339. break;
  1340. case 2:
  1341. max_port_size = 16;
  1342. break;
  1343. default:
  1344. LOG_ERROR("Illegal max_port_size");
  1345. exit(-1);
  1346. }
  1347. command_print(cmd_ctx, "max. port size: %i", max_port_size);
  1348. command_print(cmd_ctx, "half-rate clocking %ssupported",
  1349. (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
  1350. command_print(cmd_ctx, "full-rate clocking %ssupported",
  1351. (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
  1352. command_print(cmd_ctx, "normal trace format %ssupported",
  1353. (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
  1354. command_print(cmd_ctx, "multiplex trace format %ssupported",
  1355. (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
  1356. command_print(cmd_ctx, "demultiplex trace format %ssupported",
  1357. (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
  1358. command_print(cmd_ctx, "FIFO full %ssupported",
  1359. (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
  1360. return ERROR_OK;
  1361. }
  1362. static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1363. {
  1364. target_t *target;
  1365. armv4_5_common_t *armv4_5;
  1366. arm7_9_common_t *arm7_9;
  1367. etm_context_t *etm;
  1368. trace_status_t trace_status;
  1369. target = get_current_target(cmd_ctx);
  1370. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1371. {
  1372. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1373. return ERROR_OK;
  1374. }
  1375. if (!arm7_9->etm_ctx)
  1376. {
  1377. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1378. return ERROR_OK;
  1379. }
  1380. etm = arm7_9->etm_ctx;
  1381. /* ETM status */
  1382. if (etm->bcd_vers >= 0x11) {
  1383. reg_t *reg;
  1384. reg = etm_reg_lookup(etm, ETM_STATUS);
  1385. if (!reg)
  1386. return ERROR_OK;
  1387. if (etm_get_reg(reg) == ERROR_OK) {
  1388. unsigned s = buf_get_u32(reg->value, 0, reg->size);
  1389. command_print(cmd_ctx, "etm: %s%s%s%s",
  1390. /* bit(1) == progbit */
  1391. (etm->bcd_vers >= 0x12)
  1392. ? ((s & (1 << 1))
  1393. ? "disabled" : "enabled")
  1394. : "?",
  1395. ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
  1396. ? " triggered" : "",
  1397. ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
  1398. ? " start/stop" : "",
  1399. ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
  1400. ? " untraced-overflow" : "");
  1401. } /* else ignore and try showing trace port status */
  1402. }
  1403. /* Trace Port Driver status */
  1404. trace_status = etm->capture_driver->status(etm);
  1405. if (trace_status == TRACE_IDLE)
  1406. {
  1407. command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
  1408. }
  1409. else
  1410. {
  1411. static char *completed = " completed";
  1412. static char *running = " is running";
  1413. static char *overflowed = ", overflowed";
  1414. static char *triggered = ", triggered";
  1415. command_print(cmd_ctx, "%s: trace collection%s%s%s",
  1416. etm->capture_driver->name,
  1417. (trace_status & TRACE_RUNNING) ? running : completed,
  1418. (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
  1419. (trace_status & TRACE_TRIGGERED) ? triggered : "");
  1420. if (etm->trace_depth > 0)
  1421. {
  1422. command_print(cmd_ctx, "%i frames of trace data read",
  1423. (int)(etm->trace_depth));
  1424. }
  1425. }
  1426. return ERROR_OK;
  1427. }
  1428. static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1429. {
  1430. target_t *target;
  1431. armv4_5_common_t *armv4_5;
  1432. arm7_9_common_t *arm7_9;
  1433. etm_context_t *etm_ctx;
  1434. if (argc < 1)
  1435. {
  1436. command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
  1437. return ERROR_OK;
  1438. }
  1439. target = get_current_target(cmd_ctx);
  1440. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1441. {
  1442. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1443. return ERROR_OK;
  1444. }
  1445. if (!(etm_ctx = arm7_9->etm_ctx))
  1446. {
  1447. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1448. return ERROR_OK;
  1449. }
  1450. if (etm_ctx->image)
  1451. {
  1452. image_close(etm_ctx->image);
  1453. free(etm_ctx->image);
  1454. command_print(cmd_ctx, "previously loaded image found and closed");
  1455. }
  1456. etm_ctx->image = malloc(sizeof(image_t));
  1457. etm_ctx->image->base_address_set = 0;
  1458. etm_ctx->image->start_address_set = 0;
  1459. /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
  1460. if (argc >= 2)
  1461. {
  1462. etm_ctx->image->base_address_set = 1;
  1463. etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
  1464. }
  1465. else
  1466. {
  1467. etm_ctx->image->base_address_set = 0;
  1468. }
  1469. if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
  1470. {
  1471. free(etm_ctx->image);
  1472. etm_ctx->image = NULL;
  1473. return ERROR_OK;
  1474. }
  1475. return ERROR_OK;
  1476. }
  1477. static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1478. {
  1479. fileio_t file;
  1480. target_t *target;
  1481. armv4_5_common_t *armv4_5;
  1482. arm7_9_common_t *arm7_9;
  1483. etm_context_t *etm_ctx;
  1484. uint32_t i;
  1485. if (argc != 1)
  1486. {
  1487. command_print(cmd_ctx, "usage: etm dump <file>");
  1488. return ERROR_OK;
  1489. }
  1490. target = get_current_target(cmd_ctx);
  1491. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1492. {
  1493. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1494. return ERROR_OK;
  1495. }
  1496. if (!(etm_ctx = arm7_9->etm_ctx))
  1497. {
  1498. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1499. return ERROR_OK;
  1500. }
  1501. if (etm_ctx->capture_driver->status == TRACE_IDLE)
  1502. {
  1503. command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
  1504. return ERROR_OK;
  1505. }
  1506. if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
  1507. {
  1508. /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
  1509. command_print(cmd_ctx, "trace capture not completed");
  1510. return ERROR_OK;
  1511. }
  1512. /* read the trace data if it wasn't read already */
  1513. if (etm_ctx->trace_depth == 0)
  1514. etm_ctx->capture_driver->read_trace(etm_ctx);
  1515. if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
  1516. {
  1517. return ERROR_OK;
  1518. }
  1519. fileio_write_u32(&file, etm_ctx->capture_status);
  1520. fileio_write_u32(&file, etm_ctx->portmode);
  1521. fileio_write_u32(&file, etm_ctx->tracemode);
  1522. fileio_write_u32(&file, etm_ctx->trace_depth);
  1523. for (i = 0; i < etm_ctx->trace_depth; i++)
  1524. {
  1525. fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
  1526. fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
  1527. fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
  1528. }
  1529. fileio_close(&file);
  1530. return ERROR_OK;
  1531. }
  1532. static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1533. {
  1534. fileio_t file;
  1535. target_t *target;
  1536. armv4_5_common_t *armv4_5;
  1537. arm7_9_common_t *arm7_9;
  1538. etm_context_t *etm_ctx;
  1539. uint32_t i;
  1540. if (argc != 1)
  1541. {
  1542. command_print(cmd_ctx, "usage: etm load <file>");
  1543. return ERROR_OK;
  1544. }
  1545. target = get_current_target(cmd_ctx);
  1546. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1547. {
  1548. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1549. return ERROR_OK;
  1550. }
  1551. if (!(etm_ctx = arm7_9->etm_ctx))
  1552. {
  1553. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1554. return ERROR_OK;
  1555. }
  1556. if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
  1557. {
  1558. command_print(cmd_ctx, "trace capture running, stop first");
  1559. return ERROR_OK;
  1560. }
  1561. if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
  1562. {
  1563. return ERROR_OK;
  1564. }
  1565. if (file.size % 4)
  1566. {
  1567. command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
  1568. fileio_close(&file);
  1569. return ERROR_OK;
  1570. }
  1571. if (etm_ctx->trace_depth > 0)
  1572. {
  1573. free(etm_ctx->trace_data);
  1574. etm_ctx->trace_data = NULL;
  1575. }
  1576. {
  1577. uint32_t tmp;
  1578. fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
  1579. fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
  1580. fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
  1581. fileio_read_u32(&file, &etm_ctx->trace_depth);
  1582. }
  1583. etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
  1584. if (etm_ctx->trace_data == NULL)
  1585. {
  1586. command_print(cmd_ctx, "not enough memory to perform operation");
  1587. fileio_close(&file);
  1588. return ERROR_OK;
  1589. }
  1590. for (i = 0; i < etm_ctx->trace_depth; i++)
  1591. {
  1592. uint32_t pipestat, packet, flags;
  1593. fileio_read_u32(&file, &pipestat);
  1594. fileio_read_u32(&file, &packet);
  1595. fileio_read_u32(&file, &flags);
  1596. etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
  1597. etm_ctx->trace_data[i].packet = packet & 0xffff;
  1598. etm_ctx->trace_data[i].flags = flags;
  1599. }
  1600. fileio_close(&file);
  1601. return ERROR_OK;
  1602. }
  1603. static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1604. {
  1605. target_t *target;
  1606. armv4_5_common_t *armv4_5;
  1607. arm7_9_common_t *arm7_9;
  1608. etm_context_t *etm_ctx;
  1609. target = get_current_target(cmd_ctx);
  1610. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1611. {
  1612. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1613. return ERROR_OK;
  1614. }
  1615. if (!(etm_ctx = arm7_9->etm_ctx))
  1616. {
  1617. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1618. return ERROR_OK;
  1619. }
  1620. if (argc > 0)
  1621. {
  1622. uint32_t new_value = strtoul(args[0], NULL, 0);
  1623. if ((new_value < 2) || (new_value > 100))
  1624. {
  1625. command_print(cmd_ctx, "valid settings are 2%% to 100%%");
  1626. }
  1627. else
  1628. {
  1629. etm_ctx->trigger_percent = new_value;
  1630. }
  1631. }
  1632. command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
  1633. return ERROR_OK;
  1634. }
  1635. static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1636. {
  1637. target_t *target;
  1638. armv4_5_common_t *armv4_5;
  1639. arm7_9_common_t *arm7_9;
  1640. etm_context_t *etm_ctx;
  1641. reg_t *etm_ctrl_reg;
  1642. target = get_current_target(cmd_ctx);
  1643. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1644. {
  1645. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1646. return ERROR_OK;
  1647. }
  1648. if (!(etm_ctx = arm7_9->etm_ctx))
  1649. {
  1650. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1651. return ERROR_OK;
  1652. }
  1653. /* invalidate old tracing data */
  1654. arm7_9->etm_ctx->capture_status = TRACE_IDLE;
  1655. if (arm7_9->etm_ctx->trace_depth > 0)
  1656. {
  1657. free(arm7_9->etm_ctx->trace_data);
  1658. arm7_9->etm_ctx->trace_data = NULL;
  1659. }
  1660. arm7_9->etm_ctx->trace_depth = 0;
  1661. etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
  1662. if (!etm_ctrl_reg)
  1663. return ERROR_OK;
  1664. etm_get_reg(etm_ctrl_reg);
  1665. /* Clear programming bit (10), set port selection bit (11) */
  1666. buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
  1667. etm_store_reg(etm_ctrl_reg);
  1668. jtag_execute_queue();
  1669. etm_ctx->capture_driver->start_capture(etm_ctx);
  1670. return ERROR_OK;
  1671. }
  1672. static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1673. {
  1674. target_t *target;
  1675. armv4_5_common_t *armv4_5;
  1676. arm7_9_common_t *arm7_9;
  1677. etm_context_t *etm_ctx;
  1678. reg_t *etm_ctrl_reg;
  1679. target = get_current_target(cmd_ctx);
  1680. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1681. {
  1682. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1683. return ERROR_OK;
  1684. }
  1685. if (!(etm_ctx = arm7_9->etm_ctx))
  1686. {
  1687. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1688. return ERROR_OK;
  1689. }
  1690. etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
  1691. if (!etm_ctrl_reg)
  1692. return ERROR_OK;
  1693. etm_get_reg(etm_ctrl_reg);
  1694. /* Set programming bit (10), clear port selection bit (11) */
  1695. buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
  1696. etm_store_reg(etm_ctrl_reg);
  1697. jtag_execute_queue();
  1698. etm_ctx->capture_driver->stop_capture(etm_ctx);
  1699. return ERROR_OK;
  1700. }
  1701. static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1702. {
  1703. target_t *target;
  1704. armv4_5_common_t *armv4_5;
  1705. arm7_9_common_t *arm7_9;
  1706. etm_context_t *etm_ctx;
  1707. int retval;
  1708. target = get_current_target(cmd_ctx);
  1709. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1710. {
  1711. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1712. return ERROR_OK;
  1713. }
  1714. if (!(etm_ctx = arm7_9->etm_ctx))
  1715. {
  1716. command_print(cmd_ctx, "current target doesn't have an ETM configured");
  1717. return ERROR_OK;
  1718. }
  1719. if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
  1720. {
  1721. switch (retval)
  1722. {
  1723. case ERROR_ETM_ANALYSIS_FAILED:
  1724. command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
  1725. break;
  1726. case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
  1727. command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
  1728. break;
  1729. case ERROR_TRACE_IMAGE_UNAVAILABLE:
  1730. command_print(cmd_ctx, "no image available for trace analysis");
  1731. break;
  1732. default:
  1733. command_print(cmd_ctx, "unknown error: %i", retval);
  1734. }
  1735. }
  1736. return ERROR_OK;
  1737. }
  1738. int etm_register_commands(struct command_context_s *cmd_ctx)
  1739. {
  1740. etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
  1741. register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
  1742. COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
  1743. return ERROR_OK;
  1744. }
  1745. static int etm_register_user_commands(struct command_context_s *cmd_ctx)
  1746. {
  1747. register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
  1748. COMMAND_EXEC, "configure/display trace mode: "
  1749. "<none | data | address | all> "
  1750. "<context_id_bits> <cycle_accurate> <branch_output>");
  1751. register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
  1752. COMMAND_EXEC, "display info about the current target's ETM");
  1753. register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
  1754. COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
  1755. register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
  1756. COMMAND_EXEC, "display current target's ETM status");
  1757. register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
  1758. COMMAND_EXEC, "start ETM trace collection");
  1759. register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
  1760. COMMAND_EXEC, "stop ETM trace collection");
  1761. register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
  1762. COMMAND_EXEC, "anaylze collected ETM trace");
  1763. register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
  1764. COMMAND_EXEC, "load image from <file> [base address]");
  1765. register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
  1766. COMMAND_EXEC, "dump captured trace data <file>");
  1767. register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
  1768. COMMAND_EXEC, "load trace data for analysis <file>");
  1769. return ERROR_OK;
  1770. }