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64 lines
2.4 KiB

  1. ################################################################################
  2. # Atmel AT91SAM9263-EK eval board
  3. ################################################################################
  4. source [find mem_helper.tcl]
  5. source [find target/at91sam9263.cfg]
  6. uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
  7. uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
  8. uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
  9. uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
  10. # By default S1 is open and this means that NTRST is not connected.
  11. # The reset_config in target/at91sam9263.cfg is overridden here.
  12. # (or S1 must be populated with a 0 Ohm resistor)
  13. reset_config srst_only
  14. scan_chain
  15. $_TARGETNAME configure -event gdb-attach { reset init }
  16. $_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
  17. $_TARGETNAME configure -event reset-start { at91sam9_reset_start }
  18. proc at91sam9263ek_reset_init { } {
  19. set config(master_pll_div) 14
  20. set config(master_pll_mul) 171
  21. set val [expr $::AT91_WDT_WDV] ;# Counter Value
  22. set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
  23. set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
  24. set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
  25. set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
  26. set config(wdt_mr_val) $val
  27. set config(sdram_piod) 1
  28. ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
  29. set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
  30. set val [expr $::AT91_MATRIX_EBI0_DBPUC]
  31. set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
  32. set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
  33. set config(matrix_ebicsa_val) $val
  34. ;# SDRAMC_CR - Configuration register
  35. set val [expr $::AT91_SDRAMC_NC_9]
  36. set val [expr ($val | $::AT91_SDRAMC_NR_13)]
  37. set val [expr ($val | $::AT91_SDRAMC_NB_4)]
  38. set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
  39. set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
  40. set val [expr ($val | (1 << 8))] ;# Write Recovery Delay
  41. set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
  42. set val [expr ($val | (2 << 16))] ;# Row Precharge Delay
  43. set val [expr ($val | (2 << 20))] ;# Row to Column Delay
  44. set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
  45. set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay
  46. set config(sdram_cr_val) $val
  47. set config(sdram_tr_val) 0x13c
  48. set config(sdram_base) $::AT91_CHIPSELECT_1
  49. at91sam9_reset_init $config
  50. }