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  1. #################################################################################################
  2. # #
  3. # Author: Lars Poeschel (larsi@wh2.tu-dresden.de) #
  4. # Generated for In-Circuit ICnova SAM9G45 SODIMM #
  5. # http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova #
  6. # #
  7. #################################################################################################
  8. # FIXME use some standard target config, maybe create one from this
  9. #
  10. # source [find target/...cfg]
  11. source [find target/at91sam9g45.cfg]
  12. # Set reset type.
  13. # reset_config trst_and_srst
  14. # adapter_nsrst_delay 200
  15. # jtag_ntrst_delay 200
  16. # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
  17. # AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
  18. # some powerful features, we want to have a special function that handles "reset init". To do this we declare
  19. # an event handler where these special activities can take place.
  20. scan_chain
  21. $_TARGETNAME configure -event reset-init {at91sam9g45_init}
  22. # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
  23. # Slow-speed oscillator enabled at reset, so run jtag speed slow.
  24. $_TARGETNAME configure -event reset-start {at91sam9g45_start}
  25. # NandFlash configuration and definition
  26. # Future TBD
  27. # Flash configuration
  28. # flash bank cfi <base> <size> <chip width> <bus width> <target#>
  29. set _FLASHNAME $_CHIPNAME.flash
  30. # set _NANDNAME $_CHIPNAME.nand
  31. flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
  32. # nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800
  33. proc read_register {register} {
  34. set result ""
  35. mem2array result 32 $register 1
  36. return $result(0)
  37. }
  38. proc at91sam9g45_start { } {
  39. # Make sure that the the jtag is running slow, since there are a number of different ways the board
  40. # can be configured coming into this state that can cause communication problems with the jtag
  41. # adapter. Also since this call can be made following a "reset init" where fast memory accesses
  42. # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
  43. # jtag speed without causing GDB keep alive problem.
  44. arm7_9 fast_memory_access disable
  45. # Slow-speed oscillator enabled at reset, so run jtag speed slow.
  46. adapter_khz 4
  47. # Make sure processor is halted, or error will result in following steps.
  48. halt
  49. wait_halt 10000
  50. # RSTC_MR : enable user reset.
  51. mww 0xfffffd08 0xa5000501
  52. }
  53. proc at91sam9g45_init { } {
  54. # At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
  55. # a number of steps that must be carefully performed. The process outline below follows the
  56. # recommended procedure outlined in the AT91SAM9G45 technical manual.
  57. #
  58. # Several key and very important things to keep in mind:
  59. # The SDRAM parts used currently on the board are -75 grade parts. This
  60. # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
  61. # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
  62. # Make sure processor is halted, or error will result in following steps.
  63. halt
  64. # RSTC_MR : enable user reset.
  65. mww 0xfffffd08 0xa5000501
  66. # WDT_MR : disable watchdog.
  67. mww 0xfffffd44 0x00008000
  68. # Enable the main 15.000 MHz oscillator in CKGR_MOR register.
  69. # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
  70. mww 0xfffffc20 0x00004001
  71. while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
  72. # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
  73. # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
  74. #mww 0xfffffc28 0x202a3f01
  75. mww 0xfffffc28 0x20c73f03
  76. while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
  77. # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
  78. # Wait for MCKRDY signal from PMC_SR to assert.
  79. #mww 0xfffffc30 0x00000101
  80. mww 0xfffffc30 0x00001301
  81. while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
  82. # Now change PMC_MCKR register to select PLLA.
  83. # Wait for MCKRDY signal from PMC_SR to assert.
  84. mww 0xfffffc30 0x00001302
  85. while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
  86. # Processor and master clocks are now operating and stable at maximum frequency possible:
  87. # -> MCLK = 132.096 MHz
  88. # -> PCLK = 396.288 MHz
  89. # Switch over to adaptive clocking.
  90. adapter_khz 6000
  91. # Enable faster DCC downloads.
  92. arm7_9 dcc_downloads enable
  93. # To be able to use external SDRAM, several peripheral configuration registers must
  94. # be modified. The first change is made to PIO_ASR to select peripheral functions
  95. # for D15 through D31. The second change is made to the PIO_PDR register to disable
  96. # this for D15 through D31.
  97. # mww 0xfffff870 0xffff0000
  98. # mww 0xfffff804 0xffff0000
  99. # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
  100. # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
  101. # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
  102. # mww 0xffffef1c 0x000100a
  103. # The ICnova SAM9G45 SODIMM has built-in NandFlash. The exact physical timing characteristics
  104. # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
  105. # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
  106. # mww 0xffffec30 0x00020002
  107. # mww 0xffffec34 0x04040404
  108. # mww 0xffffec38 0x00070007
  109. # mww 0xffffec3c 0x00030003
  110. # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
  111. # nand probe 0
  112. # SMC_SETUP0 : Setup SMC for NOR Flash
  113. mww 0xffffe800 0x0012000a
  114. # SMC_PULSE0
  115. mww 0xffffe804 0x3b38343b
  116. # SMC_CYCLE0
  117. mww 0xffffe808 0x003f003f
  118. # SMC_MODE0
  119. mww 0xffffe80c 0x00001000
  120. # Identify flash bank 0
  121. flash probe 0
  122. # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
  123. # are based on 2 x Samsung K4T51083QG memory.
  124. # 0. Enable DDR2 Clock
  125. mww 0xfffffc00 0x4
  126. # 1. Program memory device type
  127. # 1.1 configure the DDR controller
  128. mww 0xffffe620 0x16
  129. # 1.2 program the DDR controller
  130. mww 0xffffe608 0x3d
  131. # 2. program memory device features
  132. # 2.1 assume timings for 7.5ns min clock period
  133. mww 0xffffe60c 0x21128226
  134. # 2.2 pSDDRC->HDDRSDRC2_T1PR
  135. mww 0xffffe610 0x02c8100e
  136. # 2.3 pSDDRC->HDDRSDRC2_T2PR
  137. mww 0xffffe614 0x01000702
  138. # 3. NOP
  139. mww 0xffffe600 0x1
  140. mww 0x70000000 0x1
  141. # 3.1 delay 200us
  142. sleep 1
  143. # jim tcl alternative: after ms
  144. # after 0.2
  145. # 4. NOP
  146. mww 0xffffe600 0x1
  147. mww 0x70000000 0x1
  148. # 4.1 delay 400ns
  149. # 5. set all bank precharge
  150. mww 0xffffe600 0x2
  151. mww 0x70000000 0x1
  152. # 5.1 delay 400ns
  153. # 6. set EMR operation (EMRS2)
  154. mww 0xffffe600 0x5
  155. mww 0x74000000 0x1
  156. # 6.1 delay 2 cycles
  157. # 7. set EMR operation (EMRS3)
  158. mww 0xffffe600 0x5
  159. mww 0x76000000 0x1
  160. # 7.1 delay 2 cycles
  161. # 8. set EMR operation (EMRS1)
  162. mww 0xffffe600 0x5
  163. mww 0x72000000 0x1
  164. # 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s)
  165. sleep 1
  166. # 9. Enable DLL Reset (set DLL bit)
  167. set CR [expr [read_register 0xffffe608] | 0x80]
  168. mww 0xffffe608 $CR
  169. # 10. mode register cycle to reset the DLL
  170. mww 0xffffe600 0x5
  171. mww 0x70000000 0x1
  172. # 10.1 delay 2 cycles
  173. # 11. set all bank precharge
  174. mww 0xffffe600 0x2
  175. mww 0x70000000 0x1
  176. # 11.1 delay 400 ns
  177. # 12. two auto-refresh (CBR) cycles are provided.
  178. mww 0xffffe600 0x4
  179. mww 0x70000000 0x1
  180. # 12.1 delay 10 cycles
  181. # 12.2 2nd cycle (schreiben des Mode Register sparen wir uns)
  182. mww 0x70000000 0x1
  183. # 12.3 delay 10 cycles
  184. # 13. disable DLL reset (clear DLL bit)
  185. set CR [expr [read_register 0xffffe608] & 0xffffff7f]
  186. mww 0xffffe608 $CR
  187. # 14. mode register set cycle
  188. mww 0xffffe600 0x3
  189. mww 0x70000000 0x1
  190. # 15. program OCD field (set OCD bits)
  191. set CR [expr [read_register 0xffffe608] | 0x7000]
  192. mww 0xffffe608 $CR
  193. # 16. (EMRS1)
  194. mww 0xffffe600 0x5
  195. mww 0x72000000 0x1
  196. # 16.1 delay 2 cycles
  197. # 17. disable OCD field (clear OCD bits)
  198. set CR [expr [read_register 0xffffe608] & 0xffff8fff]
  199. mww 0xffffe608 $CR
  200. # 18. (EMRS1)
  201. mww 0xffffe600 0x5
  202. mww 0x76000000 0x1
  203. # 18.1 delay 2 cycles
  204. # 19. normal mode command
  205. mww 0xffffe600 0x0
  206. mww 0x70000000 0x1
  207. # 20. perform write to any address
  208. #mww 0x70000000 0x1
  209. # 21. write refresh rate into the count field of the refresh rate register
  210. mww 0xffffe604 0x24b
  211. # 21.1 delay (500 * 6 cycles)
  212. arm7_9 fast_memory_access enable
  213. }