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  1. # Configuration for the ST SPEAr310 Evaluation board
  2. # EVALSPEAr310 Rev. 2.0
  3. # http://www.st.com/spear
  4. #
  5. # Date: 2010-08-17
  6. # Author: Antonio Borneo <borneo.antonio@gmail.com>
  7. # The standard board has JTAG SRST not connected.
  8. # This script targets such boards using quirky code to bypass the issue.
  9. #
  10. # Check ST Application Note AN3321 on how to fix SRST on
  11. # the board, then use the script board/spear310evb20_mod.cfg
  12. source [find mem_helper.tcl]
  13. source [find target/spear3xx.cfg]
  14. source [find chip/st/spear/spear3xx_ddr.tcl]
  15. source [find chip/st/spear/spear3xx.tcl]
  16. arm7_9 dcc_downloads enable
  17. arm7_9 fast_memory_access enable
  18. # CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
  19. set _FLASHNAME0 $_CHIPNAME.pnor
  20. flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
  21. # Serial NOR on SMI CS0. 8Mbyte.
  22. set _FLASHNAME1 $_CHIPNAME.snor
  23. flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  24. if { [info exists BOARD_HAS_SRST] } {
  25. # Modified board has SRST on JTAG connector
  26. reset_config trst_and_srst separate srst_gates_jtag \
  27. trst_push_pull srst_open_drain
  28. } else {
  29. # Standard board has no SRST on JTAG connector
  30. reset_config trst_only separate srst_gates_jtag trst_push_pull
  31. source [find chip/st/spear/quirk_no_srst.tcl]
  32. }
  33. $_TARGETNAME configure -event reset-init { spear310evb20_init }
  34. proc spear310evb20_init {} {
  35. reg pc 0xffff0020 ;# loop forever
  36. sp3xx_clock_default
  37. sp3xx_common_init
  38. sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
  39. sp310_init
  40. sp310_emi_init
  41. }