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159 lines
4.5 KiB

  1. # -------------------------------------------------------------------------
  2. # KaRo TX25 CPU Module on a StarterkitV base board
  3. # http://www.karo-electronics.com/tx25.html
  4. # -------------------------------------------------------------------------
  5. source [find tcl/target/imx25.cfg]
  6. #-------------------------------------------------------------------------
  7. # Declare Nand
  8. #-------------------------------------------------------------------------
  9. nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
  10. $_TARGETNAME configure -event gdb-attach { reset init }
  11. $_TARGETNAME configure -event reset-init { tx25_init }
  12. proc tx25_init { } {
  13. #-------------------------------------------------------------------------
  14. # AIPS setup - Only setup MPROTx registers. The PACR default values are good.
  15. # Set all MPROTx to be non-bufferable, trusted for R/W,
  16. # not forced to user-mode.
  17. #-------------------------------------------------------------------------
  18. mww 0x43f00000 0x77777777
  19. mww 0x43f00004 0x77777777
  20. mww 0x53f00000 0x77777777
  21. mww 0x53f00004 0x77777777
  22. sleep 100
  23. #-------------------------------------------------------------------------
  24. # MAX (Multi-Layer AHB Crossbar Switch) setup
  25. # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
  26. #-------------------------------------------------------------------------
  27. mww 0x43f04000 0x00043210
  28. mww 0x43f04100 0x00043210
  29. mww 0x43f04200 0x00043210
  30. mww 0x43f04300 0x00043210
  31. mww 0x43f04400 0x00043210
  32. # SGPCR - always park on last master
  33. mww 0x43f04010 0x10
  34. mww 0x43f04110 0x10
  35. mww 0x43f04210 0x10
  36. mww 0x43f04310 0x10
  37. mww 0x43f04410 0x10
  38. # MGPCR - restore default values
  39. mww 0x43f04800 0x0
  40. mww 0x43f04900 0x0
  41. mww 0x43f04a00 0x0
  42. mww 0x43f04b00 0x0
  43. mww 0x43f04c00 0x0
  44. # Configure M3IF registers
  45. # M3IF Control Register (M3IFCTL) for MX25
  46. # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
  47. # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
  48. # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
  49. # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
  50. # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
  51. # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
  52. # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
  53. # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
  54. # ----------
  55. # 0x00000001
  56. mww 0xb8003000 0x00000001
  57. #-------------------------------------------------------------------------
  58. # configure ARM CLK
  59. #-------------------------------------------------------------------------
  60. # Set the Clock CTL (HRM p. 355)
  61. mww 0x53F80008 0x20034000
  62. # Setup Clock Gating CTL 0-2 (HRM p. 357)
  63. mww 0x53F8000C 0x1fffffff
  64. mww 0x53F80010 0xffffffff
  65. mww 0x53F80014 0x000fdfff
  66. #-------------------------------------------------------------------------
  67. # SDRAM initialization
  68. #-------------------------------------------------------------------------
  69. # set to 3.3v SDRAM
  70. mww 0x43FAC454 0x00000800
  71. # reset (set up ESDMISC)
  72. mww 0xB8001010 0x00000002
  73. # Setup for SDRAM Bank 0
  74. #-------------------------------------------------------------------------
  75. # Write ESDCFG0
  76. mww 0xB8001004 0x00095728
  77. # CTL SMode = Precharge command
  78. mww 0xB8001000 0x92116480
  79. mww 0x80000400 0x00000000
  80. # CTL SMode = Auto Refresh command
  81. mww 0xB8001000 0xA2116480
  82. mww 0x80000000 0x0
  83. mww 0x80000000 0x0
  84. mww 0x80000000 0x0
  85. mww 0x80000000 0x0
  86. mww 0x80000000 0x0
  87. mww 0x80000000 0x0
  88. mww 0x80000000 0x0
  89. mww 0x80000000 0x0
  90. # CTL SMode = Load Mode Register command
  91. mww 0xB8001000 0xB2116480
  92. mwb 0x80000033 0x00
  93. # CTL SMode = normal
  94. mww 0xB8001000 0x82116480
  95. # Setup for SDRAM Bank 1
  96. #-------------------------------------------------------------------------
  97. # Write ESDCFG1
  98. mww 0xB800100C 0x00095728
  99. # CTL SMode = Precharge command
  100. mww 0xB8001008 0x92116480
  101. mww 0x90000400 0x00000000
  102. # CTL SMode = Auto Refresh command
  103. mww 0xB8001008 0xA2116480
  104. mww 0x90000000 0x00000000
  105. mww 0x90000000 0x00000000
  106. mww 0x90000000 0x00000000
  107. mww 0x90000000 0x00000000
  108. mww 0x90000000 0x00000000
  109. mww 0x90000000 0x00000000
  110. mww 0x90000000 0x00000000
  111. mww 0x90000000 0x00000000
  112. # CTL SMode = Load Mode Register command
  113. mww 0xB8001008 0xB2116480
  114. mwb 0x90000033 0x00
  115. # CTL SMode = normal
  116. mww 0xB8001008 0x82116480
  117. # GPIO configuration
  118. #-------------------------------------------------------------------------
  119. mww 0x43FAC02C 0x00000015
  120. mww 0x53FD0000 0x01000000
  121. mww 0x53FD0004 0x00000080
  122. }