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98 lines
3.7 KiB

  1. # Thanks to Pieter Conradie for this script!
  2. #
  3. # Unknown vendor board contains:
  4. #
  5. # Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
  6. # OSCSEL configured for internal RC oscillator (22 to 42 kHz)
  7. #
  8. # 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
  9. # 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
  10. ##################################################################
  11. # We add to the minimal configuration.
  12. source [find target/at91sam9260.cfg]
  13. $_TARGETNAME configure -event reset-start {
  14. # At reset CPU runs at 22 to 42 kHz.
  15. # JTAG Frequency must be 6 times slower.
  16. jtag_rclk 3
  17. halt
  18. # RSTC_MR : enable user reset, MMU may be enabled... use physical address
  19. mww phys 0xfffffd08 0xa5000501
  20. }
  21. $_TARGETNAME configure -event reset-init {
  22. mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
  23. mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
  24. sleep 20 ;# wait 20 ms
  25. mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
  26. sleep 10 ;# wait 10 ms
  27. mww 0xfffffc28 0x205dbf09 ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz
  28. sleep 20 ;# wait 20 ms
  29. mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
  30. sleep 10 ;# wait 10 ms
  31. mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
  32. sleep 10 ;# wait 10 ms
  33. # Increase JTAG Speed to 6 MHz if RCLK is not supported
  34. jtag_rclk 6000
  35. arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
  36. mww 0xffffec00 0x01020102 ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  37. mww 0xffffec04 0x09070806 ;# SMC_PULSE0
  38. mww 0xffffec08 0x000d000b ;# SMC_CYCLE0
  39. mww 0xffffec0c 0x00001003 ;# SMC_MODE0
  40. flash probe 0 ;# Identify flash bank 0
  41. mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
  42. mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
  43. mww 0xfffff860 0xffff0000 ;# PIO_PUDR : Disable D15..D31 pull-ups
  44. mww 0xffffef1c 0x00010102 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  45. # VDDIOMSEL set for +3V3 memory
  46. # Disable D0..D15 pull-ups
  47. mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  48. mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
  49. mww 0x20000000 0
  50. mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
  51. mww 0x20000000 0
  52. mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  53. mww 0x20000000 0
  54. mww 0xffffea00 0x4
  55. mww 0x20000000 0
  56. mww 0xffffea00 0x4
  57. mww 0x20000000 0
  58. mww 0xffffea00 0x4
  59. mww 0x20000000 0
  60. mww 0xffffea00 0x4
  61. mww 0x20000000 0
  62. mww 0xffffea00 0x4
  63. mww 0x20000000 0
  64. mww 0xffffea00 0x4
  65. mww 0x20000000 0
  66. mww 0xffffea00 0x4
  67. mww 0x20000000 0
  68. mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
  69. mww 0x20000000 0
  70. mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
  71. mww 0x20000000 0
  72. mww 0xffffea04 0x2a2 ;# SDRAMC_TR : Set refresh timer count to 7us
  73. }
  74. #####################
  75. # Flash configuration
  76. #####################
  77. #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
  78. set _FLASHNAME $_CHIPNAME.flash
  79. flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME