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51 lines
1.4 KiB

  1. #use combined on interfaces or targets that can't set TRST/SRST separately
  2. reset_config srst_only srst_pulls_trst
  3. if { [info exists CHIPNAME] } {
  4. set _CHIPNAME $CHIPNAME
  5. } else {
  6. set _CHIPNAME sam7x256
  7. }
  8. if { [info exists ENDIAN] } {
  9. set _ENDIAN $ENDIAN
  10. } else {
  11. set _ENDIAN little
  12. }
  13. if { [info exists CPUTAPID] } {
  14. set _CPUTAPID $CPUTAPID
  15. } else {
  16. set _CPUTAPID 0x3f0f0f0f
  17. }
  18. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  19. set _TARGETNAME $_CHIPNAME.cpu
  20. target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
  21. $_TARGETNAME configure -event reset-init {
  22. # disable watchdog
  23. mww 0xfffffd44 0x00008000
  24. # enable user reset
  25. mww 0xfffffd08 0xa5000001
  26. # CKGR_MOR : enable the main oscillator
  27. mww 0xfffffc20 0x00000601
  28. sleep 10
  29. # CKGR_PLLR: 96.1097 MHz
  30. mww 0xfffffc2c 0x00481c0e
  31. sleep 10
  32. # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
  33. mww 0xfffffc30 0x00000007
  34. sleep 10
  35. # MC_FMR: flash mode (FWS=1,FMCN=60)
  36. mww 0xffffff60 0x003c0100
  37. sleep 100
  38. }
  39. $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
  40. #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
  41. set _FLASHNAME $_CHIPNAME.flash
  42. flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432